CN203573956U - 晶体管 - Google Patents

晶体管 Download PDF

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CN203573956U
CN203573956U CN201190000074.5U CN201190000074U CN203573956U CN 203573956 U CN203573956 U CN 203573956U CN 201190000074 U CN201190000074 U CN 201190000074U CN 203573956 U CN203573956 U CN 203573956U
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transistor
dislocation
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尹海洲
朱慧珑
骆志炯
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Abstract

本实用新型涉及一种晶体管。本实用新型的晶体管包括：半导体衬底；形成在所述半导体衬底上的栅极电介质；形成在所述栅极电介质上的栅极；位于所述半导体衬底中、且分别在所述栅极两侧的源区和漏区，其中至少所述源区和漏区之一包含在平行于衬底表面的方向上排列的多个位错；位于所述源区和漏区上方的含硅外延半导体层；以及位于所述外延半导体层上方的金属硅化物层。

Description

晶体管
技术领域
本实用新型涉及半导体器件制造领域，尤其涉及一种晶体管。 
背景技术
通常，集成电路包含形成在衬底上的NMOS（n型金属-氧化物-半导体）晶体管和PMOS（p型金属-氧化物-半导体）晶体管的组合。集成电路的性能与其所包含的晶体管的性能有直接关系。因此，希望提高晶体管的驱动电流以增强其性能。 
美国专利申请No.20100038685A公开了一种晶体管，在该晶体管的沟道区与源/漏区之间形成位错，这种位错产生拉应力，该拉应力提高了沟道中的电子迁移率，由此晶体管的驱动电流得以增加。图11a-11c示出了这种位错的形成。在图11a中，对已经形成了栅极电介质2和栅极3的半导体衬底1进行硅注入，从而形成非晶区域，如图中阴影部分所示。在图11b中，对该半导体衬底1进行退火，使得非晶区域再结晶，在再结晶过程中，水平方向和竖直方向上的两个不同的晶体生长前端相遇，如图中箭头所示，从而形成了图11c所示的位错。 
实用新型内容
当自由表面低于导电沟道的水平面或者在导电沟道的水平面上时，由位错产生的拉应力会显著减小。通常，为了减小源极和漏极接触的接触电阻，会在源区和漏区上方形成金属硅化物。然而，硅化物的形成涉及硅和金属的移动，这等效于在硅化物底面产生了某种自由表面，这种自由表面如果在导电沟道的水平面上时，会导致由位错产生拉应力减小。 
本实用新型的目的是提供一种晶体管以及一种晶体管的制造方法。 
本实用新型的晶体管包括： 
半导体衬底；
形成在所述半导体衬底上的栅极电介质；
形成在所述栅极电介质上的栅极；
位于所述半导体衬底中、且分别在所述栅极两侧的源区和漏区，其中至少所述源区和漏区之一包含在平行于衬底表面的方向上排列的多个位错；
位于所述源区和漏区上方的含硅外延半导体层；以及
位于所述外延半导体层上方的金属硅化物层。
本实用新型的制造晶体管的方法包括如下步骤： 
在形成了栅极的半导体衬底上形成掩膜层，所述掩膜层覆盖所述栅极以及所述半导体衬底；
图形化该掩膜层，使得至少源区和漏区之一的至少一部分暴露；
对源区和/或漏区的暴露部分进行第一离子注入步骤；
对所述半导体衬底进行退火以在源区和/或漏区的暴露部分形成位错；
在源区和漏区上形成含有硅的半导体层；
在所述半导体层上形成金属层并进行退火以形成金属硅化物，
其中所述金属硅化物的底面高于位于所述源区和漏区之间的导电沟道。
在本实用新型的晶体管中，在源区和漏区上方形成含硅的半导体层，并且在该半导体层上沉积金属以形成金属硅化物，使得金属硅化物的底部位于导电沟道上方。根据本实用新型，一方面通过形成金属硅化物减小了源极接触和漏极接触的接触电阻；另一方面通过使金属硅化物底部在导电沟道上方，避免了源区和/或漏区中形成的位错产生的拉应力显著减小。 
本实用新型的其它方面和优点将在以下结合附图更详细地描述。 
附图说明
图1示出了根据本实用新型第一实施方式的晶体管的示意图。 
图2a-2b示出了制造图1所示晶体管的一些步骤的示意图。 
图3示出了根据本实用新型第二实施方式的一个示例性晶体管的示意图。 
图4a-4d示出了制造图3所示晶体管的一些步骤的示意图。 
图5示出根据本实用新型第二实施方式的另一个示例性晶体管的示意图。 
图6示出了制造图5所示晶体管的步骤之一的示意图。 
图7示出了根据本实用新型的第三实施方式的晶体管的示意图。 
图8a-8b示出了制造图7所示的晶体管的一些步骤的示意图。 
图9a示意性示出了根据本实用新型第四实施方式的一个例子的晶体管制造方法的步骤之一。 
图9b示意性示出了根据本实用新型第四实施方式的一个例子的晶体管。 
图10a示意性示出了根据本实用新型第四实施方式的另一个例子的晶体管制造方法的步骤之一。 
图10b示意性示出了根据本实用新型第四实施方式的另一个例子的晶体管。 
图11a-11c示出了现有技术中位错的形成。 
具体实施方式
以下结合附图描述本实用新型的优选实施例。附图是示意性的并未按比例绘制，且只是为了说明本实用新型的实施例而并不意图限制本实用新型的保护范围。贯穿附图相同的附图标记表示相同或相似的部件。为了使本实用新型的技术方案更加清楚，本领域熟知的工艺步骤及器件结构在此省略。 
<第一实施方式> 
图1示出了根据本实用新型第一实施方式的晶体管的示意图。如图1所示，晶体管100包括半导体衬底102、形成在所述半导体衬底102上的栅极电介质104、形成在所述栅极电介质104上的栅极106、在所述半导体衬底102中且分别位于栅极106两侧的源区108和漏区110、以及沟道区112，所述沟道区112位于源区108和漏区110之间且在栅极电介质104下方。在图1所示的晶体管100中，所述源区108和漏区110包含毗邻所述沟道区112的位错101。所述位错对沟道区112施加拉应力（如图中箭头所示），这种拉应力使得沟道区的电子迁移率增加。
晶体管100还包括：形成在栅极电介质104和栅极106侧壁上的侧墙116，形成在所述源区108和漏区110上的半导体层118，以及位于所述半导体层上的金属硅化物层122。所述半导体层118可以是Si、SiGe或Si:C层。实际上，晶体管100还包括源极接触和漏极接触，由于这些都是本领域普通技术人员所熟知的，因此在此并未示出和描述。 
形成该晶体管100的方法包括，首先如图11a-c中所示在源区108和漏区110中形成位错，然后在栅极电介质104和栅极106侧壁上形成侧墙116，并且随后在源区108和漏区110上形成半导体层118，得到如图2a所示的结构。该半导体层118可以通过外延生长的方式形成，例如通过溅射，化学气相沉积（CVD）、物理气相沉积（PVD）、原子层沉积（ALD）、及/或其他合适的工艺等方法形成。所述半导体层118可以是典型掺杂的。接下来，在所述半导体层118上沉积金属层120，例如，Ni层、Ti层或Co层，如图2b所示。最后，对图2b中所得到的结构进行退火，使得金属层120中的金属与所述半导体层118反应生成金属硅化物层122，并且之后除去金属层120的未反应的部分，从而得到如图1所示的晶体管。 
根据本实施方式，金属硅化物底部在导电沟道上方，在减小源极接触和漏极接触的接触电阻的同时，避免了源区和漏区中形成的位错产生的拉应力显著减小。 
<第二实施方式> 
图3示出了根据本实用新型的第二实施方式的一个示例性晶体管200a。如图3所示，该晶体管200a与第一实施方式的晶体管100的区别在于，在所述源区108和漏区110中均包含两个位错。尽管图3中示出所述位错不相交，但所述位错也可以是相交的。
图4a-d示出了晶体管200a的制造过程中的一些阶段。如图4a所示，首先在形成了栅极电介质104和栅极106的半导体衬底102上形成掩膜层114。该掩膜层114可以由光刻胶形成，或者是由诸如氧化硅和/或氮化硅的电介质材料形成的硬掩膜层。尽管在图1中示出所述掩膜层114形成为覆盖栅极106，但是本实用新型不限于此，掩膜层114也可以形成为与栅极106齐平或者低于栅极106。 
接下来，图形化所述掩膜层114，使得源区108和漏区110都有一部分暴露，如图4b所示。图形化掩膜层114可以通过本领域熟知的光刻工艺实现，在此并未详细描述。 
在图形化掩膜层114之后，对所述源区108和漏区110的暴露部分进行离子注入，以形成非晶区113，如图4c所示。 
再接下来，除去所述掩膜层114并对所得到的结构进行退火，从而在源区108和漏区110中都形成两个位错，如图4d所示。在掩膜层114是硬掩膜的情况下，也可以选择在退火之后除去掩膜层114。 
最后，在所述栅极电介质104和栅极106的侧壁上形成侧墙116，在形成侧墙116之后，执行与上述图2a和2b所示的相同的步骤，从而在所述源区108和漏区110上形成半导体层118以及金属硅化物层122。由此得到图3所示的晶体管300a。 
图5示出了根据本实施方式的另一个示例性的晶体管200b，其中源区108和漏区110每一个均包含三个位错。相应地，形成晶体管200b的方法与形成晶体管200a的方法的不同之处仅在于图4b所示的步骤，即，在图形化掩膜层114时，使得源区108和漏区110的两个部分暴露，这两个暴露部分之间的掩膜层未被除去。图6示出了制造晶体管200b时与图4b相对应的方法步骤的示意图。基于以上的描述，本领域技术人员可以理解，通过图形化掩膜层114使得源区108和漏区110有更多部分暴露（相邻的暴露部分之间的掩膜层114未被除去），可以在源区和漏区中形成更多的位错。 
尽管如上所述在源区108和漏区110中对称地形成位错，但是本实用新型不限于此。在一种变型中，可以在源区108和漏区109中不对称地形成位错，这可以通过采用不同的光刻图案对源区108和漏区109上方的掩膜层114进行图形化来实现。此外，优选地，可以仅使得源区108的至少一部分暴露而保持漏区109被掩膜层114覆盖，从而仅在源区108中形成位错，这样做可以避免结漏电流增加。 
除了与上述第一实施方式相同的优点外，本实施方式的优点还在于平行于衬底表面形成了更多的位错，使得作用于沟道区的拉应力增强，从而载流子迁移率的进一步增加称为可能。 
<第三实施方式> 
图7示出了根据本实用新型的第三实施方式的晶体管的示意图。图7所示晶体管300与图1所示晶体管100的区别在于，所述源区108和漏区110包括毗邻沟道区112、在垂直于半导体衬底102的表面的方向上排列的一组两个位错。
相应地，与第一实施方式中制造晶体管100的方法相比较，本实施方式中制造晶体管300的方法还包括，在进行根据第一实施方式的方法的退火步骤之后，对所述源区108和漏区109执行第二离子注入步骤，以形成非晶区，该第二离子注入的深度d2小于上述第一深度d1，如图8a所示。在该第二离子注入步骤之后再次进行退火，从而在源区108和漏区110中形成另一位错103，如图8b所示。可以通过调节离子注入能量和剂量来控制离子注入深度。之后，可以在所述栅极电介质104和栅极106的侧壁上形成侧墙116。在形成侧墙116之后，执行与上述图2a和2b所示的相同的步骤，从而在所述源区108和漏区110上形成半导体层118以及金属硅化物层122。由此得到图7所示的晶体管300。 
虽然图7示出了源区108和漏区110分别包含一组两个位错。但是本实用新型不限于此，源区108和漏区110可以包括毗邻沟道区112、在垂直于半导体衬底102的表面的方向上排列的一组不止两个位错。相应地，通过执行更多个注入深度不同的离子注入步骤来形成所述更多的位错，其中在后离子注入步骤的注入深度小于先前离子注入步骤的注入深度。 
除了与第一实施方式相同的优点外，本实施方式的优点还在于可以在源区108和漏区110中根据需要毗邻沟道区形成更多数目的位错，更进一步增强了作用于沟道区的拉应力，相应地，沟道区的电子迁移率进一步增加也成为可能。 
<第四实施方式> 
第四实施方式是第二实施方式和第三实施方式的组合。本实施方式中的晶体管制造方法可以选择在所述离子注入步骤中的一个或多个之前，在至少所述源区108和漏区110之一上选择性地形成掩膜层114以使其一部分或至少两个部分暴露，在后一种情况下，相邻的暴露部分之间的源区108和/或漏区110的部分被掩膜层114覆盖。在一个优选实施例中至少使得源区108和/或漏区110毗邻所述栅极106的部分暴露。选择性地形成掩膜层例如可以通过本领域熟知的光刻工艺实现。
在所述离子注入步骤中的多个之前选择性地形成掩膜层的情况下，每一次所形成的掩膜层的图案可以相同或不同，或者源区和漏区上所形成的掩膜层的图案也可以是不同的。在一个优选方案中，所述掩膜层由诸如氧化硅和/或氮化硅的电介质材料形成，这样在退火过程中无需除去掩膜层，从而仅需执行一次选择性地形成掩膜层的步骤，就可以在平行于衬底表面的方向上形成多个位错的同时，通过多次注入-退火步骤在垂直于衬底表面的方向上形成多个位错。 
作为一个非限制性的例子，在第二实施方式中形成了图4d所示的器件结构之后进行第二离子注入步骤，得到如图9a所示的结构，该第二离子注入步骤的注入深度d2’小于第一注入深度d1。在该第二离子注入步骤之后除去掩膜层114并且进行退火以形成位错。然后，在所述栅极电介质104和栅极106的侧壁上形成侧墙116，在形成侧墙116之后。执行与上述图2a和2b所示的相同的步骤，从而在所述源区108和漏区110上形成半导体层118以及金属硅化物层122，得到了图9b所示的晶体管400a。优选在该例子中使用硬掩膜层作为掩膜层114，使得在为形成图4d所示的器件结构执行的退火步骤中无需除去掩膜层114，从而在进行第二离子注入步骤时仍保留所述掩膜层114。 
作为另一个非限制性的例子，除了执行第三实施方式中的方法步骤之外，还在执行第二离子注入步骤之前，选择性地形成掩膜层114，使得源区108的两个部分暴露，相邻的暴露部分之间的源区108的部分被掩膜层114所覆盖；而漏区110有一个部分暴露。图10a示出了在形成该掩膜层114后进行第二离子注入步骤后所得到的结构。然后除去掩膜层114并且对所得到的结构进行退火，掩膜层114可以根据需要在退火之前或之后除去。再接下来，在栅极电介质104和栅极106的侧壁上形成侧墙116。之后执行与上述图2a和2b所示的相同的步骤，从而在所述源区108和漏区110上形成半导体层118以及金属硅化物层122。由此，得到图10b所示的晶体管400b。 
由此，本实施方式中的晶体管在源区和/或漏区具有至少另一个位错，该至少另一个位错相比于第三实施方式中形成的位错更远离所述沟道区。 
将平行于衬底表面的方向规定为晶体管的横向，将垂直于衬底表面的方向规定为晶体管的纵向。相比于第一、第二、第三实施方式，该第四实施方式可以在晶体管的纵向上以及横向上都得到更多的位错。因此，除了具有与第一实施方式相同的优点之外，在本实施方式中作用于沟道区的拉应力（并且因此沟道区的电子迁移率）更进一步增加成为可能。 
此外，优选在该实施方式中，在每一次离子注入步骤之前都使得掩膜层114完全覆盖漏区110，从而在漏区110中不产生位错，以避免结漏电流增加。 
上述第一至四实施方式中的晶体管可以是NMOS晶体管。 
上述第一至四实施方式所述的晶体管制造方法中，所述半导体衬底可以包括NMOS器件区和PMOS器件区，其中仅在NMOS器件区执行根据本实用新型的晶体管制造方法。 
上述第一至四实施方式中：晶体管还可以包括位于所述源区108上方的半导体层（未示出），该半导体层例如是Si、碳化硅、硅锗或者锗层，该半导体层使得所述位错不暴露于自由表面。以防止由于错位暴露于自由表面而可能导致的拉应力减小。 
在上述第一至四实施方式中，离子注入步骤中注入的离子例如可以是硅、锗、磷、硼或砷中的一种或其组合。 
在上述第一至四实施方式中，退火温度可以大于400℃，优选为500-900℃，退火时间可以为数秒至数分钟。 
在上述第一至四实施方式所描述的方法步骤之后，可以执行本领域熟知的侧墙形成以及源极/漏极接触的形成等步骤，以形成完整的器件。 
尽管在上面的描述中，在形成位错之后再进行形成源和漏的掺杂工艺，然而，本实用新型不限于此，可以在任何适当的阶段形成所述位错，例如，可以在进行形成源和漏的掺杂之后形成所述位错。 
此外，上文所描述的半导体衬底可以是Si衬底、SiGe衬底、SiC衬底、或III-V半导体衬底（例如，GaAs、GaN等等）。栅极电介质可以使用SiO2、HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al2O3、La2O3、ZrO2、LaAlO中的一种或其组合，栅极的材料可以选自Poly-Si 、Ti 、Co、Ni、Al、W，上述金属的合金或者金属硅化物。 
以上通过示例性实施例描述了本实用新型的晶体管及制造晶体管的方法，然而，这并不意图限制本实用新型的保护范围。本领域技术人员可以想到的上述实施例的任何修改或变型都落入由所附权利要求限定的本实用新型的范围内。 

Claims (7)

1.一种晶体管，包括：
半导体衬底；
形成在所述半导体衬底上的栅极电介质；
形成在所述栅极电介质上的栅极；
位于所述半导体衬底中、且分别在所述栅极两侧的源区和漏区，其中至少所述源区和漏区之一包含在平行于衬底表面的方向上排列的多个位错；
位于所述源区和漏区上方的含硅外延半导体层；以及
位于所述外延半导体层上方的金属硅化物层。
2.根据权利要求1所述的晶体管，至少所述源区和漏区之一包括毗邻沟道区、在垂直于所述半导体衬底的表面的方向上排列的第一组位错，该第一组位错包含至少两个位错。
3.根据权利要求2所述的晶体管，其中至少所述源区和漏区之一还含有至少另一个位错，该至少另一个位错相比于所述第一组位错更远离所述沟道区。
4.根据权利要求2所述的晶体管，其中至少所述源区和漏区之一还含有在垂直于所述半导体衬底的表面的方向上排列的至少另一组位错，该至少另一组位错包含至少两个位错，且相比于所述第一组位错更远离所述沟道区。
5.根据权利要求1至4中任一项所述的晶体管，其中所述位错对位于源区和漏区之间的沟道区施加拉应力，使得所述沟道区的电子迁移率增加。
6.根据权利要求1至4中任一项所述的晶体管，其中所述晶体管为NMOS晶体管。
7.根据权利要求1至4中任一项所述的晶体管，其中所述漏区中不含有位错。
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Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102468166B (zh) * 2010-10-29 2015-01-28 中国科学院微电子研究所 晶体管及其制造方法
US8685804B2 (en) * 2011-10-03 2014-04-01 International Business Machines Corporation Enhancement of charge carrier mobility in transistors
US9299838B2 (en) 2011-10-24 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. MOSFETs with multiple dislocation planes
US20130200455A1 (en) * 2012-02-08 2013-08-08 Taiwan Semiconductor Manufacturing Company, Ltd. Dislocation smt for finfet device
CN103515238B (zh) * 2012-06-26 2016-03-16 中芯国际集成电路制造(上海)有限公司 Nmos晶体管及形成方法、cmos结构及形成方法
CN103578987B (zh) * 2012-07-19 2016-08-24 中国科学院微电子研究所 半导体器件及其制造方法
CN103943504A (zh) * 2013-01-22 2014-07-23 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制备方法
US9412650B2 (en) 2013-03-08 2016-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure and method of forming the same
CN104517846B (zh) * 2013-09-27 2018-06-08 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法
US10644116B2 (en) * 2014-02-06 2020-05-05 Taiwan Semiconductor Manufacturing Company, Ltd. In-situ straining epitaxial process
CN104851804B (zh) * 2014-02-18 2018-07-20 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制备方法
US9406797B2 (en) * 2014-03-07 2016-08-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor integrated circuit with dislocations
US9231079B1 (en) * 2014-06-13 2016-01-05 Globalfoundries Inc. Stress memorization techniques for transistor devices
KR101659176B1 (ko) * 2014-08-08 2016-09-22 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 복수의 전위 면을 갖는 ｍｏｓｆｅｔ
US9991384B2 (en) * 2015-01-15 2018-06-05 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device including fin structures and manufacturing method thereof
KR102245136B1 (ko) 2015-02-24 2021-04-28 삼성전자 주식회사 반도체 소자 형성 방법
CN106711215B (zh) * 2015-11-12 2021-09-07 联华电子股份有限公司 半导体元件及其制作方法
CN111435679B (zh) 2019-01-14 2023-06-13 联华电子股份有限公司 具有非对称应变源极/漏极结构的半导体元件其制作方法
CN111081761B (zh) * 2019-12-16 2022-05-03 电子科技大学 具有抗辐射加固结构的低功耗晶体管器件及其制备方法

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4998150A (en) * 1988-12-22 1991-03-05 Texas Instruments Incorporated Raised source/drain transistor
US5710450A (en) 1994-12-23 1998-01-20 Intel Corporation Transistor with ultra shallow tip and method of fabrication
SE512813C2 (sv) * 1997-05-23 2000-05-15 Ericsson Telefon Ab L M Förfarande för framställning av en integrerad krets innefattande en dislokationsfri kollektorplugg förbunden med en begravd kollektor i en halvledarkomponent, som är omgiven av en dislokationsfri trench samt integrerad krets framställd enligt förfarandet
US6180476B1 (en) * 1998-11-06 2001-01-30 Advanced Micro Devices, Inc. Dual amorphization implant process for ultra-shallow drain and source extensions
CN100382277C (zh) * 1999-12-24 2008-04-16 Nxp有限公司 半导体器件的制造方法
US6982474B2 (en) * 2002-06-25 2006-01-03 Amberwave Systems Corporation Reacted conductive gate electrodes
WO2004012243A2 (en) * 2002-07-29 2004-02-05 Amberwave Systems Selective placement of dislocation arrays
US6803270B2 (en) * 2003-02-21 2004-10-12 International Business Machines Corporation CMOS performance enhancement using localized voids and extended defects
US6800887B1 (en) * 2003-03-31 2004-10-05 Intel Corporation Nitrogen controlled growth of dislocation loop in stress enhanced transistor
US7413957B2 (en) * 2004-06-24 2008-08-19 Applied Materials, Inc. Methods for forming a transistor
JP5172083B2 (ja) * 2004-10-18 2013-03-27 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法、並びにメモリ回路
US7247547B2 (en) * 2005-01-05 2007-07-24 International Business Machines Corporation Method of fabricating a field effect transistor having improved junctions
US7691714B2 (en) 2005-01-25 2010-04-06 Texas Instruments Incorporated Semiconductor device having a dislocation loop located within a boundary created by source/drain regions and a method of manufacture therefor
US7566605B2 (en) * 2006-03-31 2009-07-28 Intel Corporation Epitaxial silicon germanium for reduced contact resistance in field-effect transistors
US7795679B2 (en) * 2008-07-24 2010-09-14 International Business Machines Corporation Device structures with a self-aligned damage layer and methods for forming such device structures
US8779477B2 (en) * 2008-08-14 2014-07-15 Intel Corporation Enhanced dislocation stress transistor
CN102468166B (zh) * 2010-10-29 2015-01-28 中国科学院微电子研究所 晶体管及其制造方法
CN102468165B (zh) * 2010-10-29 2014-06-25 中国科学院微电子研究所 晶体管及其制造方法

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