CN202633241U - 晶体管 - Google Patents

晶体管 Download PDF

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CN202633241U
CN202633241U CN2011900000726U CN201190000072U CN202633241U CN 202633241 U CN202633241 U CN 202633241U CN 2011900000726 U CN2011900000726 U CN 2011900000726U CN 201190000072 U CN201190000072 U CN 201190000072U CN 202633241 U CN202633241 U CN 202633241U
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transistor
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尹海洲
朱慧珑
骆志炯
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Abstract

本实用新型提供了一种晶体管。该晶体管（100）包括：半导体衬底（102）；形成在所述半导体衬底上的栅极电介质（104）；形成在所述栅极电介质上的栅极（106）；位于所述栅极电介质下方的沟道区（112）；位于所述半导体衬底中、且分别在所述沟道区两侧的源区（108）和漏区（110），其中至少所述源区和漏区之一包含毗邻所述沟道区、在垂直于所述半导体衬底的表面的方向上排列的一组位错（101），该组位错包含至少两个位错。

Description

晶体管
技术领域
本实用新型涉及半导体器件制造领域，尤其涉及一种晶体管。 
背景技术
通常，集成电路包含形成在衬底上的NMOS（n型金属-氧化物-半导体）晶体管和PMOS（p型金属-氧化物-半导体）晶体管的组合。集成电路的性能与其所包含的晶体管的性能有直接关系。因此，希望提高晶体管的驱动电流以增强其性能。 
美国专利申请No.20100038685A公开了一种晶体管，在该晶体管的沟道区与源/漏区之间形成位错，这种位错产生拉应力，该拉应力提高了沟道中的电子迁移率，由此晶体管的驱动电流得以增加。图12a-12c示出了这种位错的形成。在图12a中，对已经形成了栅极电介质2和栅极3的半导体衬底1进行硅注入，从而形成非晶区域，如图中阴影部分所示。在图12b中，对该半导体衬底1进行退火，使得非晶区域再结晶，在再结晶过程中，水平方向和竖直方向上的两个不同的晶体生长前端相遇，如图中箭头所示，从而形成了图12c所示的位错。 
实用新型内容
本实用新型的目的是提供一种晶体管以及一种晶体管的制造方法。 
本实用新型的制造晶体管的方法包括如下步骤： 
在半导体衬底上形成栅极电介质；
在所述栅极电介质上形成栅极；
对位于所述衬底中且分别在所述栅极两侧的所述半导体衬底的第一区和第二区进行第一离子注入步骤，该第一离子注入步骤的注入深度为第一深度；
在该第一离子注入步骤之后进行退火，使得在所述第一区和第二区中均形成位错；
对所述第一区和第二区之一或二者执行第二离子注入步骤，该第二离子注入步骤的注入深度为第二深度，该第二深度小于第一深度；以及
在该第二离子注入步骤之后进行退火，使得在所述第一区和第二区中均形成位错。
根据本实用新型的晶体管制造方法，通过在源区和漏区进行不同深度的非晶化-结晶步骤，能够毗邻沟道区形成更多的位错，更多的位错可导致更多的拉应力作用于沟道，从而使增强沟道区的电子迁移率成为可能。 
本实用新型的晶体管包括： 
半导体衬底；
形成在所述半导体衬底上的栅极电介质；
形成在所述栅极电介质上的栅极；
位于所述栅极电介质下方的沟道区；
位于所述半导体衬底中、且分别在所述沟道区两侧的源区和漏区，
其中至少所述源区和漏区之一包含毗邻所述沟道区、在垂直于所述半导体衬底的表面的方向上排列的一组位错，该组位错包含至少两个位错；
其中所述位错对位于源区和漏区之间的沟道区施加拉应力，使得所述沟道区的电子迁移率增加。
根据本实用新型的晶体管由于毗邻沟道区具有更多的位错，因此作用在沟道区的拉应力可以得到增强，沟道区的电子迁移率也可以得以进一步增加。 
本实用新型的其它方面和优点将在以下结合附图更详细地描述。 
附图说明
图1示出了根据本实用新型第一实施方式的晶体管的示意图。 
图2a-d是根据本实用新型的第一实施方式制造晶体管的方法步骤的示意图 
图3示出了根据本实用新型的第二实施方式的晶体管的示意图。
图4示出了根据本实用新型的第二实施方式的晶体管的制造方法的步骤之一的示意图。 
图5示出根据本实用新型的第三实施方式的变型的晶体管的示意图。 
图6示出了根据本实用新型的第四实施方式的晶体管的制造方法的步骤之一的示意图。 
图7示出了根据本实用新型的第四实施方式的晶体管的示意图。 
图8示出了根据本实用新型的第四实施方式的一个变型的晶体管的制造方法的步骤之一的示意图。 
图9示出了根据本实用新型的第四实施方式的一个变型的晶体管的示意图。 
图10示出了根据本实用新型的第四实施方式的另一个变型的晶体管的制造方法的步骤之一的示意图。 
图11示出了根据本实用新型的第四实施方式的另一个变型的晶体管的示意图。 
图12a-c示出了现有技术中位错的形成。 
具体实施方式
以下结合附图描述本实用新型的优选实施例。附图是示意性的并未按比例绘制，且只是为了说明本实用新型的实施例而并不意图限制本实用新型的保护范围。贯穿附图相同的附图标记表示相同或相似的部件。为了使本实用新型的技术方案更加清楚，本领域熟知的工艺步骤及器件结构在此省略。 
<第一实施方式> 
图1示出了根据本实用新型第一实施方式的晶体管的示意图。如图1所示，晶体管100包括半导体衬底102、形成在所述半导体衬底102上的栅极电介质104、形成在所述栅极电介质104上的栅极106、分别位于栅极106两侧的源区108和漏区110、以及沟道区112，所述沟道区112位于源区108和漏区110之间且在栅极电介质104下方。在图1所示的晶体管100中，所述源区108和漏区110都包含毗邻所述沟道区112、在垂直于所述半导体衬底的表面的方向上排列的一组位错，每组位错包含两个位错101。所述位错对沟道区112施加拉应力（如图中箭头所示），这种拉应力使得沟道区的电子迁移率增加。相比于现有技术，本实用新型毗邻沟道区形成了更多数量的位错，使得作用于沟道区112的拉应力得以增强，从而进一步提高沟道区112的电子迁移率成为可能。
此外，晶体管100还包括形成在栅极电介质104和栅极106侧面的侧墙以及源极和漏极接触等，由于这些结构对于本领域技术人员而言是熟知的，因此并未在附图中示出以及详细描述。 
接下来，参照图2a-d描述根据第一实施方式的晶体管制造方法。 
如图2a所示，在半导体衬底102上形成栅极电介质104和栅极106。接下来，如图2b所示，对位于所述半导体衬底102中且分别在所述栅极106两侧的所述半导体衬底的第一区108和第二区110进行第一离子注入步骤，由此在所述第一区108和第二区110中形成非晶区，如图中阴影部分所示，该第一离子注入步骤的注入深度为第一深度d1。所述第一区108和第二区110分别是要形成晶体管的源和漏的区域，或者分别是已经通过执行离子注入形成了晶体管的源和漏的区域。在图2b所示的步骤之后执行退火，使得非晶区再结晶。在再结晶过程中，不同的晶体生长前端相遇，从而在所述第一区108和第二区110中形成位错，如图2c所示，所述位错毗邻位于所述栅极电介质104下方的要形成导电沟道的区域。 
接下来，对图2c所示的结构进行第二离子注入步骤，以形成非晶区，如图2d所示，该第二离子注入步骤的注入深度为第二深度d2，d2小于d1。可以通过调节离子注入能量和剂量来控制离子注入深度。然后，对图2d所示的结构进行退火，从而得到如图1所示的结构。 
<第二实施方式> 
图3示出了根据本实用新型的第二实施方式的晶体管的示意图。图3所示晶体管200与图1所示晶体管100的区别在于，所述源区108和漏区110中的每一个均包括毗邻沟道区112、在垂直于半导体衬底102的表面的方向上排列的一组三个位错。
相应地，与制造晶体管100的方法相比较，本实施方式中制造晶体管200的方法还包括对所述第一区108和第二区110执行第三离子注入步骤，该第三离子注入的深度d3小于上述第二深度d2，如图4所示。 
虽然图3示出了源区108和漏区110中的每组位错包括三个位错。但是本实用新型不限于此，源区108和漏区110中的每组位错还可以包括更多的位错，相应地，通过执行更多个注入深度不同的离子注入步骤来形成所述更多的位错，其中在后离子注入步骤的注入深度小于先前离子注入步骤的注入深度。 
根据本实施方式，可以根据需要毗邻沟道区形成更多数目的位错，更进一步增强了作用于沟道区的拉应力，相应地，沟道区的电子迁移率进一步增加也成为可能。 
<第三实施方式> 
尽管在以上对第一实施方式和第二实施方式的描述中，在晶体管的源区和漏区中位错是对称的，但是本实用新型不限于此，可以通过在任一次离子注入步骤之前利用掩膜层将第一区和第二区中的一个完全覆盖而仅对其中的另一个执行离子注入，从而在源区108和漏区110中不对称地形成位错。例如，在执行第二离子注入步骤之前，在第一区108而不在第二区110上形成掩膜层，从而不对第一区108执行第二离子注入步骤。这样，在所得到的晶体管200a中，第一区108仅包含一个位错，而第二区110包含在垂直于半导体衬底102的表面的方向上排列的一组两个位错，如图5所示。
<第四实施方式> 
本实施方式中的晶体管制造方法与前述第一实施方式和第二实施方式所述的方法的不同之处在于，可以选择在所述离子注入步骤中的一个或多个之前，在所述第一区108和第二区110中的至少一个上选择性地形成掩膜层，以覆盖其一部分并且在一个优选实施例中使得其毗邻所述栅极的部分暴露。作为一个非限制性的例子，除了执行第一实施方式中的方法步骤之外，还在执行第二离子注入步骤之前，在第二区110上形成覆盖其一部分的掩模层114，图6示出了在形成该掩膜层114后进行第二离子注入步骤后所得到的结构，其中第二区110中被掩膜层114覆盖的部分未被注入离子。对图6的结构进行退火，从而得到图7所示的晶体管300，虽然在图7中仍然示出了掩膜层114，但实际上掩膜层114可以在退火之前已经被除去。
所述掩膜层可以是光刻胶层，或者是由诸如氧化硅和/或氮化硅的电介质材料形成的硬掩膜层。而选择性地形成硬掩膜层例如可以通过本领域熟知的光刻工艺实现。在所述离子注入步骤中的多个之前选择性地形成掩膜层的情况下，每一次所形成的掩膜层的图案可以相同或不同。在一个优选方案中，所述掩膜层由诸如氧化硅和/或氮化硅的电介质材料形成，这样在掩膜层图案相同时的退火过程中无需除去掩膜层，从而仅需执行一次形成掩膜层的步骤。 
作为第四实施方式的一个变型，可以在所述离子注入步骤中的一个或多个之前，在所述第一区108和第二区110中的至少一个上选择性地形成掩膜层，以覆盖其不相邻的至少两个部分。作为一个非限制性的例子，除了执行第一实施方式中的方法步骤之外，还分别在执行第一和第二离子注入步骤之前，在第一区108和第二区110上均形成覆盖其不相邻的两个部分的掩模层114，而后进行第一离子注入步骤，所得到的结构如图8所示。接下来，在不去除掩膜层114的情况下，执行第二离子注入步骤及相应的退火。注意，掩膜层114在第一区108和第二区110上的位置可以是关于晶体管100的栅极106对称的或不对称的。图9示出了该例子中最终形成的晶体管100a的示意图。虽然在图9中仍然示出了掩膜层114，但实际上掩膜层114可以在退火之前已经被除去。 
在另一个非限制性的例子中，仅在第一区108和第二区110之一上形成覆盖其不相邻的两个部分的掩模层114，而另一个上不形成掩膜层或者完全被掩膜层覆盖。 
作为第四实施方式的又一个变型，可以在所述离子注入步骤中的一个或多个之前，在所述第一区108和第二区110中的一个上选择性地形成掩膜层，以覆盖其不相邻的至少两个部分，而在所述第一区108和第二区110中的另一个上选择性地形成掩膜层，以覆盖其一部分。作为一个非限制性的例子，除了执行第一实施方式中的方法步骤之外，还在执行第二离子注入步骤之前，在第一区108上形成覆盖其一部分的掩膜层114，且在第二区110上形成覆盖其不相邻的两个部分的掩模层114，而后进行第二离子注入步骤，所得到的结构如图10所示。图11示出了该例子中最终得到的晶体管100b的示意图。虽然在图11中仍然示出了掩膜层114，但实际上掩膜层114可以在退火之前已经被除去。 
由此，本实施方式中的晶体管在至少所述源区和漏区之一还含有至少另一个位错，该至少另一个位错相比于第一和第二实施方式中形成的位错更远离所述沟道区。 
将平行于衬底表面的方向规定为晶体管的横向，将垂直于衬底表面的方向规定为晶体管的纵向。相比于第一、第二、第三实施方式，该第四实施方式及其变型除了可以在晶体管的纵向上得到更多的位错之外，还可以进一步在晶体管的横向上得到更多的位错，从而使得作用于沟道区的拉应力（并且因此沟道区的电子迁移率）更进一步增加成为可能。 
上述第一至四实施方式及其变型中的晶体管可以是NMOS晶体管。 
上述第一至四实施方式及其变型所述的晶体管制造方法中，所述半导体衬底可以包括NMOS器件区和PMOS器件区，其中仅在NMOS器件区执行根据本实用新型的晶体管制造方法。 
上述第一至四实施方式及其变型中：晶体管还可以包括位于所述源区108和漏区110上方的半导体层（未示出），该半导体层例如是Si、碳化硅、硅锗或者锗层，该半导体层使得所述位错不暴露于自由表面；晶体管的制造方法包括在进行形成源和漏的掺杂步骤之后在源区和漏区上方形成所述半导体层。所述半导体层使得位错不暴露于自由表面，以防止由于错位暴露于自由表面而可能导致的拉应力减小。 
在上述第一至四实施方式及其变型中，离子注入步骤中注入的离子例如可以是硅、锗、磷、硼或砷中的一种或其组合。 
在上述第一至四实施方式及其变型中，退火温度可以大于400℃，优选为500℃-900℃，退火时间可以为数秒至数分钟。 
在上述第一至四实施方式及其变型中所描述的方法步骤之后，可以执行本领域熟知的源区和漏区的掺杂、侧墙形成以及源极/漏极接触的形成等步骤，以形成完整的器件。 
尽管在上面的描述中，在形成位错之后再进行形成源和漏的掺杂工艺，然而，本实用新型不限于此，可以在任何适当的阶段形成所述位错，例如，可以在进行形成源和漏的掺杂之后形成所述位错。 
此外，上文所描述的半导体衬底可以是Si衬底、SiGe衬底、SiC衬底、或III-V半导体衬底（例如，GaAs、GaN等等）。栅极电介质可以使用SiO2、HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al2O3、La2O3、ZrO2、LaAlO中的一种或其组合，栅极的材料可以选自Poly-Si 、Ti 、Co、Ni、Al、W，上述金属的合金或者金属硅化物。 
以上通过示例性实施例描述了本实用新型的晶体管及制造晶体管的方法，然而，这并不意图限制本实用新型的保护范围。本领域技术人员可以想到的上述实施例的任何修改或变型都落入由所附权利要求限定的本实用新型的范围内。 

Claims (2)

1.一种晶体管，包括：
半导体衬底；
形成在所述半导体衬底上的栅极电介质；
形成在所述栅极电介质上的栅极；
位于所述栅极电介质下方的沟道区；
位于所述半导体衬底中、且分别在所述沟道区两侧的源区和漏区，
其中至少所述源区和漏区之一包含毗邻所述沟道区、在垂直于所述半导体衬底的表面的方向上排列的一组位错，该组位错包含至少两个位错；
其中所述位错对位于源区和漏区之间的沟道区施加拉应力，使得所述沟道区的电子迁移率增加。
2.根据权利要求1所述的晶体管，其中所述晶体管为NMOS晶体管。
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