WO2012055142A1 - 晶体管及其制造方法 - Google Patents

晶体管及其制造方法 Download PDF

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Publication number
WO2012055142A1
WO2012055142A1 PCT/CN2011/000262 CN2011000262W WO2012055142A1 WO 2012055142 A1 WO2012055142 A1 WO 2012055142A1 CN 2011000262 W CN2011000262 W CN 2011000262W WO 2012055142 A1 WO2012055142 A1 WO 2012055142A1
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Prior art keywords
region
ion implantation
implantation step
transistor
dislocations
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PCT/CN2011/000262
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English (en)
French (fr)
Inventor
尹海洲
朱慧珑
骆志炯
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中国科学院微电子研究所
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Application filed by 中国科学院微电子研究所 filed Critical 中国科学院微电子研究所
Priority to CN2011900000726U priority Critical patent/CN202633241U/zh
Priority to US13/112,989 priority patent/US8564029B2/en
Publication of WO2012055142A1 publication Critical patent/WO2012055142A1/zh
Priority to US14/023,426 priority patent/US9023706B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/2654—Bombardment with radiation with high-energy radiation producing ion implantation in AIIIBV compounds
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/2654—Bombardment with radiation with high-energy radiation producing ion implantation in AIIIBV compounds
    • H01L21/26546—Bombardment with radiation with high-energy radiation producing ion implantation in AIIIBV compounds of electrically active species
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material

Definitions

  • the present invention relates to the field of semiconductor device fabrication, and more particularly to a transistor and a method of fabricating the same. Background technique
  • an integrated circuit includes a combination of an NMOS (n-type metal-oxide-semiconductor) transistor and a PMOS (p-type metal-oxide-semiconductor) transistor formed on a substrate.
  • NMOS n-type metal-oxide-semiconductor
  • PMOS p-type metal-oxide-semiconductor
  • U.S. Patent Application No. 2010010381068105 A discloses a transistor in which a dislocation is formed between a channel region and a source/drain region of the transistor, which generates a tensile stress which increases the electron mobility in the channel. Thus, the drive current of the transistor is increased.
  • the formation of such dislocations is illustrated in Figures 12a-12c.
  • silicon implantation is performed on the semiconductor substrate 1 on which the gate dielectric 2 and the gate 3 have been formed, thereby forming an amorphous region as shown by the hatched portion in the figure.
  • the semiconductor substrate 1 is annealed to recrystallize the amorphous regions. During the recrystallization process, two different crystal growth front ends in the horizontal direction and the vertical direction meet, as indicated by the arrows in the figure. Thus, the dislocations shown in Fig. 12c are formed. Summary of the invention
  • the method of manufacturing a transistor of the present invention includes the following steps:
  • Annealing is performed after the first ion implantation step such that dislocations are formed in both the first region and the second region;
  • the first The implantation depth of the two ion implantation step is a second depth, and the second depth is smaller than the second
  • Annealing is performed after the second ion implantation step so that dislocations are formed in both the first region and the second region.
  • the transistor manufacturing method of the present invention by performing the amorphization-crystallization steps of different depths in the source and drain regions, more dislocations can be formed adjacent to the channel region, and more dislocations can cause more tensile stress. Acting on the channel makes it possible to enhance the electron mobility of the channel region.
  • the transistor of the present invention includes:
  • Source and drain regions located in the semiconductor substrate and on opposite sides of the channel region, wherein at least one of the source and drain regions comprises adjacent to the channel region, perpendicular to the A set of dislocations arranged in the direction of the surface of the semiconductor substrate, the set of dislocations comprising at least two dislocations.
  • the transistor according to the present invention has more dislocations due to the adjacent channel region, so that the tensile stress acting on the channel region can be enhanced, and the electron mobility of the channel region can be further enhanced.
  • Fig. 1 shows a schematic view of a transistor in accordance with a first embodiment of the present invention.
  • FIGS. 2a-d are schematic illustrations of method steps for fabricating a transistor in accordance with a first embodiment of the present invention
  • Figure 3 shows a schematic diagram of a transistor in accordance with a second embodiment of the present invention.
  • Fig. 4 is a schematic view showing one of the steps of a method of manufacturing a transistor according to a second embodiment of the present invention.
  • Fig. 5 shows a schematic diagram of a transistor according to a variant of the third embodiment of the invention.
  • Fig. 6 is a schematic view showing one of the steps of a method of manufacturing a transistor according to a fourth embodiment of the present invention.
  • Fig. 7 shows a schematic diagram of a transistor in accordance with a fourth embodiment of the present invention.
  • Fig. 8 is a view showing one of the steps of a method of manufacturing a transistor according to a modification of the fourth embodiment of the present invention.
  • Fig. 9 shows a schematic diagram of a transistor according to a modification of the fourth embodiment of the present invention.
  • Fig. 10 is a view showing one of the steps of a method of manufacturing a transistor according to another modification of the fourth embodiment of the present invention.
  • Fig. 11 shows a schematic view of a transistor according to another modification of the fourth embodiment of the present invention. .
  • FIGS 12a-c illustrate the formation of dislocations in the prior art. detailed description
  • FIG. 1 shows a schematic diagram of a transistor in accordance with a first embodiment of the present invention.
  • the transistor 100 includes a semiconductor substrate 102, a gate dielectric 104 formed on the semiconductor substrate 102, and a gate electrode 106 formed on the gate dielectric 104, respectively located on both sides of the gate 106.
  • the source region 108 and the drain region 1 10, and the channel region 1 12 are located between the source region 108 and the drain region 110 and below the gate dielectric 104.
  • the source region 108 and the drain region 110 both contain adjacent bits of the channel region and include two bits.
  • the dislocations apply a tensile stress to the channel region (shown by the arrow in the figure) which increases the electron mobility of the channel region.
  • the present invention forms a larger number of dislocations adjacent to the channel region, so that the tensile stress acting on the channel region 12 is enhanced, thereby further increasing the electron mobility of the channel region 12 .
  • transistor 100 also includes sidewalls formed on the sides of gate dielectric 104 and gate 106, as well as source and drain contacts, etc., as these structures are known to those skilled in the art. It is well known and therefore not shown in the drawings and described in detail.
  • a transistor manufacturing method will be described with reference to Figs. 2a-d.
  • a gate dielectric 104 and a gate 106 are formed over the semiconductor substrate 102.
  • a first ion implantation is performed on the first region 108 and the second region 110 of the semiconductor substrate located in the semiconductor substrate 102 and on both sides of the gate 106, respectively. Steps, thereby forming an amorphous region in the first region 108 and the second region 110, as shown by hatched portions in the drawing, the implantation depth of the first ion implantation step is the first depth dl.
  • the first region 108 and the second region 1 10 are regions where a source and a drain of a transistor are to be formed, respectively, or regions where a source and a drain of a transistor have been formed by performing ion implantation, respectively. Annealing is performed after the step shown in Fig. 2b to recrystallize the amorphous region. During the recrystallization process, different crystal growth front ends meet to form dislocations in the first region 108 and the second region 110, as shown in FIG. 2c, the dislocations are adjacent to the gate dielectric 104. The area i or below where the conductive channel is to be formed.
  • a second ion implantation step is performed on the structure shown in Fig. 2c to form an amorphous region.
  • the implantation depth of the second ion implantation step is a second depth d2, and d2 is smaller than dl.
  • the ion implantation depth can be controlled by adjusting the ion implantation energy and dose.
  • the structure shown in Fig. 2d is annealed to obtain a structure as shown in Fig. 1.
  • FIG. 3 shows a schematic diagram of a transistor in accordance with a second embodiment of the present invention.
  • the transistor 200 shown in FIG. 3 differs from the transistor 100 of FIG. 1 in that each of the source region 108 and the drain region 110 includes an adjacent channel region 112, perpendicular to the surface of the semiconductor substrate 102. A set of three dislocations arranged in the direction.
  • the method of fabricating the transistor 200 in the present embodiment further includes performing a third ion implantation step, the third ion implantation, on the first region 108 and the second region 110, as compared with the method of fabricating the transistor 100.
  • the depth d3 is smaller than the second depth d2 described above, as shown in FIG.
  • each set of dislocations in the source region 108 and the drain region 1 10 includes three dislocations.
  • the present invention is not limited thereto, and each set of dislocations in the source region 108 and the drain region 1 10 may further include more dislocations, and accordingly, the formation of the more is performed by performing more ion implantation steps having different implantation depths.
  • a greater number of dislocations can be formed adjacent to the channel region as needed.
  • the tensile stress acting on the channel region is further enhanced, and accordingly, the electron mobility of the channel region is further increased.
  • the present invention is not limited thereto, and the mask may be utilized before any ion implantation step.
  • the layer completely covers one of the first region and the second region and performs ion implantation only on the other one, thereby asymmetrically forming dislocations in the source region 108 and the drain region 110.
  • a mask layer is formed on the first region 108 and not on the second region 110 before the second ion implantation step is performed, so that the second ion implantation step is not performed on the first region 108.
  • the first region 108 contains only one dislocation
  • the second region 1 10 includes a set of two dislocations arranged in a direction perpendicular to the surface of the semiconductor substrate 102, as shown in the figure. 5 is shown.
  • the transistor manufacturing method in the present embodiment is different from the methods described in the first embodiment and the second embodiment in that it may be selected before the one or more of the ion implantation steps, in the first
  • a mask layer is selectively formed on at least one of the region 108 and the second region 1 10 to cover a portion thereof and, in a preferred embodiment, expose a portion thereof adjacent to the gate.
  • a mask layer covering a portion thereof is formed on the second region 110 before the second ion implantation step is performed.
  • 6 shows a structure obtained after the second ion implantation step is performed after the mask layer 14 is formed, in which the portion of the second region 1 10 covered by the mask layer 14 is not implanted with ions.
  • the structure of Fig. 6 is annealed to obtain the transistor 300 shown in Fig. 7.
  • the mask layer 14 is still shown in Fig. 7, the mask layer 14 can be removed before annealing.
  • the mask layer may be a photoresist layer or a hard mask layer formed of a dielectric material such as silicon oxide and/or silicon nitride.
  • the selective formation of a hard mask layer can be achieved, for example, by a photolithography process well known in the art.
  • the pattern of the mask layer formed each time may be the same or different.
  • the mask layer is formed of a dielectric material such as silicon oxide and/or silicon nitride, so that it is not necessary to remove the mask layer during the annealing process when the mask layer patterns are the same, so that only one formation is required. The step of masking the layer.
  • one of the ion implantation steps may be employed A mask layer is selectively formed on at least one of the first region 108 and the second region 1 10 to cover at least two portions that are not adjacent thereto.
  • overlays are formed on both the first region 108 and the second region 110 before performing the first and second ion implantation steps, respectively.
  • the mask layer 1 14 of the two portions which are not adjacent to each other is then subjected to a first ion implantation step, and the resulting structure is as shown in FIG.
  • the second ion implantation step and the corresponding annealing are performed.
  • FIG. 9 shows a schematic diagram of the finally formed transistor 100a in this example. Although mask layer 1 14 is still shown in Figure 9, in practice mask layer 14 may have been removed prior to annealing.
  • a mask layer 1 14 covering two portions that are not adjacent thereto is formed only on one of the first region 108 and the second region 110, and no mask is formed on the other.
  • the layer is either completely covered by the mask layer.
  • a mask layer may be selectively formed on one of the first region 108 and the second region 1 10 before one or more of the ion implantation steps, To cover at least two portions that are not adjacent thereto, a mask layer is selectively formed on the other of the first region 108 and the second region 1 10 to cover a portion thereof.
  • a mask layer 142 covering a portion thereof is formed on the first region 108 before the second ion implantation step is performed, and A mask layer 1 14 covering the two portions not adjacent thereto is formed on the second region 1 10, and then a second ion implantation step is performed, and the resulting structure is as shown in FIG.
  • Figure 1 1 shows a schematic diagram of the resulting transistor 100b in this example.
  • the mask layer 14 is still shown in Fig. 11, the mask layer 14 can be removed before annealing.
  • the crystal body tube in the present embodiment further contains at least one other dislocation in at least one of the source region and the drain region, the at least another dislocation being formed in comparison with the first and second embodiments.
  • the dislocations are further away from the channel region.
  • the direction parallel to the surface of the substrate is defined as the lateral direction of the transistor, and the direction perpendicular to the surface of the substrate is defined as the longitudinal direction of the transistor.
  • the fourth embodiment and its variant can obtain more dislocations in the longitudinal direction of the transistor, and further can obtain more in the lateral direction of the transistor. Dislocation, thereby making Further increase in the tensile stress (and thus the electron mobility of the channel region) for the channel region is made possible.
  • the transistors in the above first to fourth embodiments and their modifications may be NMOS transistors.
  • the semiconductor substrate may include an NMOS device region and a PMOS device region, wherein the transistor fabrication method according to the present invention is performed only in the NMOS device region.
  • the transistor may further include a semiconductor layer (not shown) over the source region 108 and the drain region 110, such as Si, silicon carbide, silicon germanium or a germanium layer, the semiconductor layer is such that the dislocations are not exposed to a free surface; the method of fabricating the transistor includes forming the semiconductor layer over the source and drain regions after performing a doping step of forming source and drain. The semiconductor layer is such that dislocations are not exposed to the free surface to prevent a reduction in tensile stress that may result from exposure to the free surface due to misalignment.
  • a semiconductor layer (not shown) over the source region 108 and the drain region 110, such as Si, silicon carbide, silicon germanium or a germanium layer, the semiconductor layer is such that the dislocations are not exposed to a free surface; the method of fabricating the transistor includes forming the semiconductor layer over the source and drain regions after performing a doping step of forming source and drain.
  • the semiconductor layer is such that dislocations are not exposed to the free surface to prevent a reduction in
  • the ions implanted in the ion implantation step may be, for example, one or a combination of silicon, germanium, phosphorus, boron or arsenic.
  • the annealing temperature may be greater than 40 (TC, preferably 50 (rC - 900 ° C, and the annealing time may be from several seconds to several minutes).
  • steps of doping, spacer formation, and source/drain contact formation of source and drain regions well known in the art may be performed to Form a complete device.
  • the source and drain doping processes are performed after the formation of the dislocations
  • the present invention is not limited thereto, and the dislocations may be formed at any appropriate stage, for example, the formation source may be performed.
  • the dislocations are formed after doping with the drain.
  • the semiconductor substrate described above may be a Si substrate, a SiGe substrate, a SiC substrate, or a III-V semiconductor substrate (eg, GaAs, GaN, etc.).
  • the gate dielectric may be selected from Si0 2 , Hf0 2 > H SiO, HfSiON, HfTaO, HfTiO, HfZrO, A1 2 0 3 , La 2 0 3 , Zr0 2 , LaA10 or a combination thereof. From Poly-Si, Ti, Co, Ni, Al, W, an alloy of the above metals or a metal silicide.

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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Insulated Gate Type Field-Effect Transistor (AREA)

Description

晶体管及其制造方法 技术领域
本发明涉及半导体器件制造领域， 尤其涉及晶体管及其制造方法。 背景技术
通常， 集成电路包含形成在衬底上的 NMOS ( n型金属 -氧化物-半 导体） 晶体管和 PMOS ( p型金属 -氧化物-半导体） 晶体管的组合。 集 成电路的性能与其所包含的晶体管的性能有直接关系。 因此， 希望提 高晶体管的驱动电流以增强其性能。
美国专利申请 No .2010010381068105 A公开了一种晶体管，在该晶 体管的沟道区与源 /漏区之间形成位错， 这种位错产生拉应力， 该拉应 力提高了沟道中的电子迁移率， 由此晶体管的驱动电流得以增加。 图 12a-12c示出了这种位错的形成。 在图 12a中， 对已经形成了栅极电介 质 2和栅极 3的半导体衬底 1进行硅注入， 从而形成非晶区域， 如图 中阴影部分所示。 在图 12b 中， 对该半导体衬底 1进行退火， 使得非 晶区域再结晶， 在再结晶过程中， 水平方向和竖直方向上的两个不同 的晶体生长前端相遇， 如图中箭头所示， 从而形成了图 12c 所示的位 错。 发明内容
本发明的目的是提供一种晶体管以及一种晶体管的制造方法。
本发明的制造晶体管的方法包括如下步骤：
在半导体衬底上形成栅极电介质；
在所述栅极电介质上形成栅极； 一区和第二区进行第一离子注入步骤， 该第一离.子注入步骤的注入深 度为第一深度；
在该第一离子注入步骤之后进行退火， 使得在所述第一区和第二 区中均形成位错；
对所述第一区和第二区之一或二者执行第二离子注入步骤， 该第 二离子注入步骤的注入深度为第二深度， 该第二深度小于第二 以及
在该第二离子注入步骤之后进行退火， 使得在所述第 区和第二 区中均形成位错。
根据本发明的晶体管制造方法， 通过在源区和漏区进行不同深度 的非晶化 -结晶步骤， 能够毗邻沟道区形成更多的位错， 更多的位错可 导致更多的拉应力作用于沟道， 从而使增强沟道区的电子迁移率成为 可能。
本发明的晶体管包括：
半导体衬底；
形成在所述半导体衬底上的栅极电介质；
形成在所述栅极电介质上的栅极；
位于所述栅极电介质下方的沟道区；
位于所述半导体衬底中、 且分别在所述沟道区两侧的源区和漏区， . 其中至少所述源区和漏区之一包含毗邻所述沟道区、 在垂直于所 述半导体衬底的表面的方向上排列的一组位错， 该组位错包含至少两 个位错。
根据本发明的晶体管由于毗邻沟道区具有更多的位错， 因此作用 在沟道区的拉应力可以得到增强， 沟道区的电子迁移率也可以得以进 一步增力口。
本发明的其它方面和优点将在以下结合附图更详细地描述。 附图说明
图 1示出了根据本发明第一实施方式的晶体管的示意图。
图 2a- d是根据本发明的第一实施方式制造晶体管的方法步骤的示 意图
图 3示出了根据本发明的第二实施方式的晶体管的示意图。
图 4 示出了根据本发明的第二实施方式的晶体管的制造方法的步 骤之一的示意图。
图 5示出根据本发明的第三实施方式的变型的晶体管的示意图。 图 6 示出了根据本发明的第四实施方式的晶体管的制造方法的步 骤之一的示意图。 图 7示出了根据本发明的第四实施方式的晶体管的示意图。
图 8 示出了根据本发明的第四实施方式的一个变型的晶体管的制 造方法的步骤之一的示意图。
图 9 示出了根据本发明的第四实施方式的一个变型的晶体管的示 意图。
图 10示出了根据本发明的第四实施方式的另一个变型的晶体管的 制造方法的步骤之一的示意图。
图 1 1示出了根据本发明的第四实施方式的另一个变型的晶体管的 示意图。 .
图 12a-c示出了现有技术中位错的形成。 具体实施方式
以下结合附图描述本发明的优选实施例。 附图是示意性的并未按 比例绘制， 且只是为了说明本发明的实施例而并不意图限制本发明的 保护范围。 贯穿附图相同的附图标记表示相同或相似的部件。 为了使 本发明的技术方案更加清楚， 本领域熟知的工艺步骤及器件结构在此 省略。
<第一实施方式 >
图 1 示出了根据本发明第一实施方式的晶体管的示意图。 如图 1 所示， 晶体管 100包括半导体衬底 102、 形成在所述半导体衬底 102上 的栅极电介质 104、 形成在所述栅极电介质 104上的栅极 106、 分别位 于栅极 106两侧的源区 108和漏区 1 10、 以及沟道区 1 12 , 所述沟道区 1 12位于源区 108和漏区 1 10之间且在栅极电介质 104下方。在图 1所 示的晶体管 100 中， 所述源区 108和漏区 1 10都包含毗邻所述沟道区 位错包含两个位 4告 101。 所述位错对沟道区 〗12施加拉应力（如图中箭 头所示） ， 这种拉应力使得沟道区的电子迁移率增加。 相比于现有技 术， 本发明毗邻沟道区形成了更多数量的位错， 使得作用于沟道区 1 12 的拉应力得以增强， 从而进一步提高沟道区 1 12 的电子迁移率成为可 能。
此外， 晶体管 100还包括形成在栅极电介质 104和栅极 106侧面 的侧墙以及源极和漏极接触等， 由于这些结构对于本领域技术人员而 言是熟知的， 因此并未在附图中示出以及详细描述。
接下来， 参照图 2a-d描述根据第一实施方式的晶体管制造方法。 如图 2a所示， 在半导体衬底 102上形成栅极电介质 104和栅极 106。 接下来， 如图 2b所示， 对位于所述半导体村底 102中且分别在所述栅极 106两侧的所述半导体衬底的第一区 108和第二区 1 10进行第一离子注 入步骤， 由此在所述第一区 108和第二区 1 10中形成非晶区， 如图中阴 影部分所示， 该第一离子注入步骤的注入深度为第一深度 dl。 所述第 一区 108和第二区 1 10分别是要形成晶体管的源和漏的区域， 或者分别 是已经通过执行离子注入形成了晶体管的源和漏的区域。 在图 2b所示 的步骤之后执行退火， 使得非晶区再结晶。 在再结晶过程中， 不同的 晶体生长前端相遇， 从而在所述第一区 108和第二区 1 10中形成位错， 如图 2c所示， 所述位错毗邻位于所述栅极电介质 104下方的要形成导电 沟道的区 i或。
接下来， 对图 2c所示的结构进行第二离子注入步骤， 以形成非晶 区， 如图 2d所示， 该第二离子注入步骤的注入深度为第二深度 d2， d2 小于 dl。 可以通过调节离子注入能量和剂量来控制离子注入深度。 然 后， 对图 2d所示的结构进行退火， 从而得到如图 1所示的结构。
<第二实施方式 >
图 3 示出了根据本发明的第二实施方式的晶体管的示意图。 图 3 所示晶体管 200与图 1所示晶体管 100的区别在于， 所述源区 108和 漏区 1 10中的每一个均包括毗邻沟道区 1 12、 在垂直于半导体衬底 102 的表面的方向上排列的一组三个位错。
相应地， 与制造晶体管 100 的方法相比较， 本实施方式中制造晶 体管 200的方法还包括对所述第一区 108和第二区 1 10执^"第三离子 注入步骤， 该第三离子注入的深度 d3小于上述第二深度 d2 , 如图 4所 示。
虽然图 3示出了源区 108和漏区 1 10中的每组位错包括三个位错。 但是本发明不限于此， 源区 108和漏区 1 10 中的每组位错还可以包括 更多的位错， 相应地， 通过执行更多个注入深度不同的离子注入步骤 来形成所述更多的位错， 其中在后离子注入步骤的注入深度小于先前 离子注入步骤的注入深度。
根据本实施方式， 可以根据需要毗邻沟道区形成更多数目的位错， 更进一步增强了作用于沟道区的拉应力， 相应地， 沟道区的电子迁移 率进一步增加也成为可能。
<第三实施方式 >
尽管在以上对第一实施方式和第二实施方式的描述中， 在晶体管 的源区和漏区中位错是对称的， 但是本发明不限于此， 可以通过在任 一次离子注入步骤之前利用掩膜层将第一区和第二区中的一个完全覆 盖而仅对其中的另一个执行离子注入， 从而在源区 108和漏区 1 10 中 不对称地形成位错。 例如， 在执行第二离子注入步骤之前， 在第一区 108而不在第二区 1 10上形成掩膜层，从而不对第一区 108执行第二离 子注入步骤。 这样， 在所得到的晶体管 200a中， 第一区 108仅包含一 个位错， 而第二区 1 10 包含在垂直于半导体衬底 102的表面的方向上 排列的一组两个位错， 如图 5所示。
<第四实施方式 >
本实施方式中的晶体管制造方法与前述第一实施方式和第二实施 方式所述的方法的不同之处在于， 可以选择在所述离子注入步骤中的 一个或多个之前， 在所述第一区 108和第二区 1 10 中的至少一个上选 择性地形成掩膜层， 以覆盖其一部分并且在一个优选实施例中使得其 毗邻所述栅极的部分暴露。 作为一个非限制性的例子， 除了执行第一 实施方式中的方法步骤之外， 还在执行第二离子注入步骤之前， 在第 二区 1 10上形成覆盖其一部分的掩模层 1 14, 图 6示出了在形成该掩膜 层 1 14后进行第二离子注入步骤后所得到的结构， 其中第二区 1 10 中 被掩膜层 1 14覆盖的部分未被注入离子。 对图 6的结构进行退火， 从 而得到图 7所示的晶体管 300， 虽然在图 7中仍然示出了掩膜层 1 14， 但实际上掩膜层 1 14可以在退火之前已经被除去。
所述掩膜层可以是光刻胶层， 或者是由诸如氧化硅和 /或氮化硅的 电介质材料形成的硬掩膜层。 而选择性地形成硬掩膜层例如可以通过 本领域熟知的光刻工艺实现。 在所述离子注入步骤中的多个之前选择 性地形成掩膜层的情况下， 每一次所形成的掩膜层的图案可以相同或 不同。 在一个优选方案中， 所述掩膜层由诸如氧化硅和 /或氮化硅的电 介质材料形成， 这样在掩膜层图案相同时的退火过程中无需除去掩膜 层， 从而仅需执行一次形成掩膜层的步骤。
作为第四实施方式的一个变型， 可以在所述离子注入步骤中的一 个或多个之前， 在所述第一区 108和第二区 1 10 中的至少一个上选择 性地形成掩膜层， 以覆盖其不相邻的至少两个部分。 作为一个非限制 性的例子， 除了执行第一实施方式中的方法步骤之外， 还分别在执行 第一和第二离子注入步骤之前， 在第一区 108和第二区 1 10上均形成 覆盖其不相邻的两个部分的掩模层 1 14， 而后进行第一离子注入步骤， 所得到的结构如图 8所示。 接下来， 在不去除掩膜层 1 14的情况下， 执行第二离子注入步骤及相应的退火。 注意， 掩膜层 1 14在第一区 108 和第二区 1 10上的位置可以是关于晶体管 100的栅极 106对称的或不 对称的。 图 9示出了该例子中最终形成的晶体管 100a的示意图。 虽然 在图 9中仍然示出了掩膜层 1 14,但实际上掩膜层 1 14可以在退火之前 已经被除去。
在另一个非限制性的例子中， 仅在第一区 108和第二区 1 10之一 上形成覆盖其不相邻的两个部分的掩模层 1 14,而另一个上不形成掩膜 层或者完全被掩膜层覆盖。
作为第四实施方式的又一个变型， 可以在所述离子注入步骤中的 一个或多个之前， 在所述第一区 108和第二区 1 10 中的一个上选择性 地形成掩膜层， 以覆盖其不相邻的至少两个部分， 而在所述第一区 108 和第二区 1 10 中的另一个上选择性地形成掩膜层， 以覆盖其一部分。 作为一个非限制性的例子， 除了执行第一实施方式中的方法步骤之外， 还在执行第二离子注入步骤之前， 在第一区 108 上形成覆盖其一部分 的掩膜层 1 14 ,且在第二区 1 10上形成覆盖其不相邻的两个部分的掩模 层 1 14， 而后进行第二离子注入步骤， 所得到的结构如图 10所示。 图 1 1 示出了该例子中最终得到的晶体管 100b的示意图。 虽然在图 1 1 中 仍然示出了掩膜层 1 14 ,但实际上掩膜层 1 14可以在退火之前已经被除 去。
由此， 本实施方式中的晶 _体管在至少所述源区和漏区之一还含有 至少另一个位错， 该至少另一个位错相比于第一和第二实施方式中形 成的位错更远离所述沟道区。
将平行于衬底表面的方向规定为晶体管的横向， 将垂直于衬底表 面的方向规定为晶体管的纵向。 相比于第一、 第二、 第三实施方式， 该第四实施方式及其变型除了可以在晶体管的纵向上得到更多的位错 之外， 还可以进一步在晶体管的横向上得到更多的位错， 从而使得作 用于沟道区的拉应力 （并且因此沟道区的电子迁移率） 更进一步增加 成为可能。
上述第一至四实施方式及其变型中的晶体管可以是 NMOS 晶体 管。
上述第一至四实施方式及其变型所述的晶体管制造方法中， 所述 半导体衬底可以包括 NMOS器件区和 PMOS器件区， 其中仅在 NMOS 器件区执行根据本发明的晶体管制造方法。
上述第一至四实施方式及其变型中： 晶体管还可以包括位于所述 源区 108和漏区 1 10上方的半导体层 （未示出） ， 该半导体层例如是 Si、 碳化硅、 硅锗或者锗层， 该半导体层使得所述位错不暴露于自由表 面； 晶体管的制造方法包括在进行形成源和漏的掺杂步骤之后在源区 和漏区上方形成所述半导体层。 所述半导体层使得位错不暴露于自由 表面， 以防止由于错位暴露于自由表面而可能导致的拉应力减小。
在上述第一至四实施方式及其变型中， 离子注入步骤中注入的离 子例如可以是硅、 锗、 磷、 硼或砷中的一种或其组合。
在上述第一至四实施方式及其变型中， 退火温度可以大于 40(TC , 优选为 50(rC -900°C， 退火时间可以为数秒至数分钟。
在上述第一至四实施方式及其变型中所描述的方法步骤之后， 可 以执行本领域熟知的源区和漏区的掺杂、 侧墙形成以及源极 /漏极接触 的形成等步骤， 以形成完整的器件。
尽管在上面的描述中， 在形成位错之后再进行形成源和漏的掺杂 工艺， 然而， 本发明不限于此， 可以在任何适当的阶段形成所述位错， 例如， 可以在进行形成源和漏的掺杂之后形成所述位错。
此外， 上文所描述的半导体衬底可以是 Si衬底、 SiGe衬底、 SiC 衬底、 或 III-V 半导体衬底 （例如， GaAs、 GaN等等） 。 栅极电介质 可以使用 Si02、 Hf02 > H SiO、 HfSiON、 HfTaO, HfTiO, HfZrO、 A1203、 La203、Zr02、LaA10中的一种或其组合，栅极的材料可以选自 Poly-Si 、 Ti 、 Co、 Ni、 Al、 W, 上述金属的合金或者金属硅化物。
以上通过示例性实施例描述了本发明的晶体管及制造晶体管的方 法， 然而， 这并不意图限制本发明的保护范围。 本领域技术人员可以 想到的上述实施例的任何修改或变型都落入由所附权利要求限定的本 发明的范围内。

Claims

1. 一种晶体管的制造方法， 包括如下步骤：
在半导体衬底上形成栅极电介质；
在所述栅极电介质上形成栅极； 一区和第二区进行第一离子注入步骤， 该第一离子注入步骤的注入深 度为第一深度； 权
在该第一离子注入步骤之后进行退火， 使得在所述第一区和第二 区中均形成位错；
对所述第一区和第二区之一或二者执行第二离子注入步骤， 该第 二离子注入步骤的注入深度为第二深度， 该第二深度小于第一深度； 以及 求
在该第二离子注入步骤之后进行退火， 使得在所述第一区和第二 区中均形成位错。
2. 根据权利要求 1所述的方法，其中在执行所述第一离子注入步骤 和第二离子注入步骤之一或二者之前， 在所述第一区和第二区上方选 择性地形成掩膜层， 使得至少所述第一区和第二区之一的一部分或多 个部分被覆盖， 所述多个部分中相邻的部分之间未被所述掩膜层覆盖。
3. 根据权利要求 1所述的方法， 所述半导体衬底包括 NMOS器件区 和 PMOS器件区， 其中仅在 NMOS器件区内执行所述第一离子注入步骤 和第二离子注入步骤以及相应的退火。
4. 根据权利要求 1所述的方法， 进一步包括：
对所述第一区和第二区之一或二者执行至少一次另外的离子注入 步骤， 该至少一次另外的离子注入步骤的注入深度小于所述第二注入 深度， 并且执行多次另外的离子注入步骤的情况下， 在后的离子注入 步骤的注入深度小于在前的离子注入步骤的注入深度；
在该至少一次另外的离子注入步骤中的每一次之后进行退火， 以 在所述第一区和第二区中形成位错。
5. 根据权利要求 4所述的方法， 其中在所述第一离子注入步骤、 第 二离子注入步骤以及所述至少一次另外的离子注入步骤中的一个或多 个之前， 在所述第一区和第二区上方选择性地形成掩膜层， 使得至少 所述第一区和第二区之一的一部分或多个部分被覆盖， 所述多个部分 中相邻的部分之间未被所述掩膜层覆盖。
6. 根据权利要求 4所述的方法， 所述半导体衬底包括 NMOS器件区 和 PMOS器件区， 其中仅在 NMOS器件区内执行所述第一离子注入步 骤、 第二离子注入步骤、 所述至少另一次离子注入步骤以及相应的退 火。
7. 根据权利要求 1-6之一所述的方法， 其中所述位错对位于所述第 一区和第二区之间的沟道区施加拉应力， 使得沟道区的电子迁移率增 加。
8. 根据权利要求 1-6之一所述的方法， 进一步包括在所述第一区和 第二区上方形成半导体层， 以使得所述位错不暴露于自由表面。
9. 根据权利要求 1-6之一所述的方法， 其中所述第一区和第二区分 别是晶体管的源区和漏区， 或者所述第一区和第二区分别是要形成晶 体管的源区和漏区的区域。
10. 根据权利要求 1-6之一所述的方法， 其中所述半导体衬底是 Si 衬底、 SiGe衬底、 SiC衬底、 GaAs衬底或 GaN衬底。
1 1. 一种晶体管， 包括：
半导体衬底；
形成在所述半导体衬底上的栅极电介质；
形成在所述栅极电介质上的栅极；
位于所述栅极电介质下方的沟道区；
位于所述半导体衬底中、 且分别在所述沟道区两侧的源区和漏区， 其中至少所述源区和漏区之一包含毗邻所述沟道区、 在垂直于所 述半导体衬底的表面的方向上排列的一组位错， 该组位错包含至少两 个位错。
12. 根据权利要求 1 1所述的晶体管，其中至少所述源区和漏区之一 还含有至少另一个位错， 该至少另一个位错相比于所述第一组位错更 远离所述沟道区。
13. 根据权利要求 1 1所述的晶体管，其中至少所述源区和漏区之一 错， 该至少另一组位错包含至少两个位错， 且相比于所述第一组位错 更远离所述沟道区。
14. 根据权利要求 11-13中任一项所述的晶体管， 其中所述位错对 位于源区和漏区之间的沟道区施加拉应力， 使得所述沟道区的电子迁 移率增加。
15. 根据权利要求 11-13中任一项所述的晶体管， 其中所述晶体管 为 NMOS晶体管。
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