WO2011113268A1 - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

Info

Publication number
WO2011113268A1
WO2011113268A1 PCT/CN2010/077248 CN2010077248W WO2011113268A1 WO 2011113268 A1 WO2011113268 A1 WO 2011113268A1 CN 2010077248 W CN2010077248 W CN 2010077248W WO 2011113268 A1 WO2011113268 A1 WO 2011113268A1
Authority
WO
WIPO (PCT)
Prior art keywords
germanium
ion implantation
source
implantation process
semiconductor device
Prior art date
Application number
PCT/CN2010/077248
Other languages
English (en)
French (fr)
Inventor
安霞
郭岳
云全新
黄如
张兴
Original Assignee
北京大学
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 北京大学 filed Critical 北京大学
Priority to US13/201,618 priority Critical patent/US8541847B2/en
Publication of WO2011113268A1 publication Critical patent/WO2011113268A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials

Definitions

  • the present invention relates to the field of ultra-large scale integrated circuit manufacturing technology, and in particular to a method of fabricating a semiconductor device.
  • MOSFET metal-oxide-semiconductor field effect transistor
  • tantalum materials Compared with silicon materials, tantalum materials have four times the hole mobility under low electric field and three times that of silicon materials. Therefore, tantalum materials as a new channel material are higher and more Symmetrical carrier mobility has become one of the promising development directions for high-speed MOSFET devices, and it is also a hot research topic.
  • strain technology is a good choice, in addition to using new channel materials such as germanium to improve carrier mobility.
  • new channel materials such as germanium to improve carrier mobility.
  • the process induced strain method has become a widely used strain introduction method in mass production in the industry with its convenient and effective characteristics.
  • Strain technology For NMOS devices uniaxial tensile stress can be introduced in a direction parallel to the plane of the channel, or compressive stress can be introduced simultaneously in a direction perpendicular to the plane of the channel, thereby increasing the mobility of electrons in the channel.
  • the present invention provides a method of fabricating a semiconductor device, comprising: providing a germanium-based semiconductor substrate having a plurality of active regions and a device isolation region between the plurality of active regions The active region has a gate dielectric layer and a gate over the gate dielectric layer, and the active region includes a source-drain extension region and a deep source-drain region;
  • An annealing process is performed on the germanium-based semiconductor substrate after the third ion implantation process.
  • the germanium-based semiconductor substrate is of a P-type, and the second ion implantation process and/or the third ion implantation process implants an N-type impurity.
  • the germanium-based semiconductor substrate includes a bulk germanium substrate, a germanium insulating substrate, or a silicon-based epitaxial germanium substrate.
  • the N-type impurity includes one or more of P, As, and Sb.
  • the annealing process is rapid thermal annealing.
  • the doping amount of the first ion implantation process is l xel3 to l xel6 atom/cm 2 .
  • the doping amount of the third ion implantation process is 5xel4 to lxel6 atom/cm 2 .
  • the source-drain extension region introduces a uniaxial tensile stress parallel to the channel direction and a compressive stress perpendicular to the channel plane in the germanium channel after the stone or carbon implantation.
  • the step of performing an annealing process on the germanium-based semiconductor substrate after the third ion implantation process further includes: forming sidewall spacers on both sides of the gate.
  • the present invention also provides a semiconductor device, including:
  • Silicon-based semiconductor substrate Silicon-based semiconductor substrate, a plurality of active regions in the germanium-based semiconductor substrate and a device isolation region between the plurality of active regions,
  • the active region including a source-drain extension region and a deep source-drain region;
  • the method includes a silicon or carbon impurity in the source/drain extension region; and the silicon or carbon impurity is doped by performing a first ion implantation process on the source/drain extension region.
  • the invention provides a semiconductor device and a preparation method thereof.
  • a NMOS-based NMOS transistor as an example, an uniaxial tensile stress is effectively introduced into a channel of a NMOS-based NMOS transistor by appropriately changing a NMOS-based NMOS transistor process, while being vertical
  • the compressive stress is introduced in the direction of the plane of the channel.
  • an impurity silicon or carbon implantation ie, a first ion implantation process
  • a deep Source/drain implantation ie, third ion implantation process
  • the semiconductor device and the preparation method thereof provided by the invention have five advantages: First, for a germanium-based NMOS transistor, the silicon or carbon impurity of the germanium has an atomic radius smaller than that of the germanium.
  • silicon or carbon impurity implantation can hinder the diffusion of specific impurities (such as P, As or Sb) in the ruthenium, especially the impurity with the dominant diffusion mechanism.
  • silicon or carbon impurity implantation will suppress the diffusion of these impurities in the ruthenium substrate, and it is easy to form a shallow junction.
  • the solid solubility of the N-type impurity in silicon is much larger than the solid solubility in the yttrium, the implantation of the impurity silicon will improve the solid solubility of the N-type impurity in the extended source-drain structure to some extent. Conducive to the formation of shallow knots.
  • the present invention introduces stress by optimizing the process, and hardly increases the complexity of the process. Sexuality, which can effectively introduce large stresses and obtain better device performance, is an economical and efficient method to improve the performance of NMOS-based NMOS devices.
  • the mobility of carriers in the channel can be improved.
  • the electrical performance of the semiconductor device is significantly improved.
  • FIG. 1(a) to (i) are schematic views showing a method of fabricating a NMOS-based NMOS transistor according to a preferred embodiment of the present invention
  • FIG. 2 is a flow chart of a method of fabricating a germanium-based NMOS transistor in accordance with a preferred embodiment of the present invention.
  • the present invention proposes a novel semiconductor device and a manufacturing method thereof, which can introduce a uniaxial tensile stress in a parallel ⁇ channel direction by using a process induced stress method, and introduce a compressive stress in a direction perpendicular to the channel plane. Increase the mobility of carriers in the ⁇ channel.
  • the semiconductor device provided by the present invention includes:
  • the active region includes a source-drain extension region and a deep source-drain region.
  • the source and drain extension regions are formed by first and second ion implantation processes; the deep source and drain regions are formed by a third ion implantation process.
  • the source/drain extension region has silicon or carbon impurities; and the silicon or carbon impurities are doped by performing a first ion implantation process on the source/drain extension region.
  • the germanium-based semiconductor substrate is of a P-type, and N-type impurities are implanted in the second and third ion implantation processes.
  • the germanium-based semiconductor substrate is of the N-type, and the second and third ion implantation processes are implanted with P-type impurities.
  • a plurality of doped active regions are used to form the channel, the source region, and the drain region.
  • the germanium-based semiconductor substrate includes a bulk germanium substrate, a germanium insulating substrate, or a silicon-based epitaxial germanium substrate.
  • the semiconductor device structure may be a conventional structure, a recessed source/drain structure or a lifted source/drain structure, wherein Ge:C, Ge:Si:C or Si:C source and drain may also be applied.
  • the manufacturing method of the above semiconductor device includes:
  • the first ion implantation process is implanted with silicon, and the doping amount of silicon is l X el3 to l X el6 atom/cm 2 .
  • C impurities may also be used, and the doping amount is also l X el3 to l X el6 atom/cm 2 .
  • the second ion implantation process may be doped with yttrium, As or Sb, and doping dose lXel3 to 5 ⁇ el4 atom/cm 2 .
  • the third ion implantation process may be doped with yttrium, As or Sb, and doping doses of 5el4 to lel6atom/cm 2 .
  • An annealing process is performed on the germanium-based semiconductor substrate after the third ion implantation process.
  • the annealing process is, for example, rapid thermal annealing.
  • the heat treatment annealing temperature is 300 ° C to 800 ° C:.
  • the annealing process is not limited to rapid heat treatment annealing, and may be a new type of annealing technology existing and future developed, such as laser annealing or flash annealing.
  • FIG. 1(a) to (i) are schematic views showing a method of fabricating a NMOS-based NMOS transistor according to a preferred embodiment of the present invention
  • FIG. 2 is a flow chart showing a method of fabricating a NMOS-based NMOS transistor according to a preferred embodiment of the present invention.
  • the method of manufacturing the germanium-based NMOS transistor includes the following steps: Step S1: providing a germanium-based semiconductor substrate. As shown in FIG.
  • a semiconductor germanium substrate 1 is doped with a P-type substrate, wherein the semiconductor germanium substrate 1 may be a bulk germanium substrate, a germanium-insulated insulating (GOI) substrate or an epitaxial Ge-line on Si. Bottom and so on.
  • Step S2 forming a shallow trench isolation region in the germanium-based semiconductor substrate. As shown in Figure 1 (b), shallow trench isolation zone 2.
  • a silicon oxide and silicon nitride layer (not shown) is deposited on the germanium-based semiconductor substrate 1, and the position of the shallow trench is defined by photolithography, and then the silicon nitride is etched by reactive ion etching.
  • Step S3 forming a gate dielectric layer on the active region. As shown in FIG.
  • the gate dielectric layer 3 may be made of silicon dioxide, a high-k gate dielectric layer, hafnium oxynitride or hafnium oxide.
  • the LPCVD method is used to fabricate the dioxide.
  • the gate is prepared by using a polysilicon gate or a metal gate or a FUSI gate.
  • a polysilicon gate layer (not shown) is deposited, and the polysilicon gate layer is doped with polysilicon. The impurity phosphorus is doped, and then the polysilicon gate layer is photolithographically etched to form the gate electrode 4, as shown in FIG. 1(d).
  • Step S5 performing a first ion implantation process on the source-drain extension regions in the active regions on both sides of the gate.
  • the source-drain extension region 5 in the germanium-based semiconductor substrate 1 can be doped with silicon impurities far exceeding the normal solid solubility by the ion implantation method for introducing parallel trenches in the germanium channel.
  • the uniaxial tensile stress of the track and the compressive stress perpendicular to the plane of the channel prevent the diffusion of source and drain impurities and increase the solid solubility of the N-type impurity.
  • the dose of silicon impurity implanted is l xel3 to l xel6 atom/cm- 2 .
  • Step S6 performing a second ion implantation process on the source-drain extension regions in the active regions on both sides of the gate.
  • impurity phosphorus is selected.
  • a lightly doped N-type implant region 6 is formed on the surface of the active region of the germanium-based semiconductor substrate 1 by ion implantation of impurity phosphorus as a source-drain extension region, which ensures a lower resistance.
  • the dose of the implanted impurity is 1 xel3 to 5xel4 atom/cnT 2 .
  • Step S7 forming side walls on both sides of the gate.
  • the spacers may be formed by depositing Si0 2 or Si 3 N 4 and etching to form sidewall spacers, or may be double-sided walls of Si 3 N 4 and then Si 2 2 .
  • a self-aligned isolation structure 7 ie, a side wall 7 is formed on the side of the gate electrode 4 by using a method of depositing silicon dioxide and dry etching, and the side wall 7 is formed.
  • the lower region is the extended source drain region 6, and the region between the extended source drain region 6 and the shallow trench isolation region 2 is the deep source drain region 8.
  • Step S8 performing a third ion implantation process on the deep source drain region and rapidly annealing the entire germanium substrate.
  • an NMOS source-drain N-type heavily doped region (deep source/drain region) 8 is formed by ion implantation of impurity phosphorus.
  • the dose of the implanted impurity is 5el4 to lel6 atom/cm- 2 .
  • the entire ruthenium-based substrate 1 is subjected to an activation heat treatment of implanting impurities, and a peak annealing is performed to facilitate formation of a shallow junction, and the implanted impurity silicon and the twice implanted impurity phosphorus are activated, and the annealing condition is 300 ° C to 800. °C.
  • Step S9 forming a contact hole and a metal wiring on the source and drain regions.
  • a silicide source/drain process may first be selected to reduce parasitic resistance, and then a dielectric layer 9 is deposited for isolation between the metal wiring layer 10 and the device layer and photolithographically formed to form contact holes.
  • Sputtering a metal layer, such as Al, Al-Ti Etc., and lithography defines a wiring pattern.
  • a metal wiring pattern is formed, and finally a metal wiring layer 10 is formed by a low temperature annealing process alloy.
  • the semiconductor device provided by the present invention is formed as shown in FIG. 1(i).
  • a new and better performance ⁇ -based strain NMOS transistor can be fabricated.
  • the lattice mismatch of the source-drain extension region can effectively introduce suitable stress into the channel, enhance the mobility of electrons in the channel, and improve device performance.
  • the impurity silicon can hinder the diffusion of the impurity phosphorus in the germanium substrate, and can also improve the solid solubility of the phosphorus in the germanium to a certain extent, and is favorable for forming a shallow junction.
  • this method has hardly increased the complexity of the process. Therefore, the semiconductor device and its manufacturing method simply and effectively improve the performance of the NMOS-based NMOS transistor with respect to the prior art fabrication method.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Manufacturing & Machinery (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Description

半导体器件及其制造方法 技术领域
本发明属于超大规模集成电路制造技术领域， 具体涉及一种半导体器件 的制造方法。
背景技术
半导体技术的发展基本上遵循摩尔定律已 40多年， 金属-氧化物-半导体 场效应晶体管 (MOSFET)几何尺寸的减小是提高器件速度并降低生产成本的 主要手段。 随着集成电路的发展和器件尺寸的缩小， 带来一些不能忽视的问 题， 比如沟道纵向电场的增加， 越来越薄的栅极氧化层与硅衬底的界面粗糙 度变差， 以及沟道杂质散射的增加等， 这些都使载流子的迁移率退化。 为了 有较大的驱动电流来保证较高的器件速度， 迁移率退化导致的驱动电流减小 是一个棘手且亟待解决的问题。
相比硅材料， 锗材料在低电场下空穴迁移率是硅材料的 4倍， 电子迁移 率是硅材料的 3倍， 因此， 锗材料作为一种新的沟道材料以其更高、 更加对 称的载流子迁移率成为高速 MOSFET器件很有希望的发展方向之一， 也是目 前研究的热点。
此外， 除了运用新的沟道材料（例如锗） 来提高载流子的迁移率， 应变 技术也是一个不错的选择。 通过改变器件材料、 结构或者工艺等方法在器件 沟道中施加应力， 改变半导体的能带结构， 可以增加沟道中载流子的迁移率， 进而提升器件的驱动电流， 改善器件性能。 其中， 工艺诱生应变方法以其方 便、 有效的特点成为目前业界大规模生产中广泛釆用的应变引入方法。 应变 技术对于 NMOS器件， 可以在平行于沟道平面的方向引入单轴拉应力， 也可 以同时在垂直于沟道平面的方向引入压应力， 从而增加电子在沟道中的迁移 率。
总而言之， 如何提高沟道中载流子的迁移率是现有超大规模集成电路制 造技术中亟待解决的难题之一。 发明内容
本发明解决的问题是提供一种半导体器件及其制造方法， 可以提高沟道 中载流子的迁移率。 为解决上述问题， 本发明提供一种半导体器件的制造方法， 包括： 提供锗基半导体衬底， 所述锗基半导体衬底具有多个有源区以及多个有 源区之间的器件隔离区， 所述有源区上具有栅极介质层和栅极介质层之上的 栅极， 所述有源区包括源漏扩展区和深源漏区；
对所述源漏扩展区进行第一离子注入工艺， 所述第一离子注入工艺中的 注入离子包括娃或碳；
对所述源漏扩展区进行第二离子注入工艺；
对所述深源漏区进行第三离子注入工艺；
对经过第三离子注入工艺之后的锗基半导体衬底进行退火工艺。
所述锗基半导体衬底为 P型， 所述第二离子注入工艺和 /或第三离子注入 工艺中注入 N型杂质。
所述锗基半导体衬底包括体锗衬底、 锗覆绝缘衬底或硅基外延锗衬底。 所述 N型杂质包括 P、 As和 Sb中的一种或多种。
所述退火工艺为快速热处理退火。
所述第一离子注入工艺的掺杂剂量为 l xel3至 l xel6 atom/cm2。
所述第三离子注入工艺的掺杂剂量为 5xel4至 l xel6 atom/cm2。
源漏扩展区进行石圭或碳注入后在锗沟道中引入平行于沟道方向的单轴张 应力和垂直于沟道平面压应力。
对经过第三离子注入工艺之后的锗基半导体衬底进行退火工艺的步骤前 还包括： 在所述栅极两侧形成侧墙。
相应的， 本发明还提供一种半导体器件， 包括：
锗基半导体衬底， 所述锗基半导体衬底中的多个有源区以及多个有源区之间的器件隔离 区，
所述有源区上的栅极介质层和栅极介质层之上的栅极， 所述有源区包括 源漏扩展区和深源漏区；
其特征在于， 所述源漏扩展区内具有硅或碳杂质； 所述硅或碳杂质通过对所述源漏扩展区进行第一离子注入工艺而掺杂。
与现有技术相比， 上述技术方案具有以下优点：
本发明提出了一种半导体器件及其制备方法，以锗基 NMOS晶体管为例， 通过适当的改变锗基 NMOS晶体管工艺过程，在锗基 NMOS晶体管的沟道中 有效引入单轴拉应力， 同时在垂直于沟道平面的方向引入压应力。 具体的， 在形成传统扩展源漏结构之前， 在源漏扩展区的注入（即第二离子注入工艺） 之前增加了杂质硅或碳的注入 (即第一离子注入工艺），并与随后的深源漏区注 入（即第三离子注入工艺） 杂质一起退火激活。 与现有技术相比， 本发明提 出的半导体器件及其制备方法有五点优势： 第一， 对于锗基 NMOS晶体管来 说， 釆用的硅或碳杂质的原子半径比锗的原子半径小， 通过注入引入器件的 源漏扩展区， 使得晶格不匹配， 并在锗沟道中引入平行于沟道方向的单轴张 应力和垂直于沟道平面压应力， 上述两种应力会提高电子的迁移率。 第二， 由于硅或碳直接注入在源漏扩展区， 相对于在有源区之上沉积薄膜的方法而 言， 更加直接对锗沟道施加应力， 使得引入应力更加有效。 应力的引入， 可 以在不改变器件其他条件的情况下， 提高器件的电流驱动能力， 显著地增强 NMOS晶体管的性能。 第三， 硅或碳杂质注入会阻碍特定杂质 （例如 P、 As 或 Sb )在锗中的扩散， 尤其是替位扩散为主导机制的杂质。 这样， 在退火激 活后， 硅或碳杂质注入将抑制这些杂质在锗衬底中的扩散， 容易形成浅结。 第四， 由于 N型杂质在硅中的固溶度要远大于在锗中的固溶度， 杂质硅的注 入会在一定程度上改善扩展源漏结构中 N型杂质的固溶度， 同样有利于浅结 的形成。 第五， 本发明通过优化工艺方法引入应力， 几乎没有增加工艺复杂 性， 能有效引入较大的应力并得到较好的器件性能， 是经济且高效的提升锗 基 NMOS器件性能的方法。
因此， 上述半导体器件及其制造方法， 可以提高沟道中载流子的迁移率。 使得半导体器件的电学性能明显改善。
附图说明
通过附图所示， 本发明的上述及其它目的、 特征和优势将更加清晰。 在 全部附图中相同的附图标记指示相同的部分。 并未刻意按实际尺寸等比例缩 放绘制附图， 重点在于示出本发明的主旨。
图 1 ( a ) ~ ( i )为本发明优选实施例锗基 NMOS晶体管的制造方法的示 意图；
图 2为本发明优选实施例锗基 NMOS晶体管的制造方法的流程图。
具体实施方式
为使本发明的上述目的、 特征和优点能够更加明显易懂， 下面结合附图 对本发明的具体实施方式做详细的说明。
在下面的描述中阐述了很多具体细节以便于充分理解本发明， 但是本发 明还可以釆用其他不同于在此描述的其它方式来实施， 本领域技术人员可以 在不违背本发明内涵的情况下做类似推广， 因此本发明不受下面公开的具体 实施例的限制。 其次， 本发明结合示意图进行详细描述， 在详述本发明实施例时， 为便 于说明， 表示器件结构的剖面图会不依一般比例作局部放大， 而且所述示意 图只是示例， 其在此不应限制本发明保护的范围。 此外， 在实际制作中应包 含长度、 宽度及深度的三维空间尺寸。
正如本发明背景技术的介绍， 发明人经过研究发现， 若将应变技术合适 地运用在锗基器件， 可以结合新沟道材料和应变技术两种技术的优势， 解决 器件迁移率退化的问题， 并能进一步提高器件的电流驱动能力， 提升器件性 能。 如果能通过工艺优化， 在不增加工艺复杂性的前提下， 在器件制备过程 中 )入合适的应力， 将极大地改善锗基晶体管的性能。 基于此， 本发明提出一种新的半导体器件及其制造方法， 可以运用工艺 诱生应力方法在平行锗沟道方向引入单轴拉应力， 同时在垂直于沟道平面的 方向引入压应力， 可增加载流子在锗沟道中的迁移率。 本发明提供的半导体器件， 包括：
锗基半导体衬底， 所述锗基半导体衬底中的多个有源区以及多个有源区 之间的器件隔离区， 所述有源区上的栅极介质层和栅极介质层之上的栅极， 所述栅极两侧优选的还具有侧墙。 所述有源区包括源漏扩展区和深源漏区。 该源漏扩展区通过第一和第二离子注入工艺形成； 该深源漏区通过第三离子 注入工艺形成。 其中， 所述源漏扩展区内具有硅或碳杂质； 所述硅或碳杂质通过对所述 源漏扩展区进行第一离子注入工艺而掺杂。
所述锗基半导体衬底为 P型， 则所述第二和第三离子注入工艺中注入 N 型杂质。 所述锗基半导体衬底为 N型， 则所述第二和第三离子注入工艺中注 入 P型杂质。 掺杂后的多个有源区用于形成沟道、 源区和漏区。 所述锗基半导体衬底包括体锗衬底、 锗覆绝缘衬底或硅基外延锗衬底。 该半导体器件结构可以是传统结构、 凹陷源漏结构或者提升源漏结构， 其中 也可应用 Ge:C、 Ge:Si:C或者 Si:C源漏。 上述半导体器件的制造方法， 包括：
提供锗基半导体衬底， 所述锗基半导体衬底具有多个有源区以及多个有 源区之间的器件隔离区， 所述有源区上具有栅极介质层和栅极介质层之上的 栅极， 所述有源区包括源漏扩展区和深源漏区； 对所述源漏扩展区进行第一离子注入工艺， 所述第一离子注入工艺中的 注入离子包括硅或碳； 优选的， 该第一离子注入工艺釆用硅注入， 硅的掺杂 剂量为 l X el3至 l X el6 atom/cm2。 另夕卜， 也可以釆用 C杂质， 掺杂剂量也为 l X el3至 l X el6 atom/cm2。 对所述源漏扩展区进行第二离子注入工艺； 该第二离子注入工艺可以掺 杂卩、 As或 Sb, 掺杂剂量 lXel3至 5Xel4atom/cm2。
对所述深源漏区进行第三离子注入工艺； 所述第三离子注入工艺可以掺 杂卩、 As或 Sb, 掺杂剂量 5el4至 lel6atom/cm2。
对经过第三离子注入工艺之后的锗基半导体衬底进行退火工艺。 该退火 工艺例如为快速热处理退火， 优选的， 热处理退火温度为 300°C至 800°C：。 所 述退火工艺并不限于快速热处理退火， 也可以为现有以及未来开发的新型退 火技术， 例如激光退火或闪光退火等。
下面以锗基 NMOS晶体管为例结合附图详细说明本发明提供的半导体器 件及其制造方法的优选实施例。 图 1 (a) ~ (i) 为本发明优选实施例锗基 NMOS晶体管的制造方法的示 意图， 图 2为本发明优选实施例锗基 NMOS晶体管的制造方法的流程图。 如图 2所示， 所述锗基 NMOS晶体管的制造方法包括如下步骤： 步骤 S1: 提供锗基半导体衬底。 如图 1 (a)所示， 一半导体锗衬底 1, P 型衬底掺杂， 其中半导体锗衬底 1可以是体锗衬底、 锗覆绝缘（GOI)衬底或 Si上外延 Ge衬底等。 步骤 S2: 在所述锗基半导体衬底内形成浅沟槽隔离区。 如图 1 (b) 中浅 沟槽隔离区 2。在所述锗基半导体衬底 1上淀积氧化硅和氮化硅层（图中未示 出）， 通过光刻定义出浅沟槽的位置， 之后利用反应离子刻蚀技术刻蚀氮化硅 和氧化硅层， 进而刻蚀锗基半导体衬底， 形成浅沟槽， 并利用 CVD方法在锗 基衬底上淀积多晶硅或氧化硅回填隔离槽， 最后利用化学机械抛光技术 (CMP)将表面磨平， 从而形成多个浅沟槽隔离区 2, 各个多个浅沟槽隔离区 2之间为形成半导体器件的有源区。 器件隔离不局限于浅槽隔离（STI), 也可 以釆用场氧隔离等技术。 步骤 S3: 在所述有源区上形成栅极介质层。 如图 1 (c)中栅极介质层 3, 该栅极介质层 3可以釆用二氧化硅、 高 k栅介质层、 氮氧化锗、 或者二氧化 锗， 本实施例釆 LPCVD方法制作二氧化硅栅极介质层。 步骤 S4: 在所述栅极介质层上形成栅极。 栅极的制备可以釆用多晶硅栅 或者金属栅或者 FUSI栅等， 本实施例中釆用淀积多晶硅栅层（图中未示出）， 并对所述多晶硅栅层进行多晶硅掺杂注入， 以掺入杂质磷， 然后所述光刻并 刻蚀多晶硅栅层形成栅极 4, 参照图 1 ( d )所示。
步骤 S5: 在所述栅极两侧的有源区内的源漏扩展区域进行第一离子注入 工艺。 如图 1 ( e )所示， 通过离子注入方法可以在锗基半导体衬底 1 中的源 漏扩展区 5掺入远远超过正常固溶度的硅杂质， 用来在锗沟道中引入平行沟 道的单轴张应力和垂直于沟道平面的压应力， 同时阻碍源漏杂质的扩散并提 升 N型杂质固溶度。 注入硅杂质的剂量为 l xel3至 l xel6 atom/cm-2。
步骤 S6: 在所述栅极两侧的有源区内的源漏扩展区进行第二离子注入工 艺。 本实施例选用杂质磷。 如图 1 ( f ) 所示， 通过离子注入杂质磷在锗基半 导体衬底 1的有源区表面形成较轻掺杂的 N型注入区域 6, 作为源漏扩展区， 在保证较低电阻的同时， 减小漏端与沟道处电场强度。 注入碑杂质的剂量为 1 xel3至 5xel4 atom/cnT2。 步骤 S7: 在栅极两侧形成侧墙。 侧墙可以通过淀积 Si02或 Si3N4并且刻 蚀形成侧墙， 也可以釆用先 Si3N4再 Si02的双侧墙。 如图 1 ( g )所示， 本实 施例釆用淀积二氧化硅并且干法刻蚀的方法， 在栅极 4 的侧面形成自对准隔 离结构 7 (即侧墙 7 ), 侧墙 7下方的区域为扩展源漏区 6, 而扩展源漏区 6与 浅沟槽隔离区 2之间的区域为深源漏区 8。
步骤 S8: 对深源漏区进行第三离子注入工艺并对整个锗基衬底快速热处 理退火。 如图 1 ( h )所示， 通过离子注入杂质磷形成 NMOS源漏 N型重掺杂 区域（深源漏区 ) 8。 注入碑杂质的剂量为 5el4至 lel6 atom/cm-2。 随后对整 个锗基衬底 1进行注入杂质的激活热处理， 釆用尖峰退火， 有利于形成浅结， 并使得注入的杂质硅，和两次注入的杂质磷激活，退火条件为 300°C至 800°C。
步骤 S9: 在源漏区上形成接触孔和金属连线。 在此工艺步骤中首先可以 选择釆用硅化物源漏工艺来降低寄生电阻， 然后淀积介质层 9用于金属连线 层 10和器件层之间的隔离并光刻形成接触孔。再溅射金属层， 比如 Al、 Al-Ti 等， 并光刻定义出连线图形， 经过刻蚀后， 既形成金属连线图形， 最后通过 低温退火过程合金， 形成金属连线层 10。 最后形成本发明所提供的半导体器 件如图 1 ( i )所示。
利用本实施例提出的半导体器件的制造方法， 可以制造出一种新的性能 更好的锗基应变 NMOS晶体管。 通过杂质硅的注入， 可以由源漏扩展区晶格 失配有效地在锗沟道中引入合适应力， 增强沟道中电子的迁移率， 提高器件 性能。 另外， 杂质硅可以阻碍杂质磷在锗衬底中的扩散， 还可以一定程度上 提高磷在锗中的固溶度， 有利于形成浅结。 同时， 本方法几乎没有增加工艺 的复杂性。 因此相对于现有工艺制备方法， 所述半导体器件及其制造方法简 单有效地提升了锗基 NMOS晶体管的性能。
以上所述， 仅是本发明的较佳实施例而已， 并非对本发明作任何形式上 的限制。 此外， 所述半导体器件及其制造方法也可以用于 PMOS晶体管， 在 此不再赘述。 虽然本发明已以较佳实施例披露如上， 然而并非用以限定本发明。 任何 熟悉本领域的技术人员， 在不脱离本发明技术方案范围情况下， 都可利用上 述揭示的方法和技术内容对本发明技术方案作出许多可能的变动和修饰， 或 修改为等同变化的等效实施例。 因此， 凡是未脱离本发明技术方案的内容， 均仍属于本发明技术方案保护的范围内。

Claims

权 利 要 求 书
1、 一种半导体器件的制造方法， 其特征在于， 包括：
提供锗基半导体衬底， 所述锗基半导体衬底具有多个有源区以及多个有 源区之间的器件隔离区， 所述有源区上具有栅极介质层和栅极介质层之上的 栅极， 所述有源区包括源漏扩展区和深源漏区；
对所述源漏扩展区进行第一离子注入工艺， 所述第一离子注入工艺中的 注入离子包括娃或碳；
对所述源漏扩展区进行第二离子注入工艺；
对所述深源漏区进行第三离子注入工艺；
对经过第三离子注入工艺之后的锗基半导体衬底进行退火工艺。
2、 根据权利要求 1所述的半导体器件的制造方法， 其特征在于， 所述锗 基半导体衬底为 p型， 所述第二离子注入工艺和 /或第三离子注入工艺中注入
N型杂质。
3、 根据权利要求 2所述的半导体器件的制造方法， 其特征在于， 所述锗 基半导体衬底包括体锗衬底、 锗覆绝缘衬底或硅基外延锗衬底。
4、 根据权利要求 2所述的半导体器件的制造方法， 其特征在于， 所述 N 型杂质包括 P、 As和 Sb中的一种或多种。
5、 根据权利要求 1所述的半导体器件的制造方法， 其特征在于， 所述退 火工艺包括快速热处理退火、 激光退火或闪光退火。
6、 根据权利要求 1所述的半导体器件的制造方法， 其特征在于， 所述第 一离子注入工艺的掺杂剂量为 l X el3至 l X el6 atom/cm2。
7、 根据权利要求 1或 2所述的半导体器件的制造方法， 其特征在于， 所 述第三离子注入工艺的掺杂剂量为 5 X el4至 l X el6 atom/cm2。
8、 根据权利要求 1所述的半导体器件的制造方法， 其特征在于， 源漏扩 展区进行石圭或碳注入后在错沟道中引入平行于沟道方向的单轴张应力和垂直 于沟道平面压应力。
9、 根据权利要求 1所述的半导体器件的制造方法， 其特征在于， 对经过 第三离子注入工艺之后的锗基半导体衬底进行退火工艺的步骤前还包括： 在 所述栅极两侧形成侧墙。
10、 一种半导体器件， 包括： 锗基半导体衬底，
所述锗基半导体衬底中的多个有源区以及多个有源区之间的器件隔离 区，
所述有源区上的栅极介质层和栅极介质层之上的栅极， 所述有源区包括 源漏扩展区和深源漏区；
其特征在于， 所述源漏扩展区内具有硅或碳杂质；
所述硅或碳杂质通过对所述源漏扩展区进行第一离子注入工艺而掺杂。
PCT/CN2010/077248 2010-03-15 2010-09-25 半导体器件及其制造方法 WO2011113268A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US13/201,618 US8541847B2 (en) 2010-03-15 2010-09-25 Semiconductor device and method for fabricating the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201010125795.0 2010-03-15
CN201010125795.0A CN102194748B (zh) 2010-03-15 2010-03-15 半导体器件及其制造方法

Publications (1)

Publication Number Publication Date
WO2011113268A1 true WO2011113268A1 (zh) 2011-09-22

Family

ID=44602573

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2010/077248 WO2011113268A1 (zh) 2010-03-15 2010-09-25 半导体器件及其制造方法

Country Status (3)

Country Link
US (1) US8541847B2 (zh)
CN (1) CN102194748B (zh)
WO (1) WO2011113268A1 (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103456611A (zh) * 2013-03-06 2013-12-18 深圳信息职业技术学院 提高锗材料n型掺杂载流子浓度的方法与应用
US9419138B2 (en) * 2014-09-29 2016-08-16 International Business Machines Corporation Embedded carbon-doped germanium as stressor for germanium nFET devices
TWI722502B (zh) * 2018-07-25 2021-03-21 國立清華大學 具有第ｉｖａ族離子佈植的金氧半場效電晶體之結構與製造方法
CN112701044B (zh) * 2020-12-28 2022-11-29 中国科学院半导体研究所 应变锗沟道晶体管及其制备方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1763084A2 (en) * 2005-09-09 2007-03-14 Fujitsu Limited Field-effect transistor and method for fabricating the same
CN101150070A (zh) * 2006-09-19 2008-03-26 台湾积体电路制造股份有限公司 半导体结构及其形成方法
CN101359685A (zh) * 2007-07-31 2009-02-04 国际商业机器公司 半导体器件及制作方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4855246A (en) * 1984-08-27 1989-08-08 International Business Machines Corporation Fabrication of a gaas short channel lightly doped drain mesfet
JP2003249649A (ja) * 2002-02-26 2003-09-05 Toshiba Corp 半導体装置及びその製造方法
JP4236992B2 (ja) * 2002-06-24 2009-03-11 富士通マイクロエレクトロニクス株式会社 半導体装置の製造方法
JP2004172389A (ja) * 2002-11-20 2004-06-17 Renesas Technology Corp 半導体装置およびその製造方法
WO2004068588A1 (ja) * 2003-01-31 2004-08-12 Fujitsu Limited 半導体装置及びその製造方法
TWI463526B (zh) * 2004-06-24 2014-12-01 Ibm 改良具應力矽之ｃｍｏｓ元件的方法及以該方法製備而成的元件
US7479431B2 (en) * 2004-12-17 2009-01-20 Intel Corporation Strained NMOS transistor featuring deep carbon doped regions and raised donor doped source and drain
US7498642B2 (en) * 2005-04-25 2009-03-03 Taiwan Semiconductor Manufacturing Company, Ltd. Profile confinement to improve transistor performance
US7947546B2 (en) * 2005-10-31 2011-05-24 Chartered Semiconductor Manufacturing, Ltd. Implant damage control by in-situ C doping during SiGe epitaxy for device applications
JP5283827B2 (ja) * 2006-03-30 2013-09-04 富士通セミコンダクター株式会社 半導体装置の製造方法
US20080305598A1 (en) * 2007-06-07 2008-12-11 Horsky Thomas N Ion implantation device and a method of semiconductor manufacturing by the implantation of ions derived from carborane molecular species
US8859377B2 (en) * 2007-06-29 2014-10-14 Texas Instruments Incorporated Damage implantation of a cap layer
US7763510B1 (en) * 2009-01-07 2010-07-27 Freescale Semiconductor, Inc. Method for PFET enhancement

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1763084A2 (en) * 2005-09-09 2007-03-14 Fujitsu Limited Field-effect transistor and method for fabricating the same
CN101150070A (zh) * 2006-09-19 2008-03-26 台湾积体电路制造股份有限公司 半导体结构及其形成方法
CN101359685A (zh) * 2007-07-31 2009-02-04 国际商业机器公司 半导体器件及制作方法

Also Published As

Publication number Publication date
US20120187495A1 (en) 2012-07-26
CN102194748B (zh) 2014-04-16
CN102194748A (zh) 2011-09-21
US8541847B2 (en) 2013-09-24

Similar Documents

Publication Publication Date Title
TWI260091B (en) Semiconductor device and method of manufacturing the same
US8043919B2 (en) Method of fabricating semiconductor device
TWI446453B (zh) 受應力之場效電晶體以及其製造方法
US7701010B2 (en) Method of fabricating transistor including buried insulating layer and transistor fabricated using the same
WO2011079596A1 (zh) Mosfet结构及其制作方法
JP5671294B2 (ja) 集積回路及びその製造方法
US20060234455A1 (en) Structures and methods for forming a locally strained transistor
JP2006019727A (ja) 勾配付き組み込みシリコン−ゲルマニウムのソース−ドレイン及び／又は延長部をもつ、歪みｐ型ｍｏｓｆｅｔの構造及びこれを製造する方法
WO2012055143A1 (zh) 晶体管及其制造方法
JP2006278974A (ja) 半導体装置及びその製造方法
JP2006303501A (ja) ＰＦＥＴの移動度を強化したステップ埋め込みＳｉＧｅ構造
JP2008515188A (ja) 歪みチャネル、及びヘテロ接合ソース／ドレインを有する半導体素子を形成する方法
CN102339859B (zh) Mos晶体管及其形成方法
WO2012100463A1 (zh) 一种形成半导体结构的方法
US8828812B2 (en) Silicon-germanium heterojunction tunnel field effect transistor and preparation method thereof
JP4992710B2 (ja) Ｍｏｓトランジスタ及びその製造方法
US8450171B2 (en) Strained semiconductor device and method of making same
CN104217955B (zh) N型晶体管及其制作方法、互补金属氧化物半导体
KR20130049540A (ko) 스트레스 기억 기술(ｓｍｔ)을 이용한 반도체 장치의 제조 방법
WO2013173944A1 (zh) 半导体器件制造方法
WO2013139064A1 (zh) 一种半导体结构及其制造方法
WO2011113268A1 (zh) 半导体器件及其制造方法
WO2012055142A1 (zh) 晶体管及其制造方法
WO2011131053A1 (zh) 一种源漏区、接触孔及其形成方法
JP2006128427A (ja) 半導体装置の製造方法及び半導体装置

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 13201618

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 10847737

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 10847737

Country of ref document: EP

Kind code of ref document: A1