CN102194748A - 半导体器件及其制造方法 - Google Patents
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Abstract
本发明提供一种半导体器件及其制造方法,其中所述制造方法包括:提供锗基半导体衬底,所述锗基半导体衬底具有多个有源区以及多个有源区之间的器件隔离区,所述有源区上具有栅极介质层和栅极介质层之上的栅极,所述有源区包括源漏扩展区和深源漏区;对所述源漏扩展区进行第一离子注入工艺,所述第一离子注入工艺中的注入离子包括硅或碳;对所述源漏扩展区进行第二离子注入工艺;对所述深源漏区进行第三离子注入工艺;对经过第三离子注入工艺之后的锗基半导体衬底进行退火工艺。所述半导体器件的制造方法,通过杂质硅或碳注入,可以由源漏扩展区晶格失配有效地在锗沟道中引入合适应力,增强沟道中电子的迁移率,提高器件性能。
Description
技术领域
本发明属于超大规模集成电路制造技术领域,具体涉及一种半导体器件的制造方法。
背景技术
半导体技术的发展基本上遵循摩尔定律已40多年,金属-氧化物-半导体场效应晶体管(MOSFET)几何尺寸的减小是提高器件速度并降低生产成本的主要手段。随着集成电路的发展和器件尺寸的缩小,带来一些不能忽视的问题,比如沟道纵向电场的增加,越来越薄的栅极氧化层与硅衬底的界面粗糙度变差,以及沟道杂质散射的增加等,这些都使载流子的迁移率退化。为了有较大的驱动电流来保证较高的器件速度,迁移率退化导致的驱动电流减小是一个棘手且亟待解决的问题。
相比硅材料,锗材料在低电场下空穴迁移率是硅材料的4倍,电子迁移率是硅材料的3倍,因此,锗材料作为一种新的沟道材料以其更高、更加对称的载流子迁移率成为高速MOSFET器件很有希望的发展方向之一,也是目前研究的热点。
此外,除了运用新的沟道材料(例如锗)来提高载流子的迁移率,应变技术也是一个不错的选择。通过改变器件材料、结构或者工艺等方法在器件沟道中施加应力,改变半导体的能带结构,可以增加沟道中载流子的迁移率,进而提升器件的驱动电流,改善器件性能。其中,工艺诱生应变方法以其方便、有效的特点成为目前业界大规模生产中广泛采用的应变引入方法。应变技术对于NMOS器件,可以在平行于沟道平面的方向引入单轴拉应力,也可以同时在垂直于沟道平面的方向引入压应力,从而增加电子在沟道中的迁移率。
总而言之,如何提高沟道中载流子的迁移率是现有超大规模集成电路制造技术中亟待解决的难题之一。
发明内容
本发明解决的问题是提供一种半导体器件及其制造方法,可以提高沟道中载流子的迁移率。
为解决上述问题,本发明提供一种半导体器件的制造方法,包括:
提供锗基半导体衬底,所述锗基半导体衬底具有多个有源区以及多个有源区之间的器件隔离区,所述有源区上具有栅极介质层和栅极介质层之上的栅极,所述有源区包括源漏扩展区和深源漏区;
对所述源漏扩展区进行第一离子注入工艺,所述第一离子注入工艺中的注入离子包括硅或碳;
对所述源漏扩展区进行第二离子注入工艺;
对所述深源漏区进行第三离子注入工艺;
对经过第三离子注入工艺之后的锗基半导体衬底进行退火工艺。
所述锗基半导体衬底为P型,所述第二离子注入工艺和/或第三离子注入工艺中注入N型杂质。
所述锗基半导体衬底包括体锗衬底、锗覆绝缘衬底或硅基外延锗衬底。
所述N型杂质包括P、As和Sb中的一种或多种。
所述退火工艺为快速热处理退火。
所述第一离子注入工艺的掺杂剂量为1×e13至1×e16atom/cm2。
所述第三离子注入工艺的掺杂剂量为5×e14至1×e16atom/cm2。
源漏扩展区进行硅或碳注入后在锗沟道中引入平行于沟道方向的单轴张应力和垂直于沟道平面压应力。
对经过第三离子注入工艺之后的锗基半导体衬底进行退火工艺的步骤前还包括:在所述栅极两侧形成侧墙。
相应的,本发明还提供一种半导体器件,包括:
锗基半导体衬底,
所述锗基半导体衬底中的多个有源区以及多个有源区之间的器件隔离区,
所述有源区上的栅极介质层和栅极介质层之上的栅极,所述有源区包括源漏扩展区和深源漏区;
其特征在于,所述源漏扩展区内具有硅或碳杂质;
所述硅或碳杂质通过对所述源漏扩展区进行第一离子注入工艺而掺杂。
与现有技术相比,上述技术方案具有以下优点:
本发明提出了一种半导体器件及其制备方法,以锗基NMOS晶体管为例,通过适当的改变锗基NMOS晶体管工艺过程,在锗基NMOS晶体管的沟道中有效引入单轴拉应力,同时在垂直于沟道平面的方向引入压应力。具体的,在形成传统扩展源漏结构之前,在源漏扩展区的注入(即第二离子注入工艺)之前增加了杂质硅或碳的注入(即第一离子注入工艺),并与随后的深源漏区注入(即第三离子注入工艺)杂质一起退火激活。与现有技术相比,本发明提出的半导体器件及其制备方法有五点优势:第一,对于锗基NMOS晶体管来说,采用的硅或碳杂质的原子半径比锗的原子半径小,通过注入引入器件的源漏扩展区,使得晶格不匹配,并在锗沟道中引入平行于沟道方向的单轴张应力和垂直于沟道平面压应力,上述两种应力会提高电子的迁移率。第二,由于硅或碳直接注入在源漏扩展区,相对于在有源区之上沉积薄膜的方法而言,更加直接对锗沟道施加应力,使得引入应力更加有效。应力的引入,可以在不改变器件其他条件的情况下,提高器件的电流驱动能力,显著地增强NMOS晶体管的性能。第三,硅或碳杂质注入会阻碍特定杂质(例如P、As或Sb)在锗中的扩散,尤其是替位扩散为主导机制的杂质。这样,在退火激活后,硅或碳杂质注入将抑制这些杂质在锗衬底中的扩散,容易形成浅结。第四,由于N型杂质在硅中的固溶度要远大于在锗中的固溶度,杂质硅的注入会在一定程度上改善扩展源漏结构中N型杂质的固溶度,同样有利于浅结的形成。第五,本发明通过优化工艺方法引入应力,几乎没有增加工艺复杂性,能有效引入较大的应力并得到较好的器件性能,是经济且高效的提升锗基NMOS器件性能的方法。
因此,上述半导体器件及其制造方法,可以提高沟道中载流子的迁移率。使得半导体器件的电学性能明显改善。
附图说明
通过附图所示,本发明的上述及其它目的、特征和优势将更加清晰。在全部附图中相同的附图标记指示相同的部分。并未刻意按实际尺寸等比例缩放绘制附图,重点在于示出本发明的主旨。
图1(a)~(i)为本发明优选实施例锗基NMOS晶体管的制造方法的示意图;
图2为本发明优选实施例锗基NMOS晶体管的制造方法的流程图。
具体实施方式
为使本发明的上述目的、特征和优点能够更加明显易懂,下面结合附图对本发明的具体实施方式做详细的说明。
在下面的描述中阐述了很多具体细节以便于充分理解本发明,但是本发明还可以采用其他不同于在此描述的其它方式来实施,本领域技术人员可以在不违背本发明内涵的情况下做类似推广,因此本发明不受下面公开的具体实施例的限制。
其次,本发明结合示意图进行详细描述,在详述本发明实施例时,为便于说明,表示器件结构的剖面图会不依一般比例作局部放大,而且所述示意图只是示例,其在此不应限制本发明保护的范围。此外,在实际制作中应包含长度、宽度及深度的三维空间尺寸。
正如本发明背景技术的介绍,发明人经过研究发现,若将应变技术合适地运用在锗基器件,可以结合新沟道材料和应变技术两种技术的优势,解决器件迁移率退化的问题,并能进一步提高器件的电流驱动能力,提升器件性能。如果能通过工艺优化,在不增加工艺复杂性的前提下,在器件制备过程中引入合适的应力,将极大地改善锗基晶体管的性能。
基于此,本发明提出一种新的半导体器件及其制造方法,可以运用工艺诱生应力方法在平行锗沟道方向引入单轴拉应力,同时在垂直于沟道平面的方向引入压应力,可增加载流子在锗沟道中的迁移率。
本发明提供的半导体器件,包括:
锗基半导体衬底,所述锗基半导体衬底中的多个有源区以及多个有源区之间的器件隔离区,所述有源区上的栅极介质层和栅极介质层之上的栅极,所述栅极两侧优选的还具有侧墙。所述有源区包括源漏扩展区和深源漏区。该源漏扩展区通过第一和第二离子注入工艺形成;该深源漏区通过第三离子注入工艺形成。
其中,所述源漏扩展区内具有硅或碳杂质;所述硅或碳杂质通过对所述源漏扩展区进行第一离子注入工艺而掺杂。
所述锗基半导体衬底为P型,则所述第二和第三离子注入工艺中注入N型杂质。所述锗基半导体衬底为N型,则所述第二和第三离子注入工艺中注入P型杂质。掺杂后的多个有源区用于形成沟道、源区和漏区。
所述锗基半导体衬底包括体锗衬底、锗覆绝缘衬底或硅基外延锗衬底。该半导体器件结构可以是传统结构、凹陷源漏结构或者提升源漏结构,其中也可应用Ge:C、Ge:Si:C或者Si:C源漏。
上述半导体器件的制造方法,包括:
提供锗基半导体衬底,所述锗基半导体衬底具有多个有源区以及多个有源区之间的器件隔离区,所述有源区上具有栅极介质层和栅极介质层之上的栅极,所述有源区包括源漏扩展区和深源漏区;
对所述源漏扩展区进行第一离子注入工艺,所述第一离子注入工艺中的注入离子包括硅或碳;优选的,该第一离子注入工艺采用硅注入,硅的掺杂剂量为1×e13至1×e16atom/cm2。另外,也可以采用C杂质,掺杂剂量也为1×e13至1×e16atom/cm2。
对所述源漏扩展区进行第二离子注入工艺;该第二离子注入工艺可以掺杂P、As或Sb,掺杂剂量1×e13至5×e14atom/cm2。
对所述深源漏区进行第三离子注入工艺;所述第三离子注入工艺可以掺杂P、As或Sb,掺杂剂量5e14至1e16atom/cm2。
对经过第三离子注入工艺之后的锗基半导体衬底进行退火工艺。该退火工艺例如为快速热处理退火,优选的,热处理退火温度为300℃至800℃。所述退火工艺并不限于快速热处理退火,也可以为现有以及未来开发的新型退火技术,例如激光退火或闪光退火等。
下面以锗基NMOS晶体管为例结合附图详细说明本发明提供的半导体器件及其制造方法的优选实施例。
图1(a)~(i)为本发明优选实施例锗基NMOS晶体管的制造方法的示意图,图2为本发明优选实施例锗基NMOS晶体管的制造方法的流程图。
如图2所示,所述锗基NMOS晶体管的制造方法包括如下步骤:
步骤S1:提供锗基半导体衬底。如图1(a)所示,一半导体锗衬底1,P型衬底掺杂,其中半导体锗衬底1可以是体锗衬底、锗覆绝缘(GOI)衬底或Si上外延Ge衬底等。
步骤S2:在所述锗基半导体衬底内形成浅沟槽隔离区。如图1(b)中浅沟槽隔离区2。在所述锗基半导体衬底1上淀积氧化硅和氮化硅层(图中未示出),通过光刻定义出浅沟槽的位置,之后利用反应离子刻蚀技术刻蚀氮化硅和氧化硅层,进而刻蚀锗基半导体衬底,形成浅沟槽,并利用CVD方法在锗基衬底上淀积多晶硅或氧化硅回填隔离槽,最后利用化学机械抛光技术(CMP)将表面磨平,从而形成多个浅沟槽隔离区2,各个多个浅沟槽隔离区2之间为形成半导体器件的有源区。器件隔离不局限于浅槽隔离(STI),也可以采用场氧隔离等技术。
步骤S3:在所述有源区上形成栅极介质层。如图1(c)中栅极介质层3,该栅极介质层3可以采用二氧化硅、高k栅介质层、氮氧化锗、或者二氧化锗,本实施例采LPCVD方法制作二氧化硅栅极介质层。
步骤S4:在所述栅极介质层上形成栅极。栅极的制备可以采用多晶硅栅或者金属栅或者FUSI栅等,本实施例中采用淀积多晶硅栅层(图中未示出),并对所述多晶硅栅层进行多晶硅掺杂注入,以掺入杂质磷,然后所述光刻并刻蚀多晶硅栅层形成栅极4,参照图1(d)所示。
步骤S5:在所述栅极两侧的有源区内的源漏扩展区域进行第一离子注入工艺。如图1(e)所示,通过离子注入方法可以在锗基半导体衬底1中的源漏扩展区5掺入远远超过正常固溶度的硅杂质,用来在锗沟道中引入平行沟道的单轴张应力和垂直于沟道平面的压应力,同时阻碍源漏杂质的扩散并提升N型杂质固溶度。注入硅杂质的剂量为1×e13至1×e16atom/cm-2。
步骤S6:在所述栅极两侧的有源区内的源漏扩展区进行第二离子注入工艺。本实施例选用杂质磷。如图1(f)所示,通过离子注入杂质磷在锗基半导体衬底1的有源区表面形成较轻掺杂的N型注入区域6,作为源漏扩展区,在保证较低电阻的同时,减小漏端与沟道处电场强度。注入磷杂质的剂量为1×e13至5×e14atom/cm-2。
步骤S7:在栅极两侧形成侧墙。侧墙可以通过淀积SiO2或Si3N4并且刻蚀形成侧墙,也可以采用先Si3N4再SiO2的双侧墙。如图1(g)所示,本实施例采用淀积二氧化硅并且干法刻蚀的方法,在栅极4的侧面形成自对准隔离结构7(即侧墙7),侧墙7下方的区域为扩展源漏区6,而扩展源漏区6与浅沟槽隔离区2之间的区域为深源漏区8。
步骤S8:对深源漏区进行第三离子注入工艺并对整个锗基衬底快速热处理退火。如图1(h)所示,通过离子注入杂质磷形成NMOS源漏N型重掺杂区域(深源漏区)8。注入磷杂质的剂量为5e14至1e16atom/cm-2。随后对整个锗基衬底1进行注入杂质的激活热处理,采用尖峰退火,有利于形成浅结,并使得注入的杂质硅,和两次注入的杂质磷激活,退火条件为300℃至800℃。
步骤S9:在源漏区上形成接触孔和金属连线。在此工艺步骤中首先可以选择采用硅化物源漏工艺来降低寄生电阻,然后淀积介质层9用于金属连线层10和器件层之间的隔离并光刻形成接触孔。再溅射金属层,比如Al、Al-Ti等,并光刻定义出连线图形,经过刻蚀后,既形成金属连线图形,最后通过低温退火过程合金,形成金属连线层10。最后形成本发明所提供的半导体器件如图1(i)所示。
利用本实施例提出的半导体器件的制造方法,可以制造出一种新的性能更好的锗基应变NMOS晶体管。通过杂质硅的注入,可以由源漏扩展区晶格失配有效地在锗沟道中引入合适应力,增强沟道中电子的迁移率,提高器件性能。另外,杂质硅可以阻碍杂质磷在锗衬底中的扩散,还可以一定程度上提高磷在锗中的固溶度,有利于形成浅结。同时,本方法几乎没有增加工艺的复杂性。因此相对于现有工艺制备方法,所述半导体器件及其制造方法简单有效地提升了锗基NMOS晶体管的性能。
以上所述,仅是本发明的较佳实施例而已,并非对本发明作任何形式上的限制。此外,所述半导体器件及其制造方法也可以用于PMOS晶体管,在此不再赘述。
虽然本发明已以较佳实施例披露如上,然而并非用以限定本发明。任何熟悉本领域的技术人员,在不脱离本发明技术方案范围情况下,都可利用上述揭示的方法和技术内容对本发明技术方案作出许多可能的变动和修饰,或修改为等同变化的等效实施例。因此,凡是未脱离本发明技术方案的内容,依据本发明的技术实质对以上实施例所做的任何简单修改、等同变化及修饰,均仍属于本发明技术方案保护的范围内。
Claims (10)
1.一种半导体器件的制造方法,其特征在于,包括:
提供锗基半导体衬底,所述锗基半导体衬底具有多个有源区以及多个有源区之间的器件隔离区,所述有源区上具有栅极介质层和栅极介质层之上的栅极,所述有源区包括源漏扩展区和深源漏区;
对所述源漏扩展区进行第一离子注入工艺,所述第一离子注入工艺中的注入离子包括硅或碳;
对所述源漏扩展区进行第二离子注入工艺;
对所述深源漏区进行第三离子注入工艺;
对经过第三离子注入工艺之后的锗基半导体衬底进行退火工艺。
2.根据权利要求1所述的半导体器件的制造方法,其特征在于,所述锗基半导体衬底为P型,所述第二离子注入工艺和/或第三离子注入工艺中注入N型杂质。
3.根据权利要求2所述的半导体器件的制造方法,其特征在于,所述锗基半导体衬底包括体锗衬底、锗覆绝缘衬底或硅基外延锗衬底。
4.根据权利要求2所述的半导体器件的制造方法,其特征在于,所述N型杂质包括P、As和Sb中的一种或多种。
5.根据权利要求1所述的半导体器件的制造方法,其特征在于,所述退火工艺包括快速热处理退火、激光退火或闪光退火。
6.根据权利要求1所述的半导体器件的制造方法,其特征在于,所述第一离子注入工艺的掺杂剂量为1×e13至1×e16atom/cm2。
7.根据权利要求1或2所述的半导体器件的制造方法,其特征在于,所述第三离子注入工艺的掺杂剂量为5×e14至1×e16atom/cm2。
8.根据权利要求1所述的半导体器件的制造方法,其特征在于,源漏扩展区进行硅或碳注入后在锗沟道中引入平行于沟道方向的单轴张应力和垂直于沟道平面压应力。
9.根据权利要求1所述的半导体器件的制造方法,其特征在于,对经过第三离子注入工艺之后的锗基半导体衬底进行退火工艺的步骤前还包括:在所述栅极两侧形成侧墙。
10.一种半导体器件,包括:
锗基半导体衬底,
所述锗基半导体衬底中的多个有源区以及多个有源区之间的器件隔离区,
所述有源区上的栅极介质层和栅极介质层之上的栅极,所述有源区包括源漏扩展区和深源漏区;
其特征在于,所述源漏扩展区内具有硅或碳杂质;
所述硅或碳杂质通过对所述源漏扩展区进行第一离子注入工艺而掺杂。
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CN110783406B (zh) * | 2018-07-25 | 2023-09-08 | 黄智方 | 具有第iva族离子注入的mosfet的结构与制造方法 |
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