TWI722502B - 具有第ｉｖａ族離子佈植的金氧半場效電晶體之結構與製造方法 - Google Patents

具有第ｉｖａ族離子佈植的金氧半場效電晶體之結構與製造方法 Download PDF

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TWI722502B
TWI722502B TW108126171A TW108126171A TWI722502B TW I722502 B TWI722502 B TW I722502B TW 108126171 A TW108126171 A TW 108126171A TW 108126171 A TW108126171 A TW 108126171A TW I722502 B TWI722502 B TW I722502B
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layer
source
base
electrode
drain
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TW202013458A (zh
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黃智方
江政毅
王勝弘
洪嘉慶
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國立清華大學
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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本發明揭露一種具有第IVA族離子佈植的金氧半場效電晶體之結構與方法，第IVA族離子佈植層設置於基極之中，且第IVA族離子佈植層接近於該閘極氧化層與該基極之交界面；其中，第IVA族離子佈植層用來改變結構之一通道的性質。

Description

具有第IVA族離子佈植的金氧半場效電晶體之結構與 製造方法
本發明係關於一種具有第IVA族離子佈植的金氧半場效電晶體之結構與製造方法，尤指一種閘極氧化層進行氧化前利用第IVA族離子佈值改善4H-SiC氧化的結構與製造方法。
在先前技術中，碳化矽金氧半場效電晶體的場效電子遷移率過低(5~10cm2/V．s)一直是碳化矽元件最大的缺點，近年來已經發展出使用氧化後一氧化氮熱退火可以讓電子遷移率有效提升至約30cm2/V．s。
澳洲格里菲斯大學的Hui-feng Li於1997年提出在6H-SiC金氧半電容(MOSC)在氧化製程後經過一氧化氮(NO)與氧化亞氮(N2O)環境下的快速加熱製程(Rapid thermal process,RTP)，實驗發現經過NO RTP步驟的MOSC量測到的介面缺陷密度(Interface trap density,Dit)比一般製程量測到的結果還低。
2001年，奧本大學G.Y.Chung.et.al把這個技術利用在4H-SiC水平型MOSFET，氧化後經過1175℃,1atm,2hr,NO熱退火，成功將通道電子遷移率從5cm2/V．s提高到37cm2/V．s。原因是其中氮原子會進入SiC/SiO2介面與Si形成鍵結，移除Si與C鍵結，C與C之間的鍵結也變少。
2010年，奈良先端科學技術大學院大學Dai Okamoto發表新的熱退火技術，改由三氯氧磷(POCl3)、氮氣(N2)與氧氣(O2)的混合氣體，在1000℃環境下持續10min，這項研究成功將通道電子遷移率提升至89cm2/V．s，不過也連帶造成副作用就是閾值電壓(VTH)急遽變小。
本發明提出第IVA族離子佈植的金氧半場效電晶體之結構與製造方法來改善閘極氧化層品質，提升場效電子遷移率。
本發明不同於習知技術提升電子遷移率，而是閘極電極氧化前，先在基極表面佈值第IVA族離子，藉由改變基極表面結構而影響閘極氧化現象，減少缺陷密度增加通道電子遷移率。
本發明提出第IVA族離子佈植的金氧半場效電晶體之結構與製造方法，用以改變閾值電壓(Threshold Voltage，VTH)。
本發明一實施例揭露一種具有第IVA族離子佈植的金氧半場效電晶體之結構，包含：一基極(Base)；一閘極電極，該閘極電極與該基極之間具有一閘極氧化層；以及一第IVA族離子佈植層，設置於該基極之中，且該第IVA族離子佈植層接近於該閘極氧化層與該基極之交界面；其中，該第IVA族離子佈植層用來改變該結構之一通道(Channel)的性質。
一種具有第IVA族離子佈植的金氧半場效電晶體之結構的製造方法，包含：一基極佈植步驟：將一鋁離子佈植於一基極中；一源極層或一汲極層之離子佈植步驟：利用一黃光製程定義出該源極層或該汲極層之區域，將一磷離子佈植於該源極層或該汲極層中；將一第IVA族離子佈植於距離該源極層、或該汲極層、或該基極之表面的一預設深度，以形成一第IVA族離子佈植層於接近該源極層、或該汲極層、或該基極之表面。
100、200、300:結構
101、201、301:基極
102、202、302:閘極電極
103、203、303:第IVA族離子佈植層
104、204、304:閘極氧化層
105、205、305:源極層
106、206、306:源極電極
107:汲極層
108、207、307:汲極電極
208、308:漂移層
209、309:基板
圖1~3顯示本發明一實施例示意圖。
圖4為Si離子佈值濃度對深度圖。
圖5a~圖5d為實驗流程圖。
圖6a、6b為量測直徑為200μm的電容得到的CV圖形。
圖6c、6d為Hi-Lo CV量測圖。
圖6c、6d為Hi-Lo CV量測圖。
圖6e為Hi-Lo換算之Dit位置分佈圖。
圖6f為電流密度-電場(Jg-εox)圖。
圖6g為習知技術標準製程SEM量測觀察實際氧化層厚度；圖6h為本發明之矽離子佈植製程SEM量測觀察實際氧化層厚度。
圖7a到圖7d為元件的IdVg與IdVd量測結果。
圖8a、圖8b為變溫IdVg。
請參考圖1，圖1顯示本發明一實施例具有第IVA族離子佈植的金氧半場效電晶體之結構之示意圖，結構100包含：基極101；閘極電極102；第IVA族離子佈植層103；閘極氧化層104；源極層105；源極電極106；汲極層107；以及汲極電極108。
閘極電極102與基極101之間具有閘極氧化層104，且第IVA族離子佈植層103設置於基極101之中，第IVA族離子佈植層103接近於閘極氧化層104與基極101之交界面，如虛線所示；其中，第IVA族離子佈植層103用來改變本結構100通道性質，一實施例中係增加結構100之通道的電子遷移率，且第IVA族離子佈植層103不設置於閘極氧化層104中。
在一實施例中，第IVA族離子可由碳(C)、矽 (Si)、鍺(Ge)、錫(Sn)、鉛(Pb)、鈇(Fl)之離子所實現。
源極層105設置於基極101之上表面；源極電極106設置於源極層105之上表面，並接觸閘極氧化層104之一側壁，且源極電極106覆蓋部分源極層105。汲極層107設置於基極101之上表面；汲極電極108設置於汲極層107之上表面，並接觸閘極氧化層104之另一側壁，且汲極電極108覆蓋部分汲極層107。
閘極氧化層104覆蓋部分源極層105、部分汲極層107以及部分基極101；源極層105與汲極層107為一第一型半導體材料，而基極101為一第二型半導體材料。
請注意，當結構100為NMOS電晶體時第一型半導體材料為N型半導體材料，第二型半導體材料為P型半導體材料；當結構100為PMOS電晶體時第一型半導體材料為P型半導體材料，第二型半導體材料為N型半導體材料。
在一實施例中，第IVA族離子佈植層103設置於源極層105與汲極層107之中，且第IVA族離子佈植層103接近於源極層105與源極電極106之交界面、以及源極層105與閘極氧化層104之交界面、汲極層107與汲極電極108之交界面、以及汲極層107與閘極氧化層104之交界面。
本結構100由改變基極101表面結構而影響氧化現象，當閘極氧化層104進行氧化反應時，以佈植進去之第IVA族離子作為反應物，因不具備一氧化氮(NO)，故減少對 基極101的碳化矽(以下簡稱SiC)鍵結破壞，以達到減少缺陷密度並增加通道電子遷移率。在本實施例中，第IVA族離子由矽離子所實現。
請參考圖2，圖2顯示本發明一實施例具有第IVA族離子佈植的金氧半場效電晶體之結構之示意圖，且結構200是垂直雙重擴散金氧半場效電晶體(Vertical DMOS)。
結構200包含：基極201、閘極電極202、第IVA族離子佈植層203、閘極氧化層204、源極層205、源極電極206、汲極電極207、漂移層(Drift layer)208、以及基板(Substrate)209。
請注意，閘極電極202與基極201之間具有閘極氧化層204，且第IVA族離子佈植層203設置於基極201之中，第IVA族離子佈植層203接近於閘極氧化層204與基極201之交界面，如虛線所示。
源極層205設置於基極201之上表面，且部分源極層205被基極201包覆；源極電極206設置於源極層205之上表面，並接觸該閘極氧化層204之一側壁，且源極電極206覆蓋部分源極層205之上表面；閘極氧化層204覆蓋部分基極201之上表面與源極層205之上表面。
漂移層208設置並接觸於閘極氧化層204之下表面並包覆該基極201；基板209接觸並設置於漂移層208之下；以及汲極電極207設置於基板209之下。
其中，閘極氧化層204也覆蓋部分源極層205、部分基極201以及部分漂移層208；源極層205、漂移層208以及基板209為一第一型半導體材料；基極201為一第二型半導體材料；在本實施例中，第一型半導體材料為N型半導體材料，第二型半導體材料為P型半導體材料。
第IVA族離子佈植層203設置於源極層205與漂移層208之中，且第IVA族離子佈植層203接近於源極層205與源極電極206之交界面、源極層205與閘極氧化層204之交界面、以及漂移層208與閘極氧化層204之交界面。
在一實施例中，第IVA族離子可由碳(C)、矽(Si)、鍺(Ge)、錫(Sn)、鉛(Pb)、鈇(Fl)之離子所實現。
請參考圖3，圖3顯示本發明一實施例具有第IVA族離子佈植的金氧半場效電晶體之結構之示意圖，且結構300是垂直溝槽式金氧半場效電晶體(Vertical UMOS)。
結構300包含：基極301、閘極電極302、第IVA族離子佈植層303、閘極氧化層304、源極層305、漂移層308、以及基板309；又，結構300具有金屬層分別設置於結構300之一上表面與一底面，以形成源極電極306與汲極電極307。
基板309設置於汲極電極307上；漂移層308設置於基板309之上；基極301設置於漂移層308之上；源極層305設置於基極301之上；溝槽T延伸通過基極301與源極層305，且溝槽T之底部終止於漂移層308，且閘極氧化層304 設置於溝槽T內，閘極電極302被閘極氧化層304所包覆。
其中，閘極氧化層304覆蓋部分源極層305、部分基極301以及部分漂移層308；源極層305、漂移層308以及基板309為一第一型半導體材料；基極301為一第二型半導體材料；以及第IVA族離子佈植層303設置於源極層305與漂移層308之中，且第IVA族離子佈植層303接近於基極301與源極電極306之交界面、源極層305與源極電極306之交界面、源極層305與閘極氧化層304之交界面、基極301與閘極氧化層304之交界面、以及漂移層308與閘極氧化層304之交界面。
接著針對本發明結構之製造方法進行說明(以下說明均以Si離子佈植為實施例)，本發明之金氧半場效電晶體(MOSFET)元件採用4H-SiC碳化矽基板，濃度為1×1020cm-3並在其上成長一層P-type磊晶層(epi layer)，濃度與厚度分別為6×1015cm-3和5μm，如圖5a。由於SiC材料不利擴散，所以本發明的源極、汲極、基極需使用離子佈值技術，以熱氧化技術成長閘極氧化層，最後以熱蒸鍍方式鍍上電極以完成元件。
本發明目的是為了改變SiC表面結構，藉此觀察是否造成SiC氧化差異，因為不再經過佈值後退火處理，故Si離子佈值必須採低能量佈值，避免造成表面粗糙(Surface roughening)而影響元件特性。且佈值進去的Si離子只留在表 層。經過Silvaco模擬決定參數如表1，模擬深度約60nm，如圖4為Si離子佈值濃度對深度圖。
Figure 108126171-A0305-02-0011-1
本發明採用N-type 4H-SiC基板，在其上成長P-type磊晶層，濃度與厚度分別為6×1015cm-3和5μm。表2為本次實驗所使用之光罩順序，圖5a~圖5d為實驗流程圖。
Figure 108126171-A0305-02-0011-2
製程前須先經過一道基本清潔，目的是為了清洗表面金屬離子及有機物。一般清潔第一步，浸泡硫酸 (H2SO4)100ml與雙氧水(H2O2)100ml催化之溶液10分鐘，此步驟可以清洗表面金屬微粒及有機物。第二步，浸泡氧化層蝕刻液(BOE)10分鐘，此步驟可以去除原生氧化層(Native Oxide)。每一步驟之後都需經過3至5分鐘的去離子水(DI water)沖洗避免殘留，再經過氮氣槍吹乾，如圖5a所示。
進行定義對準鍵及黃光製程(Alignment key& Lithography)。黃光製程步驟一，旋塗光阻，先用LOR光阻，旋轉參數3000轉45秒，經過170℃、5分鐘的軟烤，接著使用S1813光阻，旋轉參數為5000轉30秒，經過90℃、3分鐘軟烤，即完成旋塗光阻。
步驟二，曝光機進行對準，試片放上曝光機進行黃光對準，對準完成後進行曝光顯影，其參數分別為曝光19秒顯影24秒，利用顯微鏡確認圖形無誤後再進行120℃ 5分鐘的硬烤以完成黃光製程。
使用Mask#1進行黃光製程，完成後保留其上殘餘光阻，利用反應式離子蝕刻(RIE)，蝕刻定義出表面的SiC完成對準鍵，光阻可保護其他地方不被RIE蝕刻破壞，結束後清洗光阻。
清洗光阻步驟如下；浸泡丙酮(ACE)10分鐘、異丙醇(IPA)10分鐘、PG remover溶液隔水加熱至90℃後將試片浸泡10分鐘。
基極區離子佈植(Base Implantation)：先在試片上 進行一次電漿化學氣象沉積(PECVD)沉積一層厚度約1μm的二氧化矽，可以當作非定義區的離子佈植阻擋層，使用Mask#2進行黃光製程定義出基極區，RIE蝕刻基極區上的二氧化矽，蝕刻結束後去除表面光阻，處理完畢之後再進行離子佈植。佈植方式為高溫(650℃)鋁(Al)離子佈植，能量與劑量如表3所示。佈植結束後用BOE溶液去除試片上的二氧化矽。
Figure 108126171-A0305-02-0013-3
源極與汲極區離子佈植(Source Drain Implantation)：在試片上進行一次電漿化學氣象沉積(PECVD)沉積一層厚度約1μm的二氧化矽，使用Mask#3進行黃光製程定義出源極與汲極區，RIE蝕刻其上的二氧化矽，蝕刻去除表面光阻，處理完畢之後再進行離子佈植。佈植方式為高溫(650℃)磷(P)離子佈植，能量劑量如表4所示。佈植結束後用BOE溶液去除試片上的二氧化矽，基極、源極、汲極離子佈植完成之剖面圖如圖5b所示。
Figure 108126171-A0305-02-0013-4
電性活化是利用超高溫(1650℃)氬氣環境下持續30分鐘，不過在如此高溫環境下SiC表面會形成熔融態導致揮發，所以在進行電性活化前需要在試片上覆蓋一層碳膜(Graphite Cap)避免揮發。試片上旋塗光阻S1813，旋塗完畢直接硬烤120℃、5分鐘，放進爐管800℃氬氣環境下30分鐘形成碳膜。活化完成後進爐管900℃氧氣環境下30分鐘讓表面碳膜進行氧化反應產生CO或CO2，藉此去除表面碳膜。
採取整面高溫(650℃)矽離子佈植，實驗設計關係需把佈植深度控制在表面附近所以先用Silvaco模擬，最後決定之能量劑量如表1所示，模擬結果如圖4，離子佈值深度落在60nm附近，如圖5c所示。
為避免佈植之後造成元件與元件之間的漏電，設計一道寬度為5μm的元件隔離區，並使用蝕刻方式製作。使用Mask#4進行黃光製程定義出隔離區，利用RIE蝕刻SiC深度大約148nm，結束後去除光阻。
閘極氧化(Gate Oxidation)：進行氧化前試片先經過RCA清潔法(RCA clean)，此步驟可以讓試片表面所有雜質、有機物、金屬離子去除，讓試片維持最純淨的狀態下氧化。RCA clean流程如下所示：
浸泡硫酸(H2SO4)與雙氧水(H2O2)的混合溶液10分鐘。
浸泡BOE溶液5分鐘。
浸泡氨水(NH4OH)溶液10分鐘，此步驟需隔水加熱直到溶液溫度達90℃。
浸泡BOE溶液1分鐘。
浸泡鹽酸(HCL)溶液10分鐘，此步驟需隔水加熱直到溶液溫度達90℃。
浸泡BOE溶液1分鐘。
氧化參數為乾氧1150℃、6小時，如圖5d所示
源極、汲極歐姆接觸(Source,Drain Contact)：使用Mask#5進行黃光製程定義源極與汲極區，RIE蝕刻其上的氧化層，選擇RIE蝕刻好處是RIE為非等向蝕刻，可避免側蝕影響通道長度。以熱蒸鍍方式蒸鍍歐姆接觸金屬鈦(Ti)、鎳(Ni)，鈦金屬為了增加金屬黏著度而鎳金屬除了提供歐姆接點外還可以防止在之後的高溫熱退火時金屬與空氣中的氧氣產生反應。金屬厚度分別為200Å/1000Å。之後再用舉離(Lift-off)方式去除其他金屬。
基極歐姆接觸(Base Contact)：使用Mask#6進行黃光製程定義出基極接觸區再用RIE蝕刻其上氧化層。P型半導體歐姆接觸困難度比較高，所使用的金屬為鈦、鋁、鎳，其中鋁可以增加歐姆接點，金屬分別為200Å/1200Å/1000Å。之後再用舉離方式去除其他金屬。
快速熱退火(RTA)：金屬需經過高溫熱退火才有較好的歐姆接觸特性，快速熱退火參數為1000℃、3分鐘， 需在真空環境下進行，避免金屬與空氣反應而影響歐姆特性。
閘極金屬與墊金屬(Pad Metal)使用Mask#7進行黃光製程定義出區域，再以熱蒸鍍方式蒸鍍金屬鈦、鋁，厚度分別為200Å/3500Å，厚度增加是為了避免量測時探針戳穿金屬而影響量測結果。最後完成之水平MOSFET元件剖面圖。
垂直電容量測：MOSC中電壓-電容量測(Capacitance-Voltage,CV)中，利用高頻率(1M Hz)量測，可以從累積層電容(Cox)中換算出等效氧化層厚度(EOT)，換算公式如式1。
Figure 108126171-A0305-02-0016-5
其中
Figure 108126171-A0305-02-0016-6
為二氧化矽介電常數，A為面積。圖6a、6b為量測直徑為200μm的電容得到的CV圖形，換算出等效氧化層厚度分別為53nm跟50nm，其中圖6a為習知技術標準製程，圖6b為本發明之矽離子佈植製程；兩種製程對於氧化層厚度並沒有太多的差異，原因在於佈植能量極小所以表面晶格完整，對於提升氧化速率上並沒有太多幫助。
Hi-Lo CV量測如圖6c、6d，其中圖6c為習知技術標準製程，圖6d為本發明之矽離子佈植製程，高頻量測頻率為1MHz，Quasi-static CV量測步階電壓為0.1V/s，換算出Dit對能帶位置的圖形如圖6e，由圖可知距離導帶0.3eV以下， 經過矽離子佈植製程的試片之Dit明顯低於標準製程試片，證明經過矽離子佈植製程可以減少介面缺陷密度。氧化層耐壓量測，根據CV量測得到的等效氧化層厚度大約在50nm上下，我們將限電流設定在1μA進行耐壓量測，圖6f為兩種製程的電流密度-電場(Jg-εox)圖，最大電場到6MV/cm以上開始進入FN漏電，證明經過Si離子佈值之後的氧化層強度並沒有變差。最後利用SEM量測觀察實際氧化層厚度，結果如圖6g、圖6h，其中圖6g為習知技術標準製程，圖6h為本發明之矽離子佈植製程，則實際厚度分別為56nm與46nm。
順向電流量測：本實施例量測採用通道長度為5μm之元件，包括汲極電流對閘極電壓量測(IdVg)與汲極電流對汲極電壓量測(IdVd)。
量測汲極電流對閘極電壓時，需施加一個極小電壓在汲極端(Vd=0.1V)，使得汲極電流的公式可以簡化如式2，另外從IdVg圖形中Id對Vg微分後得到轉導增益(Transconductance,gm)，式3，並利用最大值(gm,MAX)時的切線方程式計算閾值電壓，藉由式4求得場效電子遷移率(Field-effect mobility,μFE)。
Figure 108126171-A0305-02-0017-7
Figure 108126171-A0305-02-0017-8
Figure 108126171-A0305-02-0017-9
表5為量測結果整理，標準製程試片平均場效電子遷移率6.38cm2/V．s，經過氧化前Si離子佈值的試片平均場 效電子遷移率提升至7.59cm2/V．s，大約有將近15%的增幅，且閾值電壓也沒有太多幅度的變動。原因在於Si經離子佈植之後沒有高溫活化，而以雜質方式存在於SiC表面，且低能量佈植並不會傷害到表面晶格完整度，進行氧化反應所需要的Si原子部分由佈植進去之雜質提供而減少破壞原本SiC鍵結，藉此減少氧化反應時產生的斷鍵降低Dit，且Si為中性摻雜也不會對閾值電壓造成太多變化。圖7a到圖7d為兩種製程條件下具代表性元件的IdVg與IdVd量測結果，其中圖7a與7c為習知技術標準製程，圖7b與7d為本發明之矽離子佈植製程。
Figure 108126171-A0305-02-0018-10
變溫電性量測：圖8a、圖8b為變溫IdVg，其中圖8a為習知技術標準製程，圖8b為本發明之矽離子佈植製程，隨著溫度提高，電流增加、電子遷移率上升且閾值電壓下降。因為SiC存在高密度的界面缺陷捕捉電子，溫度上升可以有效釋放被捕捉的電子，使得通道電子濃度提高更容易達到通道反轉，閾值電壓下降電子遷移率上升，值得注意的是，經過Si離子佈植之後的試片，閾值電壓下降幅度比基本製程試 片還慢，更容易避免元件提早進入常開模式。詳細變溫數據整理表6、表7。
Figure 108126171-A0305-02-0019-11
Figure 108126171-A0305-02-0019-12
本發明在氧化製程前以Si離子佈值改變表面特 性，改善氧化環境，提升SiC水平金氧半場效電晶體電子遷移率。
藉由氧化前Si離子佈值將場效電子遷移率由原本的6.38cm2/V．s提升至7.59cm2/V．s增幅約15%，平均介面缺陷密度也從4.079×1012eV-1cm-2下降到3.764×1012eV-1cm-2，雖然沒有NO熱退火所帶來這麼大的電子遷移率增幅，不過卻避免閾值電壓偏移的副作用，且不影響歐姆接觸等其他電性。
100:結構
101:基極
102:閘極電極
103:第IVA族離子佈植層
104:閘極氧化層
105:源極層
106:源極電極
107:汲極層
108:汲極電極

Claims (12)

  1. 一種具有第IVA族離子佈植的金氧半場效電晶體之結構，包含：一基極(Base)；一閘極電極(Gate Electrode)，該閘極電極與該基極之間具有一閘極氧化層；以及一第IVA族離子佈植層，設置於該基極之中，且該第IVA族離子佈植層接近於該閘極氧化層與該基極之交界面；其中，該第IVA族離子佈植層用來改變該結構之一通道(Channel)的性質；以及，該第IVA族離子佈植層被控制設置於一預設深度中。
  2. 如申請專利範圍第1項所述之結構，其中，該通道的性質包含一通道電子遷移率及一閾值電壓(Threshold Voltage，VTH)。
  3. 如申請專利範圍第2項所述之結構，其中，該第IVA族離子佈植層用來增加該基極之鍵結。
  4. 如申請專利範圍第3項所述之結構，其中，該第IVA族離子佈植層為一矽離子佈植層。
  5. 如申請專利範圍第4項所述之結構，其中，該矽離子佈植層不設置於該閘極氧化層。
  6. 如申請專利範圍第5項所述之結構，其中，該結構更包含：一源極層，設置於該基極之上表面；以及一源極電極，設置於該源極層之上表面； 其中，該矽離子佈植層接近於該源極層與該源極電極之交界面。
  7. 如申請專利範圍第6項所述之結構，其中，該源極電極接觸該閘極氧化層之一側壁，且該源極電極覆蓋部分該源極層；該結構更包含：一汲極層，設置於該基極之上表面；以及一汲極電極，設置於該汲極層之上表面，並接觸該閘極氧化層之另一側壁，且該汲極電極覆蓋部分該汲極層；其中，該閘極氧化層覆蓋部分該源極層、部分該汲極層以及部分該基極；該源極層與該汲極層為一第一型半導體材料；以及該基極為一第二型半導體材料；以及該矽離子佈植層設置於該源極層與該汲極層之中，且該矽離子佈植層接近於該源極層與該閘極氧化層之交界面、該汲極層與該汲極電極之交界面、以及該汲極層與該閘極氧化層之交界面。
  8. 如申請專利範圍第6項所述之結構，其中，部分該源極層被該基極包覆，該源極電極接觸該閘極氧化層之一側壁，且該源極電極覆蓋部分該源極層；該結構更包含：一漂移層(Drift layer)，設置並接觸於該閘極氧化層之下表面並包覆該基極；一基板，接觸並設置於該漂移層之下；以及一汲極電極，設置於該基板之下；其中，該閘極氧化層覆蓋部分該源極層、部分該基極以及部分該漂移層；該源極層、該漂移層以及該基板為一第一型半導體材料；該基極為一第二型半導體材料；以及該矽離子佈植層設置於該源極層與該漂移層之中，且該 矽離子佈植層接近於該源極層與該閘極氧化層之交界面、以及該漂移層與該閘極氧化層之交界面。
  9. 如申請專利範圍第6項所述之結構，其中，該結構更包含：一金屬層，分別設置於該結構之一上表面與一底面，以形成該源極電極與一汲極電極；一基板，設置於該汲極電極之上；一漂移層，設置於該基板之上；一基極，設置於該漂移層之上；以及一溝槽，延伸通過該基極與該源極層，且該溝槽之底部終止於該漂移層，且該閘極氧化層設置於該溝槽內，該閘極電極被該閘極氧化層所包覆；其中，該閘極氧化層覆蓋部分該源極層、部分該基極以及部分該漂移層；該源極層、該漂移層以及該基板為一第一型半導體材料；該基極為一第二型半導體材料；以及該矽離子佈植層設置於該源極層與該漂移層之中，且該矽離子佈植層接近於該基極與該源極電極之交界面、該源極層與該閘極氧化層之交界面、以及該漂移層與該閘極氧化層之交界面。
  10. 一種具有第IVA族離子佈植的金氧半場效電晶體之結構的製造方法，包含：一基極佈植步驟：將一鋁離子佈植於一基極中；一源極層或一汲極層之離子佈植步驟：利用一黃光製程定義出該源極層或該汲極層之區域，將一磷離子佈植於該源極層或該汲極層中；以及一第IVA族離子佈植之步驟：將一第IVA族離子佈植於距離該源極層、或該汲極層、或該基極之表面的一預設 深度，以形成一第IVA族離子佈植層於接近該源極層、或該汲極層、或該基極之表面。
  11. 如申請專利範圍第10項所述之方法，其中，該第IVA族離子為一矽離子，且該預設深度為100nm以內。
  12. 如申請專利範圍第11項所述之方法，其中，該第IVA族離子佈植之步驟在一閘極氧化層進行氧化前。
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