WO2012020689A1 - 半導体装置の製造方法および半導体装置 - Google Patents

半導体装置の製造方法および半導体装置 Download PDF

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WO2012020689A1
WO2012020689A1 PCT/JP2011/067847 JP2011067847W WO2012020689A1 WO 2012020689 A1 WO2012020689 A1 WO 2012020689A1 JP 2011067847 W JP2011067847 W JP 2011067847W WO 2012020689 A1 WO2012020689 A1 WO 2012020689A1
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film
semiconductor device
semiconductor substrate
substrate
manufacturing
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French (fr)
Japanese (ja)
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大見　忠弘
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Tohoku University NUC
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Tohoku University NUC
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Priority to CN2011800389423A priority Critical patent/CN103081077A/zh
Priority to US13/814,950 priority patent/US20130140700A1/en
Publication of WO2012020689A1 publication Critical patent/WO2012020689A1/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H10P14/6336—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/6903—Inorganic materials containing silicon
    • H10P14/6905—Inorganic materials containing silicon being a silicon carbide or silicon carbonitride and not containing oxygen, e.g. SiC or SiC:H
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H10P50/692—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their composition, e.g. multilayer masks or materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0245—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising use of blind vias during the manufacture
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0249—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias wherein the through-semiconductor via protrudes from backsides of the chips, wafers or substrates during the manufacture
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H10P14/6316—Formation by nitridation, e.g. nitridation of the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H10P14/6319—Formation by plasma treatments, e.g. plasma oxidation of the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/694—Inorganic materials composed of nitrides
    • H10P14/6943—Inorganic materials composed of nitrides containing silicon
    • H10P14/69433—Inorganic materials composed of nitrides containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/60—Wet etching
    • H10P50/64—Wet etching of semiconductor materials
    • H10P50/642—Chemical etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations

Definitions

  • the present invention relates to a method for manufacturing a semiconductor device having a TSV structure and a semiconductor device.
  • a TSV Through Silicon Via, silicon through electrode
  • a semiconductor device semiconductor chip or semiconductor wafer
  • a technique of forming a three-dimensional structure by providing a through electrode and connecting an end of the through electrode to an electrode of another semiconductor device is adopted.
  • a large number of holes are formed in a silicon substrate (wafer) on which a circuit is formed, and an electrode metal such as Cu or W as TSV is formed therein.
  • a pillar is formed, and then processing such as etching is performed from the back surface of the wafer, thereby thinning the wafer and causing the electrode metal column to protrude from the back surface (Patent Document 1).
  • the substrate can be thinned by the above-described processing, there is a problem in that the substrate is likely to warp.
  • the present invention has been made in view of the above problems, and a technical problem thereof is to provide a method of manufacturing a semiconductor device having a TSV structure that can prevent warping even if the substrate is thinned. is there.
  • a first aspect of the present invention includes a step (a) in which semiconductor elements are integrated on a surface of a semiconductor substrate to form all or part of a circuit, and a hole is formed from the surface of the semiconductor substrate.
  • a method of manufacturing a semiconductor device comprising: a step (e) of projecting a film from the back surface; and a step (f) of subsequently providing a SiCN film on the back surface of the semiconductor substrate.
  • a semiconductor substrate having a semiconductor element formed on the front surface, a through electrode provided so as to penetrate the semiconductor substrate and partially project from the back surface, and so as to cover the back surface And a provided SiCN film.
  • the present invention it is possible to provide a method of manufacturing a semiconductor device having a TSV structure that can prevent warping even if the substrate is thinned.
  • FIG. 1 is a cross-sectional view showing a semiconductor device 100.
  • FIG. 5 is a cross-sectional view showing a manufacturing process of the semiconductor device 100.
  • FIG. 5 is a cross-sectional view showing a manufacturing process of the semiconductor device 100.
  • FIG. 5 is a cross-sectional view showing a manufacturing process of the semiconductor device 100.
  • FIG. 5 is a cross-sectional view showing a manufacturing process of the semiconductor device 100.
  • FIG. 5 is a cross-sectional view showing a manufacturing process of the semiconductor device 100.
  • FIG. 5 is a cross-sectional view showing a manufacturing process of the semiconductor device 100.
  • FIG. 5 is a cross-sectional view showing a manufacturing process of the semiconductor device 100.
  • FIG. 3 is a diagram showing a relationship between a composition of a SiCN film 20 and physical properties (internal stress).
  • a semiconductor device 100 has a substrate 1 such as a silicon substrate, and a circuit 2 having an LSI structure such as DRAM or flash memory is integrated on the surface of the substrate 1 by integrating semiconductor elements (not shown). Is formed.
  • a substrate 1 such as a silicon substrate
  • a circuit 2 having an LSI structure such as DRAM or flash memory is integrated on the surface of the substrate 1 by integrating semiconductor elements (not shown). Is formed.
  • a through electrode 31 (TSV) is formed in the semiconductor device 100 so as to penetrate the substrate 1, and a part of the through electrode 31 is formed on the back surface of the substrate 1 (opposite the surface on which the circuit 2 is formed). Projecting from the surface).
  • the through electrode 31 has a columnar plug 13 made of a conductive metal such as Cu, and a barrier film 12 made of TaN or the like so as to cover the plug 13.
  • an insulating film 11 such as Si 3 N 4 is provided between the through electrode 31 and the substrate 1 so as to cover the through electrode 31 and in contact with the substrate 1.
  • a SiCN film 20 is formed on the back surface of the substrate 1 so as to cover the back surface.
  • the SiCN film 20 is a passivation film that is provided on the back surface of the substrate and does not cause the substrate 1 to warp.
  • a silicon oxide film or a silicon nitride film is used as the passivation film, but there is a problem that they cause warpage on a thin substrate.
  • the warpage of the wafer can be made substantially zero by controlling the amount of C during film formation.
  • a substrate 1 as shown in FIG. 2 is prepared.
  • a silicon substrate or the like is used as the substrate 1, and semiconductor elements (not shown) are integrated to form all or part of the circuit 2 on the surface.
  • a silicon substrate having a thickness of 775 ⁇ m was prepared as the substrate 1, and semiconductor elements were integrated on the surface thereof to form an LSI structure circuit 2 such as a DRAM or a flash memory.
  • a predetermined number of holes 10 are formed from the surface in the portion of the substrate 1 where the TSV structure (through electrode 31) is formed.
  • the diameter of the hole 10 is about 10 ⁇ m ⁇ 10 ⁇ m, and the depth is about 40 ⁇ m to 50 ⁇ m.
  • etching is performed by etching.
  • the hole etching is performed using a 2.45 GHz microwave excited RLSA plasma etcher or a 915 MHz microwave excited MSEP (Metal Surface Wave® Excitation Plasma) plasma etcher.
  • the etchers cover the inner wall surface of the chamber with an Al 2 O 3 film formed by non-aqueous anodic oxidation, they do not emit moisture at all. If all the organic solvent and moisture in the resist are removed in advance, the etching selectivity between the resist and Si will be 50-100. Therefore, the resist film thickness may be as thin as about 2 ⁇ m, and the resolution can be increased accordingly.
  • an insulating film 11 is formed on the inner surface of the hole 10.
  • a method for forming the insulating film 11 there is a method in which Si is directly nitrided and a silicon nitride film is formed thereon by CVD.
  • the direct nitridation is performed by using a MSEP plasma processing apparatus of a single-stage shower plate excited by 915 MHz microwave and flowing a mixed gas of Ar gas and NH 3 gas from the shower plate.
  • a Si 3 N 4 film is formed on the silicon nitride by CVD (Chemical Vapor Deposition).
  • This CVD uses a MSEP plasma processing apparatus of a two-stage shower plate excited by 915 MHz microwave, and a mixed gas of Ar gas and NH 3 gas is flowed from the upper shower plate, and a mixture of Ar gas and SiH 4 gas is flowed from the lower shower plate Run with gas flow.
  • a barrier film 12 is formed on the inner surface of the insulating film 11.
  • the MSEP plasma processing apparatus of a two-stage shower plate excited by 915 MHz microwaves is used as in the formation of the insulating film 11, and a mixed gas of Ar gas and NH 3 gas is flowed from the upper shower plate to lower shower.
  • a gas such as TaCl 3 was flowed from the plate to form a TaN film as a barrier film 12 on the Si 3 N 4 film by CVD.
  • the barrier film 12 is a conductive barrier film that prevents Cu deposited later from diffusing into the semiconductor substrate.
  • the plug 13 is formed so as to fill the hole 10 in the hole 10.
  • a current was passed through the TaN film (barrier film 12)
  • Cu was electroplated on the inner surface of the TaN film using the TaN film as a seed film
  • a Cu metal column TSV electrode
  • TSV electrodes through electrodes 31 are formed in the respective holes 10.
  • etching is performed from the back side of the substrate 1 to reduce the thickness of the substrate 1 to a predetermined thickness, and further, the TSV electrode (plug) covered with the TaN film 12 and the insulating film 11. 13) A part on the bottom side of the bottom surface is projected (exposed) from the back surface of the substrate 1.
  • Etching paste surface of the substrate 1 to the porous glass substrate 33 (manufactured by Tokyo Ohka Kogyo Co., Ltd.), very fast wet etching using HF / HNO 3 / CH 3 COOH / H 2 O solution, silicon 775 ⁇ m substrate
  • the back side of 1 was etched at a rate of 750 ⁇ m / min for about 1 minute.
  • the thickness of the substrate 1 becomes about 20 ⁇ m to 30 ⁇ m.
  • the Si 3 N 4 film (insulating film 11) is not etched, the substrate 1 can be thinned only by wet etching.
  • a Cu plug 13 covered with a TaN film (barrier film 12) and a Si 3 N 4 film (insulating film 11) is formed on the back side of the substrate 1 having a thickness of 20 ⁇ m to 30 ⁇ m. The bottom side of is protruding.
  • a SiCN film 20 is formed on the back surface of the substrate 1 by CVD.
  • the SiCN film 20 uses a MSEP plasma processing apparatus of a two-stage shower plate excited by 915 MHz microwave, and a mixed gas of Ar gas and NH 3 gas is flowed from the upper shower plate, and Ar gas is flown from the lower shower plate. , SiH 4 gas and SiH (CH 3 ) 3 gas are flowed to form a film at a temperature of about 100 ° C. As a result, the warpage of the wafer (substrate 1) can be completely controlled.
  • the internal stress changes from positive to negative by setting the C amount to around 10 atomic%, and therefore, it is possible to find a condition for making the wafer warpage zero by controlling the C amount.
  • the internal stress of the SiCN film 20 is adjusted, for example, by adjusting the concentration of SiH (CH 3 ) 3 gas (that is, the C content in the film) as shown by the white arrow in FIG. It can be substantially zero).
  • SiCN silicon nitride Si 3 N 4 contains (adds) a little less than 10% of C, but it may be a composition with C added at 2 to 40 atomic%.
  • SiCN is characterized by not only excellent properties as a passivation film but also excellent thermal conductivity.
  • the thermal conductivity of SiO 2 is 1.4 W / m / Kelvin, while SiCN is overwhelmingly large at 70 W / m / Kelvin.
  • the surface of the protrusion of the Cu plug 13 covered with the TaN film (barrier film 12) and the Si 3 N 4 film (insulating film 11) is also formed on the SiCN.
  • a film 20 is formed.
  • the wafer (substrate 1) is peeled off from the glass substrate 33. Since the glass substrate 33 is etched little by little with a wet etching HF / HNO 3 / CH 3 COOH / H 2 O solution as it is, the exposed surface is coated with Y 2 O 3 added with CeO 2. Then, it is covered with a protective film (not shown) baked at about 700 ° C. to prevent etching.
  • a resist is applied to the surface of the SiCN film 20 (portion formed on the back surface of the silicon substrate) on the back surface side of the substrate 1.
  • the SiCN film 20 and the Si 3 N 4 film (insulating film 11) covering the surface (the surface of the barrier film 12 protruding from the back surface of the substrate 1) are removed by etching.
  • the semiconductor device 100 shown in FIG. 1 is completed.
  • the semiconductor device 100 forms the hole 10 in the substrate 1, forms the insulating film 11, the barrier film 12, and the plug 13 in the hole 10, and etches the back surface of the substrate 1.
  • the SiCN film 20 is formed on the back surface of the substrate 1.
  • the present invention is applied to the semiconductor device 100 using the silicon substrate on which the DRAM or the flash memory is formed is described.
  • the present invention is not limited to this, It can be applied to the TSV structure.
  • Substrate 2 Circuit (LSI structure) 10 hole 11 insulating film 12 barrier film (TaN film) 13 Plug (conductive metal) 20 SiCN film 31 Through electrode 33 Glass substrate 100 Semiconductor device

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
PCT/JP2011/067847 2010-08-10 2011-08-04 半導体装置の製造方法および半導体装置 Ceased WO2012020689A1 (ja)

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Application Number Priority Date Filing Date Title
CN2011800389423A CN103081077A (zh) 2010-08-10 2011-08-04 半导体装置的制造方法及半导体装置
US13/814,950 US20130140700A1 (en) 2010-08-10 2011-08-04 Method of manufacturing a semiconductor device and semiconductor device

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JP2010179468A JP5419167B2 (ja) 2010-08-10 2010-08-10 半導体装置の製造方法および半導体装置
JP2010-179468 2010-08-10

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103426864A (zh) * 2013-08-26 2013-12-04 华进半导体封装先导技术研发中心有限公司 适用于转接板的tsv结构及其制备方法
US20140008810A1 (en) * 2012-07-05 2014-01-09 Globalfoundries Singapore Pte. Ltd. Method for forming through silicon via with wafer backside protection

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2921677B2 (ja) 1997-07-28 1999-07-19 矢崎総業株式会社 カード式電気錠装置
US8963336B2 (en) 2012-08-03 2015-02-24 Samsung Electronics Co., Ltd. Semiconductor packages, methods of manufacturing the same, and semiconductor package structures including the same
US9034752B2 (en) * 2013-01-03 2015-05-19 Micron Technology, Inc. Methods of exposing conductive vias of semiconductor devices and associated structures
CN105990166B (zh) * 2015-02-27 2018-12-21 中芯国际集成电路制造(上海)有限公司 晶圆键合方法
TWI587458B (zh) * 2015-03-17 2017-06-11 矽品精密工業股份有限公司 電子封裝件及其製法與基板結構
CN105428311A (zh) * 2015-12-16 2016-03-23 华进半导体封装先导技术研发中心有限公司 Tsv背部露头的工艺方法
TWI605557B (zh) * 2015-12-31 2017-11-11 矽品精密工業股份有限公司 電子封裝件及其製法與基板結構
CN107305840B (zh) * 2016-04-25 2020-05-12 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法和电子装置
US10396012B2 (en) 2016-05-27 2019-08-27 International Business Machines Corporation Advanced through substrate via metallization in three dimensional semiconductor integration
US10312181B2 (en) 2016-05-27 2019-06-04 International Business Machines Corporation Advanced through substrate via metallization in three dimensional semiconductor integration
US9786605B1 (en) * 2016-05-27 2017-10-10 International Business Machines Corporation Advanced through substrate via metallization in three dimensional semiconductor integration
US9997452B1 (en) 2017-01-27 2018-06-12 Micron Technology, Inc. Forming conductive plugs for memory device
CN108735744B (zh) * 2017-04-21 2021-02-02 联华电子股份有限公司 半导体存储装置以及其制作方法
CN109994422B (zh) * 2017-12-29 2021-10-19 江苏长电科技股份有限公司 Tsv封装结构及其制备方法
KR102757381B1 (ko) * 2020-10-13 2025-01-20 삼성전자주식회사 반도체 장치 제조 방법
CN115588619B (zh) * 2021-07-05 2025-07-18 长鑫存储技术有限公司 微凸块及其形成方法、芯片互连结构及方法
US20230352369A1 (en) * 2022-04-28 2023-11-02 Invensas Bonding Technologies, Inc. Through-substrate vias with metal plane layers and methods of manufacturing the same

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004158832A (ja) * 2002-10-17 2004-06-03 Renesas Technology Corp 半導体装置およびその製造方法
JP2004296515A (ja) * 2003-03-25 2004-10-21 Renesas Technology Corp 半導体装置およびその製造方法
JP2005310817A (ja) * 2004-04-16 2005-11-04 Seiko Epson Corp 半導体装置の製造方法、回路基板、並びに電子機器
JP2006269580A (ja) * 2005-03-23 2006-10-05 Matsushita Electric Ind Co Ltd 半導体装置とその製造方法
JP2008053639A (ja) * 2006-08-28 2008-03-06 Tohoku Univ 半導体装置および多層配線基板

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4500961B2 (ja) * 2004-06-07 2010-07-14 国立大学法人九州工業大学 薄膜形成方法
WO2006059589A1 (ja) * 2004-11-30 2006-06-08 Kyushu Institute Of Technology パッケージングされた積層型半導体装置及びその製造方法
KR20100021856A (ko) * 2008-08-18 2010-02-26 삼성전자주식회사 관통 전극을 갖는 반도체장치의 형성방법 및 관련된 장치
US8501587B2 (en) * 2009-01-13 2013-08-06 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked integrated chips and methods of fabrication thereof
KR20120048590A (ko) * 2009-07-31 2012-05-15 고쿠리츠 다이가쿠 호진 도호쿠 다이가쿠 반도체 장치, 반도체 장치의 제조 방법, 및 표시 장치

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004158832A (ja) * 2002-10-17 2004-06-03 Renesas Technology Corp 半導体装置およびその製造方法
JP2004296515A (ja) * 2003-03-25 2004-10-21 Renesas Technology Corp 半導体装置およびその製造方法
JP2005310817A (ja) * 2004-04-16 2005-11-04 Seiko Epson Corp 半導体装置の製造方法、回路基板、並びに電子機器
JP2006269580A (ja) * 2005-03-23 2006-10-05 Matsushita Electric Ind Co Ltd 半導体装置とその製造方法
JP2008053639A (ja) * 2006-08-28 2008-03-06 Tohoku Univ 半導体装置および多層配線基板

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140008810A1 (en) * 2012-07-05 2014-01-09 Globalfoundries Singapore Pte. Ltd. Method for forming through silicon via with wafer backside protection
US8940637B2 (en) * 2012-07-05 2015-01-27 Globalfoundries Singapore Pte. Ltd. Method for forming through silicon via with wafer backside protection
US9230886B2 (en) 2012-07-05 2016-01-05 Globalfoundries Singapore Pte. Ltd. Method for forming through silicon via with wafer backside protection
CN103426864A (zh) * 2013-08-26 2013-12-04 华进半导体封装先导技术研发中心有限公司 适用于转接板的tsv结构及其制备方法

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