CN110034017A - 用于使金属和阻挡层-衬垫可控凹陷的方法 - Google Patents

用于使金属和阻挡层-衬垫可控凹陷的方法 Download PDF

Info

Publication number
CN110034017A
CN110034017A CN201811489710.XA CN201811489710A CN110034017A CN 110034017 A CN110034017 A CN 110034017A CN 201811489710 A CN201811489710 A CN 201811489710A CN 110034017 A CN110034017 A CN 110034017A
Authority
CN
China
Prior art keywords
barrier layer
feature
dielectric substance
dielectric
metal layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201811489710.XA
Other languages
English (en)
Inventor
任河
阿米里塔·B·穆利克
瑞加娜·弗雷德
梅裕尔·奈克
乌代·米特拉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micromaterials LLC
Original Assignee
Micromaterials LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micromaterials LLC filed Critical Micromaterials LLC
Publication of CN110034017A publication Critical patent/CN110034017A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02142—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides
    • H01L21/02145—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides the material containing aluminium, e.g. AlSiOx
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76832—Multiple layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76865—Selective removal of parts of the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76883—Post-treatment or after-treatment of the conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01044—Ruthenium [Ru]

Abstract

描述了将金属层和含金属的阻挡层蚀刻到预定深度的方法。在一些实施方案中，将所述金属层和所述含金属的阻挡层形成在基板上，所述基板具有第一电介质和形成在所述第一电介质上的第二电介质。将所述金属层和所述含金属的阻挡层形成在所述第一电介质和所述第二电介质中的特征内。在一些实施方案中，可以从电介质材料中形成的特征顺序地蚀刻所述金属层和所述含金属的阻挡层。在一些实施方案中，将在电介质材料中形成的特征的侧壁钝化以改变电介质材料的附着性质。

Description

用于使金属和阻挡层-衬垫可控凹陷的方法
技术领域
本公开一般涉及用于使金属和阻挡层/衬垫材料凹陷的方法。具体地，本公开涉及作为图案化过程的一部分，可控地使金属和阻挡层/衬垫材料凹陷的方法。
背景技术
通常在电介质层与金属层之间使用基于金属的衬垫或阻挡层。这些衬垫往往在用于产生自对准通孔的沉积-蚀刻方案中使用。在使用中，往往蚀刻或凹陷金属层以去除至少一些金属层。然而，衬垫通常不受蚀刻工艺的影响，或者在金属层凹陷之后暴露在侧壁表面上。
在一些工艺中，衬垫仅被部分地蚀刻，留下衬垫材料在侧壁上。较长的蚀刻时间可以减少留在侧壁上的材料量。然而，较长的蚀刻时间可能在不同宽度的特征上产生不同的蚀刻结果。例如，较宽的特征倾向于比较窄的特征被蚀刻更多。由于特征的尺寸可能由于许多因素(包括工艺不规则性)而变化，因此不同的蚀刻深度可能导致额外的不均匀性。另外，许多用于去除阻挡层的蚀刻工艺可能损伤金属或电介质层。
因此，在本领域存在改进使金属层和基于金属的衬垫凹陷的方法的需要。
发明内容
本公开的一个或多个实施方案涉及处理方法，所述处理方法包括提供基板，所述基板具有第一电介质材料和形成在第一电介质材料上的第二电介质材料。所述第二电介质材料具有某一厚度。基板包括在第一电介质材料和第二电介质材料中形成的至少一个特征。所述至少一个特征具有至少一个侧壁和底部。所述特征的深度被限定为从第二电介质材料的顶表面到特征的底部。在所述至少一个侧壁和所述底部上形成阻挡层。在所述阻挡层上形成金属层以填充所述至少一个特征的深度。蚀刻所述金属层和所述阻挡层以将所述金属层的深度减小到凹陷深度并从所述第二电介质材料的所述侧壁去除所述阻挡层。
本公开的其他实施方案涉及处理方法，所述处理方法包括提供包含电介质材料的基板，所述电介质材料具有形成在其上的至少一个特征。所述至少一个特征具有至少一个侧壁和底部。从所述电介质材料的表面到所述特征的底部的距离限定了所述特征的深度。钝化在所述特征的侧壁处的所述电介质材料以形成钝化的电介质层。在所述钝化的电介质层上的至少一个侧壁和所述至少一个特征的底部上形成阻挡层。在所述特征中沉积金属层以填充所述至少一个特征。将金属层和阻挡层的一部分去除至预定深度，并从所述钝化的电介质层去除阻挡层。
本公开内容的另外实施方案涉及处理方法，所述处理方法包括提供包含电介质材料的基板。所述基板具有至少一个特征，所述至少一个特征具有至少一个侧壁和底部以限定体积。在所述至少一个侧壁和所述底部上形成阻挡层。在所述阻挡层上形成金属层以填充所述至少一个特征的体积。蚀刻所述金属层以暴露所述特征内的所述阻挡层的一部分。蚀刻所述阻挡层的暴露部分以去除所述阻挡层的暴露部分。重复蚀刻所述金属层和蚀刻所述阻挡层，直到已经去除了预定深度的金属层。
附图说明
因此，以可以详细地理解本公开的上述特征的方式，可以通过参考实施方式提供对上述简要概述的本公开的更具体描述，所述实施方式中的一些实施方式示出在附图中。然而，应注意，附图仅示出了本公开的典型实施方式，因此不应视为限制本发明的范围，因为本公开可允许其他同等有效的实施方式。
图1示出了根据本公开的一个或多个实施方案的基板的示意性剖视图，所述基板具有形成在其中的特征；
图2A示出了根据本公开的一个或多个实施方案的基板的示意性剖视图，所述基板具有不同材料和在所述材料中的一种材料上形成的特征；
图2B示出了图2A的基板的俯视图；
图3A和图3B示出了根据本公开的一个或多个实施方案的金属凹陷过程的示意性剖视图；和
图4A和图4B示出了根据本公开的一个或多个实施方案的金属凹陷过程的示意性剖视图；
图5A至图5D示出了根据本公开的一个或多个实施方案的金属凹陷过程的示意性剖视图；和
图6A至图6F示出了根据本公开的一个或多个实施方案的金属凹陷过程的示意性剖视图。
具体实施方式
在描述本公开的若干示例性实施方案之前，应理解的是，本公开不限于以下描述中阐述的构造或处理步骤的细节。本公开能够具有其他实施方案并且能够以各种方式实践或执行。
如本文所使用的“基板”是指任何基板或形成在基板上的材料表面，在制造过程期间在所述基板或形成在所述基板上的所述材料表面上进行膜处理。例如，可以在上面进行处理的基板表面包括诸如硅、氧化硅、应变硅、绝缘体上硅(SOI)、碳掺杂的氧化硅、非晶硅、掺杂的硅、锗、砷化镓、玻璃、蓝宝石的材料，以及诸如金属、金属氮化物、金属合金的任何其他材料，以及其他导电材料，具体取决于应用。基板包括但不限于半导体晶片。可以将基板暴露于预处理工艺以抛光、蚀刻、还原、氧化、羟基化、退火和/或烘焙基板表面。除了直接在基板本身的表面上进行膜处理之外，在本公开中，如下面更详细公开的，也可以在基板上形成的底层上执行所公开的任何膜处理步骤，并且术语“基板表面”旨在包括如上下文所指示的这种底层。因此，例如，在已经将膜/层或部分膜/层沉积到基板表面上的情况下，新沉积的膜/层的暴露表面变成基板表面。
如在本说明书和所附权利要求书中使用的，术语“前体”、“反应物”、“反应气体”等可互换使用，是指可与基板表面反应或者与在基板表面上形成的膜反应的任何气态物质。
常规金属凹陷是相对于金属阻挡层选择性的，从而导致在所述金属层顶部上方形成阻挡层的“耳朵”。使用长处理时间实现目标凹陷深度的金属凹陷工艺导致微负载，在所述微负载中较宽特征具有比较小特征更大量的蚀刻。该负载效应是随着较长处理时间而逐渐恶化的。另外，金属阻挡层凹陷过程倾向于攻击芯金属而导致损伤。
因此，本公开的一个或多个实施方案有利地提供了用于使金属层和含金属的衬垫凹陷至大致相同高度的方法。本发明的一些实施方案有利地提供使金属层和阻挡层凹陷而不会过度损伤金属或相邻电介质层的方法。本公开的一些实施方案有利地提供了快速且均匀地去除金属层和衬垫层的方法。本公开的一些实施方案提供了以最小的芯金属损伤和最小的微负载效应使金属层和含金属的阻挡层凹陷到预定深度的方法。
本公开的一个或多个实施方案提供了使用具有不同表面附着性的附加电介质层来提高衬垫的蚀刻速率的方法。一些实施方案提供了使用电介质表面(即，特征侧壁)的选择性钝化(例如，通过UV或等离子体)来改变钝化表面上的表面附着性的方法。本公开的一些实施方案提供了循环地蚀刻金属层和阻挡层的方法。
本公开的一些实施方案提供了用于通过以下步骤使金属和阻挡层凹陷到相同高度的互连集成方案的方法和方案：(1)使用芯金属(Co或Cu)凹陷然后是金属阻挡层凹陷(TiN或TaN/Co/Ru)的连续凹陷；(2)针对芯金属而选择性地，使芯金属在室温和酸性pH水平下暴露于含有过氧化氢和配制化学物质的湿化学物质；(3)针对金属阻挡层而选择性地，在30℃至60℃下将含有过氧化氢和氢氧化铵的用于金属阻挡层凹陷的湿化学物质调节到碱性pH水平。为了促进阻挡层去除效率，可以通过以下项中的一者或多者来处理超低介电常数的侧壁电介质：(a)在电介质蚀刻后用N2/NH3等离子体进行表面氮化；(b)薄(例如，)共形富氮膜沉积和通孔底部蚀穿；(c)其他表面钝化膜，诸如AlN、AlON、AlO、SiCN、SiOC、SiOCN或它们的组合，所述表面钝化膜密封超低介电常数表面孔并有助于阻挡层凹陷；(d)使用宽带UV在高温(200至400℃)下用(二甲基氨基)二甲基硅烷(DMADMS)和类似前体进行UV孔密封；以及(e)使用氮化物电介质帽使凹陷前部的顶部不同。
图1示出了包含电介质材料110的基板100，所述电介质材料具有形成在其中的至少一个特征114。特征114在电介质材料110的顶表面112中形成开口。特征114从顶表面112延伸深度D到达底部116。特征114具有至少一个侧壁118，所述至少一个侧壁限定特征114的宽度W。由至少一个侧壁118和底部116形成的开口区域也被称为间隙。由至少一个侧壁118和底部116形成的间隙具有体积，所述体积测量到电介质材料110的顶表面112的水平面处的平面。图1中示出的特征114具有侧壁118，所述侧壁向内倾斜，使得特征114的底部116宽度小于特征114的顶表面112宽度。这仅仅代表一种可能的配置，并且不应被视为限制本公开的范围。特征114的形状可以是圆柱形、圆锥形、截头圆锥形、倒锥形、截头倒锥形(如图所示)、沟槽或其他形状。
测量特征的宽度W作为侧壁之间的平均宽度，所述平均宽度为从顶表面112测量的特征114中的深度的函数。图1中所示的实施方案示出了包含电介质材料110的基板100，所述电介质材料形成特征114的顶表面112、底部116和侧壁118的边界。然而，本领域技术人员将认识到，特征114的侧壁118和底部116可以由不同的材料界定。如以这种方式使用，术语“由...界定(bounded)”是指所述部件的侧面和/或底部上的材料。例如，图2A中所示的实施方案具有由导电材料120限定的特征114的底部116，而特征114的侧壁118由电介质材料110限定。也可以使用相反的材料布置。
一些实施方案中的特征114是通孔。当从顶表面112观察时，如图2B中所示，特征114看起来是圆形或椭圆形开口。图2B中的特征114具有一个侧壁118，所述侧壁118是材料的连续区段。这种类型的特征114的宽度W被测量为特征114上的平均宽度或直径。
图3A和图3B示出了用于在形成于电介质材料110中的特征114中使金属层140凹陷的传统蚀刻工艺。图3A中示出的特征114包括阻挡层130，所述阻挡层沿着特征114的侧壁118和底部116形成衬垫。金属层140填充特征114的体积直到顶表面142，所述顶表面142与电介质材料110的顶表面112大致共面。在将基板100暴露于蚀刻工艺之后，如图3B所示，金属层140的顶表面142凹陷到低于电介质材料110的顶表面112。蚀刻工艺还去除了一些阻挡层130，使阻挡层残留物135留在凹陷金属层140的顶表面142与电介质材料110的顶表面112之间的侧壁118上。阻挡层残留物135也被称为“耳朵”。
参照图4A和图4B，本公开的一个或多个实施方案涉及使金属层凹陷的处理方法。提供基板200，所述基板具有第一电介质材料210和沉积在第一电介质材料上的第二电介质材料220。第二电介质材料220具有厚度T。基板200包括至少一个特征214，所述特征形成在第一电介质材料210中并穿过第二电介质材料220。特征214具有至少一个侧壁218和底部216。在靠近第二电介质材料220的顶表面222处，侧壁218由第二电介质材料220界定。换句话说，侧壁218由穿过第二电介质材料220的厚度T的第二电介质材料220界定并且由第二电介质材料220的厚度T下方的第一电介质材料210界定。特征的深度被限定为从第二电介质材料220的顶表面222到特征的底部216。
特征214的宽度和深度可以变化。特征的纵横比(深度:宽度)可以是任何合适的纵横比。在一些实施方案中，特征214的纵横比在0.5:1至20:1的范围内，其中典型范围为1:1至4:1。
第二电介质材料220的厚度T可以是任何合适的厚度。在一些实施方案中，第二电介质材料220的厚度T在特征214的深度的约5％至约90％的范围内，或者在特征214的深度的约5％至约70％的范围内，或者在特征214的深度的约5％至约50％的范围内，或者在特征214的深度的约10％至约30％的范围内。
第二电介质材料220与第一电介质材料210的不同之处在于组成和物理性质中的一者或多者。在一些实施方案中，第二电介质材料220可以是与第一电介质材料210不同的组成。在一些实施方案中，第一电介质材料210和第二电介质材料220是相同的组成，但第二电介质材料220比第一电介质材料210更致密和/或更少孔。在一些实施方案中，第二电介质材料220具有与第一电介质材料210不同的附着特性(关于阻挡层230)。
第一电介质材料210可以是任何合适的材料。在一些实施方案中，第一电介质材料210包括碳氧化硅(SiOC)、多孔有机硅酸盐玻璃(p-SiCOH)、掺杂或未掺杂的硅酸盐玻璃、氧化硅(SiOx)。
第二电介质材料220可以是任何合适的材料。在一些实施方案中，第二电介质材料包括SiN、SiCN、SiOC、AlOx、AlN、AlC或以上项的组合中的一者或多者。本领域技术人员将认识到，使用如“SiN”的术语并不表示所述元素的化学计算量；相反，术语“SiN”表示该材料具有硅原子和氮原子。
在特征214的至少一个侧壁218和底部216上形成阻挡层230。在第二电介质材料220的顶表面222附近，特征214的侧壁218上的阻挡层230由穿过第二电介质材料220的厚度T的第二电介质材料220界定。侧壁218上的阻挡层230也由第二电介质材料220的厚度T下方的第一电介质材料210界定。
阻挡层230可包括任何合适的组分。在一些实施方案中，阻挡层230包含氮化钛(TiN)或氮化钽(TaN)中的一者或多者。在一些实施方案中，阻挡层230包含衬垫材料(未示出)，所述衬垫材料作为单独的层或与阻挡层230混合。一些实施方案的衬垫是钴(Co)或钌(Ru)中的一者或多者。在一些实施方案中，阻挡层包含具有钴(Co)或钌(Ru)衬垫的氮化钽(TaN)。阻挡层还可包含含铝化合物(包括金属Al)或含锰化合物(包括金属Mn)。
在阻挡层230上沉积金属层240以填充至少一个特征214的深度。换句话说，特征214的体积被填充有阻挡层230和金属层240。可以通过本领域的技术人员已知的任何合适技术将金属层240沉积在特征214中。
金属层240可包含任何合适的金属。在一些实施方案中，金属层240包含钴(Co)、铜(Cu)、钨(W)、钌(Ru)、镍(Ni)、贵金属(Ir、Pt)、合金或复合导体(例如NiSi)中的一者或多者。在一些实施方案中，金属层240包含Co，并且阻挡层230包含TiN。在一些实施方案中，金属层240包含Cu，并且阻挡层230包含具有衬垫的TaN，所述衬垫包含Co或Ru中的一者或多者。
如图4B所示，在蚀刻之后，金属层240已经凹陷到凹陷深度。所述凹陷深度处的金属层240的顶表面242低于第二电介质材料220的顶表面222。在一些实施方案中，金属层240已凹陷，使得金属层240的顶表面242低于第二电介质材料220的厚度T，或低于第二电介质材料220与第一电介质材料210之间的界面215。
该蚀刻工艺还可以从第二电介质材料220的侧壁218去除阻挡层230。一些阻挡层残留物235可能保持与第一电介质材料210接触。可能保留的阻挡层残留物235在第二电介质材料220的顶表面222下方。
在一些实施方案中，蚀刻工艺包括用以选择性地蚀刻金属层240和选择性地蚀刻阻挡层230的循环性工艺或连续性工艺。在一些实施方案中，重复连续的金属层240蚀刻和阻挡层230蚀刻工艺。
该蚀刻工艺可以是本领域技术人员已知的任何合适的蚀刻工艺。蚀刻工艺也可称为芯金属凹陷。在一些实施方案中，蚀刻金属层240或使芯金属凹陷包括湿化学法，在所述湿化学法中，使金属层240在大致室温(即，在约20℃至约100℃的范围内)下，于酸性pH下暴露于过氧化氢(H2O2)。在一些实施方案中，蚀刻阻挡层230包括使基板在约30℃至约80℃范围内的温度下，暴露于具有碱性pH水平的过氧化氢(H2O2)和氢氧化铵(NH4OH)的混合物。
本公开的一些实施方案涉及半导体器件，所述半导体器件包括基板200，所述基板具有第一电介质材料210和形成在第一电介质材料上的第二电介质材料220。基板200具有形成在第一电介质材料210中并穿过第二电介质材料220的至少一个特征214。特征214具有至少一个侧壁218和底部216。所述至少一个侧壁218由第二电介质材料220和第一电介质材料210界定。
该半导体器件包括阻挡层230，所述阻挡层位于特征214内，使得阻挡层230位于由第一电介质材料210界定的侧壁218上。在一些实施方案中，阻挡层230基本上仅由第一电介质材料210界定。在一些实施方案中，阻挡层230不在由第二电介质材料220界定的特征214的侧壁218上。一些实施方案的阻挡层230是在特征214的侧壁218和底部216上的基本上共形的膜。当以这种方式使用时，“共形膜”是指膜在任何点的厚度在膜平均厚度的±10％、±5％、±2％或±1％内。
金属层240在由阻挡层230界定的特征214内。在一些实施方案中，金属层240在金属层240的侧面和底部上具有阻挡层230。在一些实施方案中，金属层240在金属层的侧面上具有阻挡层230。在一些实施方案中，金属层240的顶表面242与阻挡层230的顶部平齐或低于阻挡层230的顶部。在一些实施方案中，阻挡层残留物235在金属层240的顶表面242上方并且在第二电介质材料220下方。
图5A至图5D示出了本公开的另一实施方案。在此提供基板300，所述基板具有电介质材料310，所述电介质材料具有顶表面312和在其中形成的至少一个特征314。特征314具有侧壁318和底部316，所述侧壁和底部限定了特征314的体积。特征314的深度由从电介质材料310的顶表面312到特征314的底部316的距离限定。
基板300可以经受钝化处理，以形成图5B中所示的基板300。钝化处理将特征314的侧壁318处的电介质材料310钝化以形成钝化的电介质层320。钝化处理可以是能够改变侧壁318处的电介质材料310的特性的任何合适的处理。合适的钝化方法包括但不限于在侧壁处形成的可伸缩物理膜、用以在保持组成的同时减小电容损失(capacitance penalty)的侧壁处理或用于将侧壁的顶部部分改性直到凹陷厚度的深度的梯度处理。在一些实施方案中，钝化电介质材料310包括UV暴露或等离子体暴露中的一者多者。在一些实施方案中，钝化电介质材料310包括形成氮化物。在一些实施方案中，钝化电介质材料310包括处理至少一个特征314的侧壁318，使得钝化的电介质层320上的阻挡层330的附着力低于电介质材料310上的阻挡层330的附着力。
参照图5C，阻挡层330可以形成在特征314的侧壁318和底部316上。阻挡层330覆盖侧壁318上的钝化的电介质层320。阻挡层330可以通过任何合适的技术形成，所述合适的技术包括但不限于共形原子层沉积(ALD)，之后进行化学机械平坦化以从电介质材料310的顶表面312去除沉积。
然后可以用金属层340填充特征314的间隙，以使得金属层340的顶表面342与电介质材料310的顶表面312大致平齐。金属层340可以通过任何合适的技术沉积，所述合适的技术包括但不限于毯覆式沉积，之后进行化学机械平坦化。
在一些实施方案中，钝化特征314的侧壁318处的电介质材料310形成了梯度钝化的电介质层320，使得从电介质材料310的顶表面312到预定深度的侧壁318部分被改性为，使得从钝化的电介质层320去除阻挡层比从电介质材料310去除阻挡层更容易。在一些实施方案中，梯度钝化的预定深度与金属层340将凹陷到的预定深度大致相同。
如图5D所示，在蚀刻之后，金属层340已经凹陷到预定的凹陷深度。所述凹陷深度处的金属层340的顶表面342低于电介质材料310的顶表面312。蚀刻工艺还可以从钝化的电介质层320去除阻挡层330。
在一些实施方案中，蚀刻工艺包括用以选择性地蚀刻金属层340和选择性地蚀刻阻挡层330的循环性工艺或连续性工艺。在一些实施方案中，重复连续的金属层340蚀刻和阻挡层330蚀刻工艺。
该蚀刻工艺可以是本领域技术人员已知的任何合适的蚀刻工艺。蚀刻工艺也可称为芯金属凹陷。在一些实施方案中，蚀刻金属层340或使芯金属凹陷包括湿化学法，在所述湿化学法中使金属层340在大致室温(即，在约20℃至约100℃的范围内)下，于酸性pH下暴露于过氧化氢(H2O2)。在一些实施方案中，蚀刻阻挡层330包括使基板在约30℃至约80℃范围内的温度下，暴露于具有碱性pH水平的过氧化氢(H2O2)和氢氧化铵(NH4OH)的混合物。
本公开的一些实施方案涉及半导体器件，所述半导体器件包括具有电介质材料310的基板300，所述电介质材料具有形成在其中的至少一个特征314。所述至少一个特征314具有至少一个侧壁318和底部316。基板300具有钝化的电介质层320，所述钝化的电介质层形成侧壁318的至少一部分。在一些实施方案中，钝化的电介质层320形成在侧壁318的顶部部分处，靠近电介质材料310的顶表面312，并且不延伸到特征的底部316。
该半导体器件包括阻挡层330，所述阻挡层位于特征314内，使得阻挡层330位于由电介质材料310或钝化的电介质层320界定的侧壁318上。在一些实施方案中，阻挡层330基本上仅由钝化的电介质层320界定。一些实施方案的阻挡层330是在特征314的侧壁318和底部316上的基本上共形的膜。
金属层340在由阻挡层330界定的特征314内。在一些实施方案中，金属层340在金属层340的侧面和底部上具有阻挡层330。在一些实施方案中，金属层340在金属层的侧面上具有阻挡层330。在一些实施方案中，金属层340的顶表面342与阻挡层330的顶部平齐或低于阻挡层330的顶部。
图6A至图6F示出了本公开的另一实施方案。图6A示出了可用于本文所述方法的基板400。基板400具有电介质材料410，所述电介质材料具有顶表面412。在电介质材料410中形成至少一个特征414。如上所述，特征414具有底部416和至少一个侧壁418。阻挡层430形成在特征414的底部416和侧壁418上，并且金属层440在阻挡层430上填充间隙以填充特征414。
在图6B中，基板400已暴露于蚀刻工艺以去除金属层440的一部分，以使金属层440的顶表面442相对于电介质材料410的顶表面412降低。以任何合适的量蚀刻金属层440达凹陷深度DR。在一些实施方案中，凹陷深度DR小于单层金属原子厚度。在一些实施方案中，凹陷深度DR在约至约的范围内。
蚀刻工艺使阻挡层430的在凹陷金属层440的顶表面442上方的部分431暴露。在图6C中，蚀刻阻挡层430的暴露部分431以将阻挡层的顶部降低到金属层440的顶表面442。图6D和图6E示出重复进行金属层440蚀刻及之后的阻挡层430蚀刻，直到已经去除预定深度的金属层440并且金属层440的顶表面442处于预定深度处，如图6F所示。
本公开的一些实施方案涉及半导体器件，所述半导体器件包括具有电介质材料410的基板400，所述基板具有形成在其中的至少一个特征414。所述至少一个特征414具有至少一个侧壁418和底部416。
该半导体器件包括阻挡层430，所述阻挡层位于特征414内，使得阻挡层430位于由电介质材料410界定的一部分侧壁418上。在一些实施方案中，阻挡层430基本上仅由电介质材料410界定。一些实施方案的阻挡层430是在特征414的侧壁418和底部416上的基本上共形的膜。
金属层440在由阻挡层430界定的特征414内。在一些实施方案中，金属层440在金属层440的侧面和底部上具有阻挡层430。在一些实施方案中，金属层440在金属层440的侧面上具有阻挡层430。在一些实施方案中，金属层440的顶表面442与阻挡层430的顶部基本上平齐。当以这种方式使用时，术语“基本上平齐”意谓金属层的顶部在或内与阻挡层的顶部平齐。在一些实施方案中，阻挡层430的顶部低于金属层440的顶表面442。
在本说明书中对“一个实施方案”、“某些实施方案”、“一个或多个实施方案”或“一实施方案”的提及意味着结合该些实施方案描述的特定特征、结构、材料或特性包括在本公开的至少一个实施方案中。因此，在整个本说明书的各处出现的表述如“在一个或多个实施方案中”、“在某些实施方案中”、“在一个实施方案中”或“在实施方案中”不一定是指本公开的同一实施方案。此外，该些特定特征、结构、材料或特性可以以任何合适的方式组合在一个或多个实施方案中。
虽然在本文中已经参照具体实施方案描述了本公开，但应了解，这些实施方案仅说明了本公开的原理和应用。对于本领域的技术人员显而易见的是，在不脱离本公开的精神和范围的情况下，可以对本公开的方法和装置进行各种修改和变化。因此，本公开旨在包括在所附权利要求书及其等同物的范围内的修改和变化。

Claims (20)

1.一种处理方法，所述处理方法包括：
提供基板，所述基板包含第一电介质材料和沉积在所述第一电介质材料上的第二电介质材料，所述第二电介质材料具有某一厚度，所述基板包括形成在所述第一电介质材料和所述第二电介质材料中的至少一个特征，所述至少一个特征具有至少一个侧壁和底部，所述特征的深度被限定为从所述第二电介质材料的顶表面到所述特征的所述底部，在所述至少一个侧壁和所述底部上形成阻挡层，并且在所述阻挡层上形成金属层以填充所述至少一个特征的所述深度；以及
蚀刻所述金属层和所述阻挡层以将所述金属层的深度减小到凹陷深度并从所述第二电介质材料的所述侧壁去除所述阻挡层。
2.根据权利要求1所述的方法，其中所述第一电介质材料包括SiOC、多孔有机硅酸盐玻璃(p-SiCOH)、掺杂或未掺杂的硅酸盐或SiOx中的一者或多者。
3.根据权利要求1所述的方法，其中所述第二电介质材料包括SiN、SiCN、SiOC、AlN、AlC、AlOx、或它们的组合中的一者或多者。
4.根据权利要求1所述的方法，其中所述第二电介质材料的密度高于所述第一电介质材料的密度。
5.根据权利要求1所述的方法，其中所述金属层包含Co、Cu、W、Ru、Ni、Ir、Pt或Si中的一者或多者。
6.根据权利要求1所述的方法，其中所述阻挡层包含TiN。
7.根据权利要求1所述的方法，其中所述阻挡层包含具有Co或Ru衬垫的TaN，或含Mn或Al的化合物。
8.根据权利要求1所述的方法，其中所述金属层包含Co并且所述阻挡层包含TiN。
9.根据权利要求1所述的方法，其中所述金属层包含Cu，并且所述阻挡层包含具有衬垫的TaN，所述衬垫包含Co或Ru中的一者或多者。
10.一种处理方法，所述处理方法包括：
提供基板，所述基板包含电介质材料，所述电介质材料具有形成在其上的至少一个特征，所述至少一个特征具有至少一个侧壁和底部，从所述电介质材料的表面到所述特征的所述底部的距离限定所述特征的深度；
钝化在所述特征的所述侧壁处的所述电介质材料以形成钝化的电介质层；
在所述钝化的电介质层上的所述至少一个侧壁和所述至少一个特征的所述底部上形成阻挡层；
在所述特征中沉积金属层以填充所述至少一个特征；以及
将所述金属层和所述阻挡层的一部分去除至预定深度，并从所述钝化的电介质层中去除所述阻挡层。
11.根据权利要求10所述的方法，其中钝化所述电介质材料包括处理所述至少一个特征的所述侧壁，使得在所述钝化的电介质层上的所述阻挡层的附着力低于在所述电介质材料上的所述阻挡层的附着力。
12.根据权利要求10所述的方法，其中钝化在所述特征的所述侧壁处的所述电介质材料形成了梯度钝化的电介质层，使得从所述电介质材料的表面到预定深度的一部分侧壁被改性为，使得从所述钝化的电介质层去除所述阻挡层比从所述电介质材料去除所述阻挡层更容易。
13.根据权利要求12所述的方法，其中所述预定深度是在去除所述金属层和所述阻挡层之后所述金属层的所述预定深度。
14.根据权利要求10所述的方法，其中钝化所述电介质材料包括UV暴露或等离子体暴露中的一者多者。
15.根据权利要求14所述的方法，其中钝化所述电介质材料包括形成氮化物。
16.一种处理方法，所述处理方法包括：
提供基板，所述基板包含电介质材料，所述基板具有至少一个特征，所述至少一个特征具有至少一个侧壁和底部，所述至少一个侧壁和所述底部限定体积，在所述至少一个侧壁和所述底部上形成阻挡层，并且在所述阻挡层上形成金属层以填充所述至少一个特征的所述体积；
蚀刻所述金属层以暴露所述特征内的所述阻挡层的一部分；
蚀刻所述阻挡层的所述暴露部分以去除所述阻挡层的所述暴露部分；以及
重复蚀刻所述金属层和蚀刻所述阻挡层，直到已经去除了预定深度的所述金属层。
17.根据权利要求16所述的方法，其中所述金属层包含Co、Cu、W、Ru、Ni、Ir、Pt或Si中的一者或多者。
18.根据权利要求16所述的方法，其中所述阻挡层包含TiN。
19.根据权利要求16所述的方法，其中所述阻挡层包含具有Co或Ru衬垫的TaN、含锰化合物或含铝化合物。
20.根据权利要求16所述的方法，其中所述金属层包含Co并且所述阻挡层包含TiN，或者所述金属层包含Cu并且所述阻挡层包含具有衬垫的TaN，所述衬垫包含Co或Ru中的一者或多者。
CN201811489710.XA 2017-12-07 2018-12-06 用于使金属和阻挡层-衬垫可控凹陷的方法 Pending CN110034017A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201762596113P 2017-12-07 2017-12-07
US62/596,113 2017-12-07

Publications (1)

Publication Number Publication Date
CN110034017A true CN110034017A (zh) 2019-07-19

Family

ID=64664065

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201811489710.XA Pending CN110034017A (zh) 2017-12-07 2018-12-06 用于使金属和阻挡层-衬垫可控凹陷的方法

Country Status (6)

Country Link
US (2) US11062942B2 (zh)
EP (1) EP3496136A1 (zh)
JP (1) JP2019106538A (zh)
KR (1) KR20190067725A (zh)
CN (1) CN110034017A (zh)
TW (1) TW201929059A (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10916477B2 (en) * 2018-09-28 2021-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. Fin field-effect transistor devices and methods of forming the same
US11450562B2 (en) * 2019-09-16 2022-09-20 Tokyo Electron Limited Method of bottom-up metallization in a recessed feature
KR20210087352A (ko) 2020-01-02 2021-07-12 삼성전자주식회사 에어 스페이서를 가지는 반도체 소자
JP2022104085A (ja) * 2020-12-28 2022-07-08 株式会社Ｓｃｒｅｅｎホールディングス 配線形成方法および基板処理装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7605082B1 (en) * 2005-10-13 2009-10-20 Novellus Systems, Inc. Capping before barrier-removal IC fabrication method
US20090321931A1 (en) * 2008-06-27 2009-12-31 Samsung Electronics Co., Ltd. Semiconductor device and method of manufacturing the same
CN107078040A (zh) * 2014-10-17 2017-08-18 盛美半导体设备（上海）有限公司 阻挡层的去除方法和半导体结构的形成方法
US20170317026A1 (en) * 2016-04-18 2017-11-02 International Business Machines Corporation Selective and non-selective barrier layer wet removal

Family Cites Families (113)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4671970A (en) 1986-02-05 1987-06-09 Ncr Corporation Trench filling and planarization process
KR0165813B1 (ko) 1995-04-12 1999-02-01 문정환 접속홀의 플러그 형성 방법
JPH08340047A (ja) * 1995-06-13 1996-12-24 Sony Corp 半導体装置の配線層構造およびその製造方法
US5872052A (en) 1996-02-12 1999-02-16 Micron Technology, Inc. Planarization using plasma oxidized amorphous silicon
KR100223334B1 (ko) 1996-06-29 1999-10-15 김영환 반도체소자의 금속배선형성방법
US6143653A (en) 1998-10-04 2000-11-07 Promos Technologies, Inc. Method of forming tungsten interconnect with tungsten oxidation to prevent tungsten loss
KR20000026588A (ko) 1998-10-21 2000-05-15 윤종용 콘택홀을 갖는 반도체 장치 및 그 제조방법
US6130151A (en) 1999-05-07 2000-10-10 Taiwan Semiconductor Manufacturing Company Method of manufacturing air gap in multilevel interconnection
JP2001015479A (ja) 1999-06-29 2001-01-19 Toshiba Corp 半導体装置の製造方法
JP2001077118A (ja) * 1999-06-30 2001-03-23 Toshiba Corp 半導体装置およびその製造方法
JP2003507888A (ja) 1999-08-18 2003-02-25 ステアーグ アール ティ ピー システムズ インコーポレイテッド 半導体ウェーハ上に銅の特徴を生じさせる方法
US6576113B1 (en) 1999-10-29 2003-06-10 California Institute Of Technology Method of electroplating of high aspect ratio metal structures into semiconductors
US6794311B2 (en) * 2000-07-14 2004-09-21 Applied Materials Inc. Method and apparatus for treating low k dielectric layers to reduce diffusion
US6373087B1 (en) 2000-08-31 2002-04-16 Agere Systems Guardian Corp. Methods of fabricating a metal-oxide-metal capacitor and associated apparatuses
US7192803B1 (en) 2000-10-13 2007-03-20 Bridge Semiconductor Corporation Method of making a semiconductor chip assembly with simultaneously formed interconnect and connection joint
US6653200B2 (en) 2001-01-26 2003-11-25 Applied Materials, Inc. Trench fill process for reducing stress in shallow trench isolation
JP2002252281A (ja) 2001-02-27 2002-09-06 Sony Corp 半導体装置およびその製造方法
US6528884B1 (en) 2001-06-01 2003-03-04 Advanced Micro Devices, Inc. Conformal atomic liner layer in an integrated circuit interconnect
US7279119B2 (en) 2001-06-14 2007-10-09 Ppg Industries Ohio, Inc. Silica and silica-based slurry
JP2003142579A (ja) * 2001-11-07 2003-05-16 Hitachi Ltd 半導体装置の製造方法および半導体装置
JP4959921B2 (ja) 2002-03-28 2012-06-27 プレジデント アンド フェロウズ オブ ハーバード カレッジ 二酸化珪素ナノラミネートの蒸着
US8298933B2 (en) 2003-04-11 2012-10-30 Novellus Systems, Inc. Conformal films on semiconductor substrates
US7276787B2 (en) 2003-12-05 2007-10-02 International Business Machines Corporation Silicon chip carrier with conductive through-vias and method for fabricating same
US7211844B2 (en) 2004-01-29 2007-05-01 International Business Machines Corporation Vertical field effect transistors incorporating semiconducting nanotubes grown in a spacer-defined passage
KR100923192B1 (ko) 2004-03-16 2009-10-22 가부시키가이샤 아이에이치아이 반도체 장치의 제조 방법
US7521378B2 (en) 2004-07-01 2009-04-21 Micron Technology, Inc. Low temperature process for polysilazane oxidation/densification
US7244344B2 (en) 2005-02-03 2007-07-17 Applied Materials, Inc. Physical vapor deposition plasma reactor with VHF source power applied through the workpiece
US8324660B2 (en) 2005-05-17 2012-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
JP2007005381A (ja) 2005-06-21 2007-01-11 Matsushita Electric Ind Co Ltd プラズマエッチング方法、及びプラズマエッチング装置
US7393789B2 (en) 2005-09-01 2008-07-01 Micron Technology, Inc. Protective coating for planarization
US7351648B2 (en) 2006-01-19 2008-04-01 International Business Machines Corporation Methods for forming uniform lithographic features
US7368394B2 (en) 2006-02-27 2008-05-06 Applied Materials, Inc. Etch methods to form anisotropic features for high aspect ratio applications
US7288463B1 (en) 2006-04-28 2007-10-30 Novellus Systems, Inc. Pulsed deposition layer gap fill with expansion material
US7956465B2 (en) 2006-05-08 2011-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Reducing resistivity in interconnect structures of integrated circuits
US7329956B1 (en) * 2006-09-12 2008-02-12 Taiwan Semiconductor Manufacturing Company, Ltd. Dual damascene cleaning method
JP2008108757A (ja) 2006-10-23 2008-05-08 Matsushita Electric Works Ltd 化合物半導体発光素子およびそれを用いる照明装置ならびに化合物半導体素子の製造方法
US7598170B2 (en) 2007-01-26 2009-10-06 Asm America, Inc. Plasma-enhanced ALD of tantalum nitride films
US20080242097A1 (en) 2007-03-28 2008-10-02 Tim Boescke Selective deposition method
US20090017631A1 (en) 2007-06-01 2009-01-15 Bencher Christopher D Self-aligned pillar patterning using multiple spacer masks
WO2008153674A1 (en) 2007-06-09 2008-12-18 Boris Kobrin Method and apparatus for anisotropic etching
US20090072409A1 (en) 2007-09-14 2009-03-19 International Business Machines Corporation Interconnect Structures Incorporating Air-Gap Spacers
US7541297B2 (en) 2007-10-22 2009-06-02 Applied Materials, Inc. Method and system for improving dielectric film quality for void free gap fill
US20100330805A1 (en) 2007-11-02 2010-12-30 Kenny Linh Doan Methods for forming high aspect ratio features on a substrate
US7985977B2 (en) 2007-12-11 2011-07-26 Hvvi Semiconductors, Inc. Sacrificial pillar dielectric platform
KR101477661B1 (ko) 2008-07-17 2014-12-31 삼성전자주식회사 텅스텐 재성장을 통한 심 없는 텅스텐 패턴 및 그 패턴형성 방법
US8169031B2 (en) 2008-08-26 2012-05-01 International Business Machines Corporation Continuous metal semiconductor alloy via for interconnects
US8101456B2 (en) 2008-10-01 2012-01-24 International Business Machines Corporation Method to reduce a via area in a phase change memory cell
KR101026486B1 (ko) 2008-10-22 2011-04-01 주식회사 하이닉스반도체 반도체 소자 및 그의 제조방법
JP5133852B2 (ja) 2008-11-13 2013-01-30 ルネサスエレクトロニクス株式会社 半導体装置の製造方法及び半導体装置
KR101534678B1 (ko) 2009-02-12 2015-07-08 삼성전자주식회사 텅스텐 콘택 플러그를 산소 분위기에서 ｒｔａ 처리하고, ｒｔｏ 처리된 텅스텐 플러그를 수소 분위기에서 환원시키는 반도체 소자의 제조방법
US8435830B2 (en) 2009-03-18 2013-05-07 Samsung Electronics Co., Ltd. Methods of fabricating semiconductor devices
US8575753B2 (en) 2009-05-27 2013-11-05 Samsung Electronics Co., Ltd. Semiconductor device having a conductive structure including oxide and non oxide portions
US8531033B2 (en) 2009-09-07 2013-09-10 Advanced Interconnect Materials, Llc Contact plug structure, semiconductor device, and method for forming contact plug
JP2011060803A (ja) 2009-09-07 2011-03-24 Toshiba Corp 半導体装置
US8274065B2 (en) 2009-10-19 2012-09-25 Macronix International Co., Ltd. Memory and method of fabricating the same
JP5654794B2 (ja) * 2010-07-15 2015-01-14 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US8778749B2 (en) 2011-01-12 2014-07-15 Sandisk Technologies Inc. Air isolation in high density non-volatile memory
US9048296B2 (en) * 2011-02-11 2015-06-02 International Business Machines Corporation Method to fabricate copper wiring structures and structures formed thereby
US8900988B2 (en) 2011-04-15 2014-12-02 International Business Machines Corporation Method for forming self-aligned airgap interconnect structures
JP2011233922A (ja) 2011-07-20 2011-11-17 Ihi Corp 素子間分離領域の形成方法
US8946082B2 (en) 2011-09-16 2015-02-03 GlobalFoundries, Inc. Methods for forming semiconductor devices
KR20130046664A (ko) 2011-10-28 2013-05-08 삼성전자주식회사 패턴 형성 방법 및 이를 이용한 반도체 소자의 제조 방법
CN113862634A (zh) 2012-03-27 2021-12-31 诺发系统公司 钨特征填充
US8860001B2 (en) 2012-04-09 2014-10-14 Freescale Semiconductor, Inc. ReRAM device structure
US20140029181A1 (en) 2012-07-27 2014-01-30 Florian Gstrein Interlayer interconnects and associated techniques and configurations
US9245987B2 (en) 2012-11-29 2016-01-26 Micron Technology, Inc. Semiconductor devices and fabrication methods
US8901607B2 (en) 2013-01-14 2014-12-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and fabricating the same
US9312220B2 (en) 2013-03-12 2016-04-12 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for a low-K dielectric with pillar-type air-gaps
US9178011B2 (en) 2013-03-13 2015-11-03 Intermolecular, Inc. Deposition of anisotropic dielectric layers orientationally matched to the physically separated substrate
US9012322B2 (en) 2013-04-05 2015-04-21 Intermolecular, Inc. Selective etching of copper and copper-barrier materials by an aqueous base solution with fluoride addition
US9040421B2 (en) 2013-05-03 2015-05-26 GlobalFoundries, Inc. Methods for fabricating integrated circuits with improved contact structures
US9219007B2 (en) 2013-06-10 2015-12-22 International Business Machines Corporation Double self aligned via patterning
CN105493249B (zh) 2013-09-27 2019-06-14 英特尔公司 用于后段(beol)互连的先前层自对准过孔及插塞图案化
EP3796371A3 (en) 2013-09-27 2021-10-06 INTEL Corporation Self-aligned via and plug patterning for back end of line (beol) interconnects
US20150111374A1 (en) 2013-10-18 2015-04-23 International Business Machines Corporation Surface treatment in a dep-etch-dep process
US8951429B1 (en) 2013-10-29 2015-02-10 Applied Materials, Inc. Tungsten oxide processing
US9362413B2 (en) 2013-11-15 2016-06-07 Cbrite Inc. MOTFT with un-patterned etch-stop
US9312168B2 (en) 2013-12-16 2016-04-12 Applied Materials, Inc. Air gap structure integration using a processing system
US9236292B2 (en) 2013-12-18 2016-01-12 Intel Corporation Selective area deposition of metal films by atomic layer deposition (ALD) and chemical vapor deposition (CVD)
JP6297884B2 (ja) 2014-03-28 2018-03-20 東京エレクトロン株式会社 タングステン膜の成膜方法
KR102377372B1 (ko) 2014-04-02 2022-03-21 어플라이드 머티어리얼스, 인코포레이티드 인터커넥트들을 형성하기 위한 방법
US9368395B1 (en) 2014-05-06 2016-06-14 Globalfoundries Inc. Self-aligned via and air gap
US9299745B2 (en) 2014-05-08 2016-03-29 GlobalFoundries, Inc. Integrated circuits having magnetic tunnel junctions (MTJ) and methods for fabricating the same
US9281382B2 (en) 2014-06-04 2016-03-08 Stmicroelectronics, Inc. Method for making semiconductor device with isolation pillars between adjacent semiconductor fins
US9627318B2 (en) 2014-06-16 2017-04-18 Taiwan Semiconductor Manufacturing Company Ltd. Interconnect structure with footing region
US9679852B2 (en) 2014-07-01 2017-06-13 Micron Technology, Inc. Semiconductor constructions
US9324650B2 (en) * 2014-08-15 2016-04-26 International Business Machines Corporation Interconnect structures with fully aligned vias
US9356047B2 (en) 2014-08-18 2016-05-31 Globalfoundries Inc. Integrated circuits with self aligned contact structures for improved windows and fabrication methods
US9508642B2 (en) 2014-08-20 2016-11-29 Globalfoundries Inc. Self-aligned back end of line cut
US9349637B2 (en) 2014-08-21 2016-05-24 Lam Research Corporation Method for void-free cobalt gap fill
US9735030B2 (en) 2014-09-05 2017-08-15 Fujifilm Planar Solutions, LLC Polishing compositions and methods for polishing cobalt films
US9515085B2 (en) 2014-09-26 2016-12-06 Sandisk Technologies Llc Vertical memory device with bit line air gap
US20160111342A1 (en) 2014-10-17 2016-04-21 Lam Research Corporation Method and apparatus for characterizing metal oxide reduction
US10043709B2 (en) * 2014-11-07 2018-08-07 Applied Materials, Inc. Methods for thermally forming a selective cobalt layer
US10727122B2 (en) 2014-12-08 2020-07-28 International Business Machines Corporation Self-aligned via interconnect structures
KR102310834B1 (ko) 2014-12-22 2021-10-07 도쿄엘렉트론가부시키가이샤 그래프팅 중합체 물질의 사용으로 기판의 패턴화
US20160260779A1 (en) 2015-03-06 2016-09-08 Kabushiki Kaisha Toshiba Non-volatile resistive random access memory device
US10002834B2 (en) * 2015-03-11 2018-06-19 Applied Materials, Inc. Method and apparatus for protecting metal interconnect from halogen based precursors
US9362165B1 (en) 2015-05-08 2016-06-07 Globalfoundries Inc. 2D self-aligned via first process flow
US9543148B1 (en) 2015-09-01 2017-01-10 Lam Research Corporation Mask shrink layer for high aspect ratio dielectric etch
US9716065B2 (en) 2015-09-14 2017-07-25 International Business Machines Corporation Via bottom structure and methods of forming
US9721888B2 (en) 2015-12-08 2017-08-01 International Business Machines Corporation Trench silicide with self-aligned contact vias
US10157787B2 (en) * 2015-12-17 2018-12-18 Applied Materials, Inc. Method and apparatus for depositing cobalt in a feature
US10163704B2 (en) 2015-12-29 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and a method for fabricating the same
WO2017136577A1 (en) 2016-02-02 2017-08-10 Tokyo Electron Limited Self-alignment of metal and via using selective deposition
US11127629B2 (en) 2016-05-17 2021-09-21 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and fabricating method thereof
US9806018B1 (en) * 2016-06-20 2017-10-31 International Business Machines Corporation Copper interconnect structures
JP2019530242A (ja) 2016-09-30 2019-10-17 アプライド マテリアルズ インコーポレイテッドＡｐｐｌｉｅｄ Ｍａｔｅｒｉａｌｓ，Ｉｎｃｏｒｐｏｒａｔｅｄ 自己整合ビアの形成方法
TWI719262B (zh) 2016-11-03 2021-02-21 美商應用材料股份有限公司 用於圖案化之薄膜的沉積與處理
TW201833991A (zh) 2016-11-08 2018-09-16 美商應用材料股份有限公司 自對準圖案化之方法
US10090247B1 (en) * 2017-05-03 2018-10-02 International Business Machines Corporation Semiconductor device formed by wet etch removal of Ru selective to other metals
WO2018227110A1 (en) 2017-06-10 2018-12-13 Applied Materials, Inc. Methods of forming self-aligned vias and air gaps
US10957579B2 (en) * 2018-11-06 2021-03-23 Samsung Electronics Co., Ltd. Integrated circuit devices including a via and methods of forming the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7605082B1 (en) * 2005-10-13 2009-10-20 Novellus Systems, Inc. Capping before barrier-removal IC fabrication method
US20090321931A1 (en) * 2008-06-27 2009-12-31 Samsung Electronics Co., Ltd. Semiconductor device and method of manufacturing the same
CN107078040A (zh) * 2014-10-17 2017-08-18 盛美半导体设备（上海）有限公司 阻挡层的去除方法和半导体结构的形成方法
US20170317026A1 (en) * 2016-04-18 2017-11-02 International Business Machines Corporation Selective and non-selective barrier layer wet removal

Also Published As

Publication number Publication date
JP2019106538A (ja) 2019-06-27
EP3496136A1 (en) 2019-06-12
KR20190067725A (ko) 2019-06-17
TW201929059A (zh) 2019-07-16
US11705366B2 (en) 2023-07-18
US20190198389A1 (en) 2019-06-27
US20210305091A1 (en) 2021-09-30
US11062942B2 (en) 2021-07-13

Similar Documents

Publication Publication Date Title
CN110034017A (zh) 用于使金属和阻挡层-衬垫可控凹陷的方法
US10943901B2 (en) Semiconductor device and method
US9190323B2 (en) Semiconductor devices with copper interconnects and methods for fabricating same
US7741226B2 (en) Optimal tungsten through wafer via and process of fabricating same
US10985058B2 (en) Semiconductor device and formation thereof
CN104733378B (zh) 半导体结构及其制造方法
US8586474B2 (en) Method to form a via
US9177858B1 (en) Methods for fabricating integrated circuits including barrier layers for interconnect structures
CN108807160A (zh) 具有减小的电阻率的晶体管的金属栅极
CN104916578B (zh) 用于beol工艺的气隙方案
US8003517B2 (en) Method for forming interconnects for 3-D applications
US20110227224A1 (en) Semiconductor device and method for manufacturing the same
CN106328583B (zh) Cvd金属晶种层
KR20170030522A (ko) 금속 상호접속을 형성하는 방법
US20070128553A1 (en) Method for forming feature definitions
US10734281B2 (en) Method and structure to fabricate a nanoporous membrane
US9941204B2 (en) III-V compatible anti-fuses
US20150235953A1 (en) Semiconductor device and formation thereof
US20210327891A1 (en) Stack for 3d-nand memory cell
US20220246626A1 (en) Raised pad formations for contacts in three-dimensional structures on microelectronic workpieces
US9786596B2 (en) Fuse formed from III-V aspect ratio structure
US9564396B2 (en) Semiconductor device and process
CN112435958A (zh) 集成电路结构及其形成方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20190719