CN103081077A - 半导体装置的制造方法及半导体装置 - Google Patents

半导体装置的制造方法及半导体装置 Download PDF

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Publication number
CN103081077A
CN103081077A CN2011800389423A CN201180038942A CN103081077A CN 103081077 A CN103081077 A CN 103081077A CN 2011800389423 A CN2011800389423 A CN 2011800389423A CN 201180038942 A CN201180038942 A CN 201180038942A CN 103081077 A CN103081077 A CN 103081077A
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mentioned
film
semiconductor device
semiconductor substrate
substrate
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大见忠弘
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Tohoku University NUC
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Tohoku University NUC
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H10P14/6336—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/6903—Inorganic materials containing silicon
    • H10P14/6905—Inorganic materials containing silicon being a silicon carbide or silicon carbonitride and not containing oxygen, e.g. SiC or SiC:H
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H10P50/692—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their composition, e.g. multilayer masks or materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0245—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising use of blind vias during the manufacture
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0249—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias wherein the through-semiconductor via protrudes from backsides of the chips, wafers or substrates during the manufacture
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H10P14/6316—Formation by nitridation, e.g. nitridation of the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H10P14/6319—Formation by plasma treatments, e.g. plasma oxidation of the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/694—Inorganic materials composed of nitrides
    • H10P14/6943—Inorganic materials composed of nitrides containing silicon
    • H10P14/69433—Inorganic materials composed of nitrides containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/60—Wet etching
    • H10P50/64—Wet etching of semiconductor materials
    • H10P50/642—Chemical etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
CN2011800389423A 2010-08-10 2011-08-04 半导体装置的制造方法及半导体装置 Pending CN103081077A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2010179468A JP5419167B2 (ja) 2010-08-10 2010-08-10 半導体装置の製造方法および半導体装置
JP2010-179468 2010-08-10
PCT/JP2011/067847 WO2012020689A1 (ja) 2010-08-10 2011-08-04 半導体装置の製造方法および半導体装置

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CN103081077A true CN103081077A (zh) 2013-05-01

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US (1) US20130140700A1 (https=)
JP (1) JP5419167B2 (https=)
CN (1) CN103081077A (https=)
TW (1) TW201216411A (https=)
WO (1) WO2012020689A1 (https=)

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CN103426864A (zh) * 2013-08-26 2013-12-04 华进半导体封装先导技术研发中心有限公司 适用于转接板的tsv结构及其制备方法
CN105428311A (zh) * 2015-12-16 2016-03-23 华进半导体封装先导技术研发中心有限公司 Tsv背部露头的工艺方法
CN105990166A (zh) * 2015-02-27 2016-10-05 中芯国际集成电路制造(上海)有限公司 晶圆键合方法
CN106206509A (zh) * 2015-03-17 2016-12-07 矽品精密工业股份有限公司 电子封装件及其制法与基板结构
CN106935563A (zh) * 2015-12-31 2017-07-07 矽品精密工业股份有限公司 电子封装件及其制法与基板结构
CN107305840A (zh) * 2016-04-25 2017-10-31 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法和电子装置
CN108735744A (zh) * 2017-04-21 2018-11-02 联华电子股份有限公司 半导体存储装置以及其制作方法
CN109994422A (zh) * 2017-12-29 2019-07-09 江苏长电科技股份有限公司 Tsv封装结构及其制备方法

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JP2921677B2 (ja) 1997-07-28 1999-07-19 矢崎総業株式会社 カード式電気錠装置
US8940637B2 (en) 2012-07-05 2015-01-27 Globalfoundries Singapore Pte. Ltd. Method for forming through silicon via with wafer backside protection
US8963336B2 (en) 2012-08-03 2015-02-24 Samsung Electronics Co., Ltd. Semiconductor packages, methods of manufacturing the same, and semiconductor package structures including the same
US9034752B2 (en) * 2013-01-03 2015-05-19 Micron Technology, Inc. Methods of exposing conductive vias of semiconductor devices and associated structures
US10396012B2 (en) 2016-05-27 2019-08-27 International Business Machines Corporation Advanced through substrate via metallization in three dimensional semiconductor integration
US10312181B2 (en) 2016-05-27 2019-06-04 International Business Machines Corporation Advanced through substrate via metallization in three dimensional semiconductor integration
US9786605B1 (en) * 2016-05-27 2017-10-10 International Business Machines Corporation Advanced through substrate via metallization in three dimensional semiconductor integration
US9997452B1 (en) 2017-01-27 2018-06-12 Micron Technology, Inc. Forming conductive plugs for memory device
KR102757381B1 (ko) * 2020-10-13 2025-01-20 삼성전자주식회사 반도체 장치 제조 방법
CN115588619B (zh) * 2021-07-05 2025-07-18 长鑫存储技术有限公司 微凸块及其形成方法、芯片互连结构及方法
US20230352369A1 (en) * 2022-04-28 2023-11-02 Invensas Bonding Technologies, Inc. Through-substrate vias with metal plane layers and methods of manufacturing the same

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JP2005310817A (ja) * 2004-04-16 2005-11-04 Seiko Epson Corp 半導体装置の製造方法、回路基板、並びに電子機器
US20100038800A1 (en) * 2008-08-18 2010-02-18 Samsung Electronics Co., Ltd. Through-silicon via structures including conductive protective layers and methods of forming the same
CN101794717A (zh) * 2009-01-13 2010-08-04 台湾积体电路制造股份有限公司 堆叠集成芯片及其制造方法

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JP4606713B2 (ja) * 2002-10-17 2011-01-05 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP4454242B2 (ja) * 2003-03-25 2010-04-21 株式会社ルネサステクノロジ 半導体装置およびその製造方法
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KR20120048590A (ko) * 2009-07-31 2012-05-15 고쿠리츠 다이가쿠 호진 도호쿠 다이가쿠 반도체 장치, 반도체 장치의 제조 방법, 및 표시 장치

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JP2005310817A (ja) * 2004-04-16 2005-11-04 Seiko Epson Corp 半導体装置の製造方法、回路基板、並びに電子機器
US20100038800A1 (en) * 2008-08-18 2010-02-18 Samsung Electronics Co., Ltd. Through-silicon via structures including conductive protective layers and methods of forming the same
CN101794717A (zh) * 2009-01-13 2010-08-04 台湾积体电路制造股份有限公司 堆叠集成芯片及其制造方法

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103426864A (zh) * 2013-08-26 2013-12-04 华进半导体封装先导技术研发中心有限公司 适用于转接板的tsv结构及其制备方法
CN105990166A (zh) * 2015-02-27 2016-10-05 中芯国际集成电路制造(上海)有限公司 晶圆键合方法
CN105990166B (zh) * 2015-02-27 2018-12-21 中芯国际集成电路制造(上海)有限公司 晶圆键合方法
CN106206509B (zh) * 2015-03-17 2019-12-03 矽品精密工业股份有限公司 电子封装件及其制法与基板结构
CN106206509A (zh) * 2015-03-17 2016-12-07 矽品精密工业股份有限公司 电子封装件及其制法与基板结构
CN105428311A (zh) * 2015-12-16 2016-03-23 华进半导体封装先导技术研发中心有限公司 Tsv背部露头的工艺方法
CN106935563A (zh) * 2015-12-31 2017-07-07 矽品精密工业股份有限公司 电子封装件及其制法与基板结构
CN106935563B (zh) * 2015-12-31 2019-06-18 矽品精密工业股份有限公司 电子封装件及其制法与基板结构
CN107305840A (zh) * 2016-04-25 2017-10-31 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法和电子装置
CN107305840B (zh) * 2016-04-25 2020-05-12 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法和电子装置
CN108735744A (zh) * 2017-04-21 2018-11-02 联华电子股份有限公司 半导体存储装置以及其制作方法
US10672864B2 (en) 2017-04-21 2020-06-02 United Microelectronics Corp. Manufacturing method of semiconductor memory device
CN108735744B (zh) * 2017-04-21 2021-02-02 联华电子股份有限公司 半导体存储装置以及其制作方法
CN109994422A (zh) * 2017-12-29 2019-07-09 江苏长电科技股份有限公司 Tsv封装结构及其制备方法
CN109994422B (zh) * 2017-12-29 2021-10-19 江苏长电科技股份有限公司 Tsv封装结构及其制备方法

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JP5419167B2 (ja) 2014-02-19
JP2012038996A (ja) 2012-02-23
WO2012020689A1 (ja) 2012-02-16
TW201216411A (en) 2012-04-16
US20130140700A1 (en) 2013-06-06

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Application publication date: 20130501