TW201924011A - 具有實質上直的接觸輪廓的半導體結構 - Google Patents

具有實質上直的接觸輪廓的半導體結構 Download PDF

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TW201924011A
TW201924011A TW107102215A TW107102215A TW201924011A TW 201924011 A TW201924011 A TW 201924011A TW 107102215 A TW107102215 A TW 107102215A TW 107102215 A TW107102215 A TW 107102215A TW 201924011 A TW201924011 A TW 201924011A
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oxide layer
barrier material
interlayer dielectric
barrier
substantially straight
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羅納德 瑙曼
麥西爾斯 辛克
羅伯特 賽德
托拜斯 巴切維茲
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美商格芯（美國）集成電路科技有限公司
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Abstract

本發明係關於半導體結構，尤其關於一種具有實質上直的接觸輪廓的半導體結構及其製造方法。該結構包含一阻擋材料，其包括在一絕緣材料的一介面上之一上方氧化層；以及一互連接觸結構，其具有通過該阻擋材料中該氧化層的實質上直的輪廓。

Description

具有實質上直的接觸輪廓的半導體結構
本發明係關於半導體結構，尤其關於一種具有實質上直的接觸輪廓之半導體結構及其製造方法。
半導體裝置包含許多不同配線層，這些配線層形成於層間介電材料內，並且可包含配線結構、互連接觸、被動裝置以及主動裝置。該等互連接觸位於晶粒的不同配線層內，以連接至該等不同結構，例如不同配線結構等等。
在製造該等半導體裝置時，通常在一配線結構之上的該層間介電材料(例如一塊SiCOH材料)的底部表面上形成一黏貼層。不過，該黏貼層具有不同於該層間介電材料的蝕刻率，造成錐形的穿孔輪廓。換言之，當該層間介電材料以及該黏貼層的蝕刻率不同時，將以不同速率蝕刻這些材料，造成該黏貼層之內的錐形輪廓。接著，該錐形穿孔輪廓造成具有錐形輪廓的互連接觸。該等互連接觸的此錐形輪廓導致電效能問題，包含在例如銅這類金屬材料內形成空隙，以及依時性閘極氧化層崩潰(TDDB)。
這些不同材料的蝕刻也是已知的難以控制，因為不可能一致地量測黏貼層的厚度。並且該黏貼層之不同厚度將產生不同的錐形穿孔輪廓。
在本發明的一態樣中，一種結構包括：一阻擋材料，其包括在一絕緣材料的一介面上之一上方氧化層；以及一互連接觸結構，其具有通過該阻擋材料中該氧化層的實質上直的輪廓。
在本發明的一態樣中，一種結構包括：一配線層，其形成於一絕緣體材料內；一阻擋材料，其包括由氧化材料構成的一上方表面；一層間介電材料，其直接位於該上方表面上；以及一接觸，其通過該阻擋材料、氧化材料以及該層間介電材料延伸至該配線層，該接觸在該氧化材料之內具有實質上直的輪廓。
在本發明的一態樣中，一種方法包括：在一配線結構之上形成一阻擋材料；將該阻擋材料氧化，以形成一上方氧化層；在該氧化層之上形成一層間介電材料；蝕刻一穿孔進入該層間介電材料、該氧化層以及該阻擋材料來露出該配線結構，該穿孔具有一實質上直的穿孔輪廓貫穿該氧化層；以及在該穿孔之內形成一接觸，該接觸具有一實質上直的輪廓貫穿該氧化層。
10‧‧‧結構
12‧‧‧配線結構
14‧‧‧絕緣體材料
16‧‧‧阻擋材料
18‧‧‧氧化層
20‧‧‧層間介電材料
22‧‧‧硬光罩
24‧‧‧硬光罩
26‧‧‧穿孔
28‧‧‧直的輪廓
30‧‧‧互連接觸
利用本發明示範具體實施例的非限制性範例，參考提及的許多圖式，從以下實施方式當中說明本發明。
圖1顯示根據本發明態樣的一結構與各別製程。
圖2顯示根據本發明態樣的其他部件之間具有實質上直的輪廓的一穿孔與各別製程。
圖3顯示根據本發明態樣的其他部件之間具有實質上直的輪廓的一互連接觸與各別製程。
本發明係關於半導體結構，尤其關於一種具有實質上直的接觸輪廓之半導體結構及其製造方法。更具體而言，本發明在一層間介電材料底下、一阻擋層中的一氧化膜之內提供一實質上直的或垂直的互連接觸輪廓。有利的是，通過使用該氧化膜，本發明提供一更能夠控制的穿孔蝕刻處理，產生改善的互連接觸電參數值，例如空隙以及依時性閘極氧化層崩潰(TDDB)減少。
在具體實施例內，提供氧處理至一BLoK層的上方表面，例如低k介電絕緣體材料。此氧處理將改善一層間介電材料與該BLoK層之間該介面上的錐形控制，例如蝕刻。也就是說，通過提供氧處理，BLoK層的氧化層將具有與層間介電層相似的蝕刻率。該結果穿孔輪廓將依序在該等兩材料之間的該介面上具有直的或實質上直的輪廓，例如相對於水平介電表面量測大體上90度，如該氧化層與該層間介電層將具有類似蝕刻率。此外，通過實作本文所述的該等處理，可消除形成於該層間介電層底部上，通常在該蝕刻處理期間導致一錐形穿孔輪廓的該黏貼層。
本發明的結構可用許多不同工具以許多方式來製造。然而一般來說，該等方法與工具係用來形成尺寸為微米與奈米等級的結構。用來製造本發明結構的該等方法，即技術，已採用積體電路(Integrated circuit，IC)技術，例如：該結構可建立在晶圓上，並且通過在晶圓頂部上以光微影蝕刻處理來製作圖案的材料膜來實現。尤其是，該結構的製造使用三種基本構件：(i)將材料薄膜沉積在一基材上，(ii)利用光微影蝕刻成像將一圖案化光罩施加於該等薄膜頂端上，以及(iii)依照該光罩選擇性地蝕刻該等薄膜。
圖1顯示根據本發明態樣的一結構與各別製程。尤其是，結構10包含形成於一絕緣體材料14內的一配線結構12。在具體實施例內，絕緣體材料14可為氧化物型材料。金屬配線結構12可由銅材料形成，例 如使用傳統光微影、蝕刻以及沉積處理。
例如：為了形成配線結構12，絕緣體材料14之上形成的一光阻暴露於能量(光線)之下，以形成一圖案(開口)。使用選擇性化學的蝕刻處理，例如反應離子蝕刻(Reactive ion etching，RIE)，將用來在絕緣體材料14內形成一或多個溝渠貫穿該光阻的開口。然後可用傳統氧氣灰化處理或其他已知剝離劑(stripants)移除該光阻。緊接在該光阻移除之後，可用任何傳統沉積處理，例如電鍍處理，沉積該導電材料。利用傳統化學機械研磨(Chemical mechanical polishing，CMP)處理，可移除絕緣體材料14表面上的任何殘留材料。
請再參閱圖1，在絕緣體材料14與配線結構12之上形成一阻擋材料16。在具體實施例內，阻擋材料16為一低k介電層，例如氮化物材料。在更特定具體實施例內，阻擋材料16可為一NBLoK〔NBLoK為應用材料公司(Applied Materials,Inc.)的商標〕，其為氮摻雜碳化矽材料。在具體實施例內，通過任何傳統沉積處理，例如化學氣相沉積(Chemical vapor deposition，CVD)處理，可根據該技術節點，沉積阻擋材料16至一特定厚度。藉由非限制範例，該阻擋層的厚度以及該氧化層的厚度應平衡，如此該剩餘阻擋厚度仍舊足夠當成擴散屏障。
在具體實施例內，阻擋材料16經歷氧處理，以形成一氧化層18。在具體實施例內，氧化層18可在該阻擋材料的上方表面上；更具體而言，根據該技術節點，可延伸大約5nm至大約25nm；不過在本文內也提供其他厚度。在更特定範例內，氧化層18可為阻擋材料16的厚度之大約20%至大約30%。在一個特定具體實施例內，對於35nm厚的阻擋材料16，氧化層18的厚度可為大約5nm。
該氧處理可以在氧氣氛中提供。該氧氣氛可為例如CVD室中載流氣體內的O2、NO2或CO2。例如：使用與該沉積處理相同的CVD室，在該沉積處理開始之後可提供該氧處理。例如：可在阻擋材料16的沉積處 理開始之後或結束時提供該氧化處理。因此，可在原位提供該氧化。或者，在外部工具內或該沉積室之內，可在層間介電材料的沉積之前提供該氧處理，例如SiCOH沉積之前的氧前置處理。作為例子，在沉積處理之後，可以使用遠端電漿工具來提供氧處理。在具體實施例內，該氧處理不應影響底下的金屬部件，例如配線結構12。
仍參閱圖1，一層間介電材料20沉積在阻擋材料16之上，在更特定的具體實施例內，層間介電材料20可為使用傳統毯覆沉積處理(例如CVD)直接沉積在氧化層18上的塊體SiCOH。據此，在此後者實作中，該氧處理程序發生於層間介電材料20的沉積之前。在具體實施例內，精通技術人士應該了解，層間介電材料20與氧化層18的蝕刻率類似，硬光罩22、24的堆疊沉積在層間介電材料20上。在具體實施例內，作為範例，硬光罩22為一ILD(Interlevel dielectric，層間介電)硬光罩22並且硬光罩24為一TiN硬光罩。
圖2顯示圖1中該結構之內形成的一穿孔26。在具體實施例內，精通技術人士應了解，穿孔26可通過傳統雙鑲嵌或單鑲嵌處理形成，使得在此不需要進一步解釋。因層間介電材料20與氧化層18的蝕刻率具有實質上相同的蝕刻率，氧化層18之內形成的該穿孔部分將具有實質上直的輪廓28(不管該氧化層的厚度)。在具體實施例內，實質上直的輪廓28表示相對於該介電材料或底下配線結構12的該水平表面量測大體上90度。該蝕刻處理可使用傳統蝕刻循環(例如RIE處理)來執行，一起蝕刻層間介電材料20與氧化層18，來在其他層之間露出底下配線結構12。
圖3顯示穿孔26內所形成在其他部件之間具有實質上直的輪廓的一互連接觸30。在該互連材料沉積之前，利用已知的剝離處理可移除該等硬光罩。通過傳統沉積處理，接著例如化學機械研磨(CMP)，在該穿孔之內將形成互連接觸30。在具體實施例內，鎢的沉積可為一CVD處理，鋁的沉積可為一電漿氣相沉積(Plasma vapor deposition，PVD)處理並且其他 金屬或金屬合金材料可由一電鍍處理來沉積。該直的輪廓是由於該互連材料以直的輪廓28沉積在該穿孔內的事實。
上述該(等)方法用於積體電路晶片的製造。結果積體電路晶片可由製造廠以原始晶圓形式(也就是具有多個未封裝晶片的單一晶圓)、當成裸晶粒或已封裝形式來散佈。在後者案例中，晶片固定在單晶片封裝內(像是塑膠載體，具有黏貼至主機板或其他更高層載體的導線)或固定在多晶片封裝內(像是一或兩表面都具有表面互連或內嵌互連的陶瓷載體)。然後在任何案例中，晶片與其他晶片、離散電路元件及/或其他信號處理裝置整合成為以下任一者的一部分：(a)中間產品，像是主機板，或(b)最終產品。該最終產品可為包含積體電路晶片的任何產品，範圍從玩具與其他低階應用到具有顯示器、鍵盤或其它輸入裝置以及中央處理器的進階電腦產品。
本發明許多具體實施例的描述已經為了例示而呈現，但不欲為窮盡性或將本發明限制在所揭示之具體實施例中。在不脫離所描述具體實施例之範疇與精神的前提下，所屬技術領域中具有通常知識者將瞭解許多修正例以及變化例。本文內使用的術語係經選擇，以最佳解釋具體實施例的原理、市場上所發現技術的實際應用或技術改進，或可讓其他所屬技術領域中具有通常知識者能理解本文所揭示的具體實施例。

Claims (20)

  1. 一種結構，包括：一阻擋材料，其包括在一絕緣材料的一介面上之一上方氧化層；以及一互連接觸結構，其具有通過該阻擋材料中該氧化層的實質上直的輪廓。
  2. 如申請專利範圍第1項之結構，其中該互連接觸結構延伸通過該絕緣材料。
  3. 如申請專利範圍第2項之結構，其中該絕緣材料為SiCOH構成的一介電材料。
  4. 如申請專利範圍第1項之結構，其中該氧化層的厚度大約是該阻擋材料厚度的大約20%至30%。
  5. 如申請專利範圍第1項之結構，其中該互連接觸結構延伸至一底下配線結構。
  6. 如申請專利範圍第1項之結構，其中該絕緣材料與該氧化層具有實質上相同的蝕刻率。
  7. 如申請專利範圍第6項之結構，其中該阻擋材料由氮化物材料構成。
  8. 如申請專利範圍第6項之結構，其中該阻擋材料由氮摻雜碳化矽構成。
  9. 如申請專利範圍第8項之結構，其中該絕緣層為塊體SiCOH。
  10. 一種結構，包括：一配線層，其形成於一絕緣體材料內；一阻擋材料，其包括由氧化材料構成的一上方表面；一層間介電材料，其直接位於該上方表面上；以及一接觸，其通過該阻擋材料、氧化材料以及該層間介電材料延伸至該配線層，該接觸在該氧化材料之內具有實質上直的輪廓。
  11. 如申請專利範圍第10項之結構，其中該層間介電材料由塊體SiCOH構成。
  12. 如申請專利範圍第10項之結構，其中該氧化材料的厚度大約是該阻擋材料厚度的大約20%至30%。
  13. 如申請專利範圍第10項之結構，其中該層間介電材料與該氧化材料具有實質上相同的蝕刻率。
  14. 如申請專利範圍第13項之結構，其中該阻擋材料由氮化物材料構成。
  15. 如申請專利範圍第14項之結構，其中該阻擋材料由氮摻雜碳化矽構成。
  16. 如申請專利範圍第14項之結構，其中該氧化材料具有之厚度大約12nm至25nm。
  17. 一種方法，包括：在一配線結構之上形成一阻擋材料；將該阻擋材料氧化，以形成一上方氧化層；在該氧化層之上形成一層間介電材料；蝕刻一穿孔進入該層間介電材料、該氧化層以及該阻擋材料來露出該配線結構，該穿孔具有一實質上直的穿孔輪廓貫穿該氧化層；以及在該穿孔之內形成一接觸，該接觸具有一實質上直的輪廓貫穿該氧化層。
  18. 如申請專利範圍第17項之方法，其中該層間介電材料與該氧化層具有實質上相同的蝕刻輪廓。
  19. 如申請專利範圍第18項之方法，其中在用於形成該阻擋材料的一沉積室內執行氧化。
  20. 如申請專利範圍第18項之方法，其中利用一電漿處理來執行該氧化。
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