WO2011151901A1 - 半導体装置 - Google Patents
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- WO2011151901A1 WO2011151901A1 PCT/JP2010/059362 JP2010059362W WO2011151901A1 WO 2011151901 A1 WO2011151901 A1 WO 2011151901A1 JP 2010059362 W JP2010059362 W JP 2010059362W WO 2011151901 A1 WO2011151901 A1 WO 2011151901A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/8213—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using SiC technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66143—Schottky diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
Definitions
- the present invention relates to a semiconductor device, and particularly to a technique effective when applied to a junction barrier Schottky diode using silicon carbide.
- Silicon carbide semiconductor (SiC) is promising as a power device because it has a large band gap and a dielectric breakdown electric field about one digit larger than silicon semiconductor.
- a Schottky diode which is a unipolar rectifier element that operates only by majority carriers, is effective as a power module loss reduction technique because a reverse current (recovery current) does not flow during switching operation due to the device configuration.
- the rectifying action of the Schottky diode is made by a Schottky barrier caused by the difference between the work function of the metal and the electron affinity of the semiconductor.
- a metal material having a high Schottky barrier height By using a metal material having a high Schottky barrier height, the reverse leakage current can be reduced, but at the same time, the forward rise voltage is increased.
- a metal material having a low Schottky barrier height the forward rise voltage can be lowered, but at the same time, the reverse leakage current is increased.
- a Schottky interface As a structure that suppresses reverse leakage current by relaxing an electric field applied to a metal / semiconductor interface (hereinafter referred to as a Schottky interface) when a reverse voltage is applied, a junction in which a plurality of junction barriers are provided at the Schottky interface.
- a structure called a barrier (Schottky diode) (hereinafter referred to as a JBS diode) has been proposed.
- a depletion layer extends from the junction barrier portion, and the electric field at the Schottky interface can be relaxed. This structure is illustrated in FIG. In FIG.
- Patent Document 1 a structure in which the impurity concentration in a region surrounded by a junction barrier is increased is disclosed (Patent Document 1). This structure is illustrated in FIG. A difference from FIG. 19 is that an n-type semiconductor region 4 having an impurity concentration higher than that of the n ⁇ drift layer is provided. With this structure, the resistance of the junction barrier forming region can be lowered.
- the non-defective product ratio Y (in this case, the probability that a chip can be produced without abnormality in the reverse direction characteristic) can be considered as a Poisson distribution and is expressed by the following equation.
- Y exp (-DA)
- D Density of foreign matters and defects that cause abnormal reverse characteristics
- A Area of Schottky interface
- FIG. 21 shows the relationship between the non-defective product ratio Y and the area A of the Schottky interface shown in Equation 1 with respect to the defect density D. The plot is shown.
- a value obtained by multiplying this value by the non-defective rate corresponding to the total area of the junction barrier region used in the JBS structure and the electric field concentration relaxation structure formed around the chip can be considered as the non-defective rate of the JBS diode.
- the Schottky diode is sensitive to the Schottky interface characteristics, it is very difficult to manufacture a large-area, high-voltage resistant chip.
- it is considered effective to increase the junction barrier region in the JBS structure and reduce the Schottky interface region as much as possible.
- the current does not spread sufficiently under the junction barrier region during forward operation, and the on-voltage increases.
- the problem to be solved is that the on-voltage increases because the current does not spread sufficiently under the junction barrier region during the forward operation of the JBS diode.
- n region having a relatively higher concentration than the n ⁇ -type drift layer concentration is provided below the junction barrier region. Representative inventions of the present invention are listed below.
- the present invention includes a first conductivity type silicon carbide substrate, a first conductivity type drift layer formed on the silicon carbide substrate and having a first impurity concentration, and formed on a surface in the drift layer at predetermined intervals.
- a plurality of first semiconductor regions having a second conductivity type opposite to the first conductivity type, a Schottky electrode that is Schottky connected to the drift layer, an ohmic electrode that is ohmically connected to the back surface of the silicon carbide substrate, and a first semiconductor
- a semiconductor device comprising: a second semiconductor region of a first conductivity type having a second impurity concentration higher than the first impurity concentration in a region between the region and the silicon carbide substrate.
- Another embodiment of the present invention is a first conductive type silicon carbide substrate, a first conductive type first semiconductor layer formed on the silicon carbide substrate and having a first impurity concentration, and formed on the first semiconductor layer.
- a first conductivity type second semiconductor layer having a second impurity concentration higher than the first impurity concentration and opposite to the first conductivity type formed at a predetermined interval on the surface in the second semiconductor layer.
- a semiconductor device comprising a plurality of first semiconductor regions having a second conductivity type, a Schottky electrode that is in Schottky connection with the second semiconductor layer, and an ohmic electrode that is in ohmic connection with the back surface of the silicon carbide substrate.
- Another embodiment of the present invention is a first conductivity type silicon carbide substrate, a first conductivity type first semiconductor layer formed on the silicon carbide substrate and having a first impurity concentration, and formed on the first semiconductor layer.
- a first conductivity type second semiconductor layer having a second impurity concentration higher than the first impurity concentration and opposite to the first conductivity type formed at a predetermined interval on the surface in the second semiconductor layer.
- the semiconductor device includes a region, a Schottky electrode that is Schottky-connected to the second semiconductor layer, and an ohmic electrode that is ohmic-connected to the back surface of the silicon carbide substrate.
- the semiconductor device of the present invention has an n region having a lower resistance than the n ⁇ -type drift layer below the junction barrier region, so the current spreads to the lower portion of the junction barrier region, so The rise can be suppressed.
- FIG. 23 is an explanatory diagram showing a cross-sectional structure of the semiconductor device according to the first embodiment of the present invention, and is a cross-sectional view taken along the line A-A ′ of FIG. 22. It is sectional structure explanatory drawing in a manufacturing process which shows an example of the manufacturing process of the semiconductor device in Embodiment 1 of this invention.
- FIG. 3 is an explanatory diagram of a cross-sectional structure in the manufacturing process of the semiconductor device, following FIG. 2; It is explanatory drawing which shows the relationship between the raise rate of drift layer resistance, and the ratio of a Schottky interface. It is explanatory drawing which shows the relationship between the raise rate of drift layer resistance, and junction barrier area
- FIG. 23 is an explanatory diagram showing a cross-sectional structure of a semiconductor device according to a second embodiment of the present invention, which is a cross-sectional view taken along the line BB ′ of FIG. 22, and (a) is a case where a Schottky electrode does not run over the insulating film 10; (B), It is sectional drawing in case a Schottky electrode runs on the insulating film 10.
- FIG. It is explanatory drawing which shows the cross-section of the semiconductor device in Embodiment 3 of this invention.
- FIG. 12 is an explanatory diagram of a cross-sectional structure during the manufacturing process of the semiconductor device following FIG. 11; It is explanatory drawing which shows the cross-section of the semiconductor device in Embodiment 4 of this invention. It is sectional structure explanatory drawing in a manufacturing process which shows an example of the manufacturing process of the semiconductor device in Embodiment 4 of this invention.
- FIG. 15 is an explanatory diagram of a cross-sectional structure in the manufacturing process of the semiconductor device, following FIG.
- FIG. 14 It is explanatory drawing which shows the cross-section of the semiconductor device in Embodiment 5 of this invention. It is sectional structure explanatory drawing in a manufacturing process which shows an example of the manufacturing process of the semiconductor device in Embodiment 5 of this invention.
- FIG. 17 is an explanatory diagram of a cross-sectional structure during the manufacturing process of the semiconductor device following FIG. 16; It is explanatory drawing which shows the cross-section of the conventional semiconductor device. It is explanatory drawing which shows the cross-section of the conventional semiconductor device. It is explanatory drawing which shows the relationship between the yield rate and the area of a Schottky interface. It is explanatory drawing which shows the upper surface structure of the semiconductor device in Embodiment 1 of this invention.
- FIG. 1 is an explanatory view showing a cross-sectional structure of a semiconductor device according to the first embodiment of the present invention.
- the semiconductor device according to the first embodiment includes a first conductivity type low impurity concentration (n ⁇ type) SiC drift formed on a first conductivity type (n type) high impurity concentration (n + type) SiC substrate 1.
- a layer 2 a second conductivity type (p-type) p-type semiconductor region 3, a Schottky electrode 5 provided on the surface of the n ⁇ drift layer 2, an ohmic electrode 6 provided on the back surface of the n + SiC substrate 1, It is a JBS diode provided with.
- this diode is provided in the region below the p-type semiconductor region 3 and between the SiC substrate and the n-type semiconductor region 4 having a higher impurity concentration than the n ⁇ drift layer 2 (n ⁇ SiC semiconductor layer 8). It has. For this reason, the current can sufficiently spread under the p-type semiconductor region 3 during the forward operation, and an increase in on-voltage can be suppressed.
- the n-type semiconductor region 4 below the p-type semiconductor region 3 is disposed in contact with the p-type semiconductor region 3, and the n-type semiconductor region 4 is the surface of the n ⁇ drift layer 2. Since it is formed as a whole, it also exists in the region between the p-type semiconductor regions 3. Note that W represents the thickness of the drift layer, S represents the interval between a plurality of p-type semiconductor regions 3 arranged, and P represents the width of the p-type semiconductor region 3.
- FIGS. 2 to 3 are cross-sectional structure explanatory views during the manufacturing process showing an example of the manufacturing process of the first embodiment.
- n of low impurity concentration on the n + SiC substrate 1 as shown in FIG. 2 - the SiC layer 8, n - n semiconductor region of higher impurity concentration than SiC layer 8 - relatively n on the SiC layer 8 A SiC substrate formed by epitaxial growth of 4 is prepared.
- the laminated film of the n ⁇ SiC layer 8 and the n semiconductor region 4 is defined as the n ⁇ drift layer 2.
- the impurity concentration of the n + SiC substrate 1 is in the range of about 1 ⁇ 10 18 to 1 ⁇ 10 19 cm ⁇ 3 .
- the (0001) plane, (000-1) plane, (11-20) plane, etc. are often used as the main surface of the SiC substrate, the present invention has the effect regardless of the selection of these main surfaces of the SiC substrate. Can be played.
- the specifications of the n ⁇ SiC layer 8 on the n + SiC substrate 1 vary depending on the set breakdown voltage specification, but the impurity concentration is 1 ⁇ 10 15 to 4 ⁇ 10 16 cm ⁇ with the same conductivity type as the substrate.
- the thickness is about 3 and the thickness is about 3 to 80 ⁇ m.
- a pattern is formed on the mask material 7 by usual lithography and dry etching.
- the mask material 7 uses SiO 2 formed by a CVD (Chemical Vapor Deposition) method. Further, the mask material 7 is usually processed into a striped pattern, island pattern, polygonal pattern, lattice pattern, etc., but the present invention is not limited as long as it is patterned with a certain width and interval. The effect can be achieved even in the shape.
- a p-type semiconductor region 3 is formed on the surface of the n ⁇ drift layer 2 by implantation of ions 12.
- the impurity concentration of the p-type semiconductor region 3 is about 10 18 to 10 20 cm ⁇ 3 and the junction depth is about 0.3 to 2.0 ⁇ m.
- Al (aluminum) or B (boron) is used as the p-type dopant.
- Al aluminum
- Al is used as a dopant
- multi-stage implantation is performed with an acceleration energy of 35 to 145 keV with a total dose of 1.8 ⁇ 10 14 cm ⁇ 2, and the impurity concentration in the vicinity of the surface is about 9 ⁇ 10 18 cm ⁇ 3 .
- the p-type semiconductor region 3 was formed so as to have a depth of about 0.55 to 0.7 ⁇ m.
- a guard ring 9 made of p-type impurities was formed on the outer periphery of the chip in the same procedure as the formation of the p-type semiconductor region 3 (see FIG. 22). Further, normal annealing for implanted impurities is performed to form an ohmic electrode 6 on the back surface of the n + SiC substrate and a Schottky electrode 5 on the surface of the n ⁇ drift layer 2, and the Schottky electrode 5 is patterned to a desired size. By processing, the main part of the semiconductor device of the present invention shown in FIG. 1 is completed.
- FIG. 22 is an explanatory view showing the top structure of the first embodiment. This top view shows the arrangement relationship of the main parts of the semiconductor device, and does not accurately show the positions and dimensions of all layers. Further, some layers such as electrodes are not shown in order to make the arrangement relationship easy to see.
- a striped pattern in which the p-type semiconductor regions 3 are arranged in a line at regular intervals is shown as the JBS structure.
- the p-type semiconductor region 9 is formed so as to surround the plurality of p-type semiconductor regions 3. 1 is a cross-sectional view taken along the line AA ′ of FIG. Although only the main part of the diode has been described here, an electric field concentration mitigation structure such as FLR (Field Limiting Ring) and JTE (Junction Termination Extension) and a channel stopper, which are usually formed around the chip, are shown in FIG. Before or after the formation of the p-type semiconductor region 3 shown, it is formed using conventional lithography, dry etching, and ion implantation.
- FLR Field Limiting Ring
- JTE Joint Termination Extension
- the SiC substrate in which the n semiconductor region 4 is formed by epitaxial growth is used.
- the n semiconductor region 4 may be formed by performing multistage ion implantation of n-type impurities into the n ⁇ drift layer 2.
- the n-type impurity N (nitrogen) or P (phosphorus) is generally used, but any other element can be used as long as it contributes as an n-type dopant.
- the region where the n-type impurity is ion-implanted may be the entire surface of the SiC substrate, or may be limited to the region where the Schottky electrode is formed.
- the ion implantation of the n-type impurity may be performed before the implantation impurity activation annealing step, and the n semiconductor region 4 may be formed after the step of forming the p-type semiconductor region 3 of FIG. .
- SiO 2 is applied to the mask material.
- a silicon nitride film or a resist material may be used, and any other material can be used as long as it is a material used as a mask during ion implantation.
- the back surface and front surface electrodes are formed immediately after the implantation impurity activation annealing.
- an oxidation treatment is performed to perform n ⁇ . You may perform the sacrificial oxidation process which removes the damage layer which entered the surface of the drift layer 2.
- the back surface and front surface electrodes are formed immediately after the implantation impurity activation annealing, but the surface of the n ⁇ drift layer 2 is protected by a CVD method such as SiO 2.
- a film may be formed to protect the surface of the n ⁇ drift layer 2.
- the surface protective film may be formed after performing the above-described sacrificial oxidation step.
- n diode having a JBS structure - drift layer resistance R Schottky diodes the n - drift layer resistance R SBD, the width of the p-type semiconductor region 3 in the JBS structure P, and spacing S, n-drift
- the thickness of layer 2 is defined as W.
- the n ⁇ drift layer 2 shows two types of specifications with different breakdown voltages.
- One is an n-drift layer having an impurity concentration of 1 ⁇ 10 16 cm ⁇ 3 and a thickness of 5 ⁇ m assuming a breakdown voltage of 600 V, and the other is an impurity concentration of 3 ⁇ 10 15 cm assuming a breakdown voltage of 3.3 kV. -3 , an n-drift layer having a thickness of 30 ⁇ m.
- FIG. 4 shows the relationship between the resistance increase rate R / R SBD of the conventional JBS diode and the Schottky interface ratio S / (S + P).
- the interval S between the p + junction regions is determined from the viewpoint of sufficiently relaxing the Schottky electrode interface electric field when the reverse voltage is applied and reducing the reverse leakage current.
- S 2 ⁇ m
- 3 ⁇ m is set as a standard dimension.
- the size of S 6 ⁇ m was also calculated in the specification of the n ⁇ drift layer 2 with a withstand voltage of 600 V.
- the specification of S considered the relaxation effect of the Schottky interface electric field. Not a value.
- the resistance increase rate R / R SBD increases as the ratio of the Schottky interface decreases.
- the sensitivity of the drift layer resistance increase rate with respect to the ratio of the Schottky interface differs depending on the specifications of the n ⁇ drift layer 2 and the size of the interval S.
- the current does not sufficiently spread to the lower part of the p-type semiconductor region, and the point at which the rate of increase in resistance R / R SBD rapidly increases is not determined only by the ratio of the width P and the interval S of the p-type semiconductor region. Yes.
- FIG. 5 shows the relationship between the resistance increase rate R / R SBD of the conventional JBS diode and the ratio W / P of the junction region width to the drift layer thickness.
- the resistance increase rate R / R SBD gradually increases at a substantially constant rate.
- the resistance increase rate R / R It can be seen that the SBD increases rapidly. This is because the factor that determines the increase in resistance of the JBS structure is determined by the width P of the p-type semiconductor region and the thickness W of the drift layer.
- the current reaches the lower portion of the p-type semiconductor region 3. It indicates that it will not spread sufficiently.
- FIG. 6 shows an example of the effect when the structure of the first embodiment is applied.
- the n-type semiconductor region 4 is indicated as a current spreading layer, but the same layer is shown. That is, what is indicated as a current spreading layer is data when the n-type semiconductor region 4 according to the present invention is provided, and what is not indicated is a conventional SBD.
- the specifications of the n ⁇ drift layer 2 assuming a breakdown voltage of 600 V are that the n ⁇ SiC layer 8 is 5 ⁇ m thick with an impurity concentration of 1 ⁇ 10 16 cm ⁇ 3 , and the n-type semiconductor region 4 is 2 ⁇ m with 3 ⁇ 10 16 cm ⁇ 3 . It is a laminated film.
- the specifications of the n ⁇ drift layer 2 assuming a breakdown voltage of 3.3 kV are as follows : the n ⁇ SiC layer 8 is 3 ⁇ 10 15 cm ⁇ 3 of 30 ⁇ m, and the n-type semiconductor region 4 is 1.5 ⁇ 10 16 cm ⁇ 3 .
- the laminated film is 2 ⁇ m.
- the rate of increase in resistance of the n ⁇ drift layer 2 to which the n-type semiconductor region 4 is added is standardized by the resistance R SBD of the Schottky diode of the n ⁇ drift layer 2 when the n-type semiconductor region 4 is not present.
- the resistance increase rate R / R SBD when W / P is large differs depending on the specifications of the n ⁇ drift layer 2 due to the impurity concentration and thickness of the laminated film.
- the increase in resistance is suppressed as compared with the conventional structure. That is, it can be seen that when the n-type semiconductor region 4 according to the present invention is provided, the effect of suppressing an increase in resistance becomes remarkable particularly in a design where P is wider than 1/4 of W.
- P is wider than 1/4 of W.
- FIG. 7 shows an example of the effect when the structure of the first embodiment is applied.
- the resistance increase rate of the n ⁇ drift layer 2 to which the n-type semiconductor region 4 is added is equal to that of the same n ⁇ drift layer 2.
- the case is shown in which the Schottky diode resistance R SBD of the structure is normalized.
- the concentration and film thickness of the n-type semiconductor region 4 can be set to arbitrary values.
- the concentration is set in a range where the concentration is higher than that of the n ⁇ SiC layer 8 and the reverse characteristics can exhibit a desired breakdown voltage.
- the film thickness may be thin or thick.
- S is set to 3 ⁇ m.
- the interval S may be set to be narrow as long as the ON voltage does not increase excessively during forward operation.
- the n type semiconductor region 4 having a relatively high impurity concentration is provided on the surface of the n ⁇ drift layer 2, it can be set to be much narrower than the normal interval S.
- FIG. 8 is a cross-sectional view taken along the line BB ′ of FIG. 22, showing a cross-sectional structure near the end of the Schottky electrode 5 of the JBS diode. As shown in FIG.
- the structure of the Schottky electrode 5 end is as follows: (a) Schottky electrode 5 is formed on n ⁇ -type SiC drift layer 2, and p-type semiconductor region (guard ring) 9 is (B) the insulating film 10 formed on the n ⁇ -type SiC drift layer 2 is processed by ordinary lithography and dry etching or wet etching, and the Schottky electrode 5 is processed. In general, a structure is used in which an electrode is processed so that an end is formed on the insulating film 10 above the p-type semiconductor region (guard ring) 9.
- the p-type semiconductor region (guard ring) 9 is provided so that the electric field does not concentrate at the end of the Schottky electrode 5 or at the boundary between the electrode and the insulating film 10. In any case, the end portion of the Schottky electrode or the boundary portion between the Schottky electrode and the insulating film 10 (end portion of the Schottky electrode) is disposed on the p-type semiconductor region.
- the p-type semiconductor region (guard ring) 9 is shown as a region formed in a separate process from the p-type semiconductor region 3, but may be formed in the same step as the p-type semiconductor region 3.
- the current sufficiently spreads under the p-type semiconductor region (guard ring) 9 during forward operation.
- an increase in on-voltage in the vicinity of the end of the Schottky electrode 5 can be suppressed.
- SiO 2 is applied to the insulating film 10, but any material having general insulating properties may be used.
- a silicon nitride film, a polyimide, or a laminate made of these different insulating films is used. It may be a membrane.
- FIG. 9 is an explanatory diagram showing a cross-sectional structure of the semiconductor device according to the third embodiment of the present invention.
- FIG. 10 is an explanatory diagram of a cross-sectional structure of another semiconductor device according to the third embodiment.
- the difference from FIG. 9 is that the n-type semiconductor region 4 has the same width as the p-type semiconductor region 3. This difference can be realized by a slight change in the manufacturing process.
- the difference between the third embodiment and the first embodiment is that the n-type semiconductor region 4 is formed only in the lower region of the p-type semiconductor region 3, and the manufacturing process is different. However, the effect is essentially the same as that shown in the first embodiment although the degree is different.
- FIG. 11 to FIG. 12 are cross-sectional structure explanatory diagrams in the manufacturing process showing an example of the manufacturing process of the third embodiment.
- a SiC substrate in which an n ⁇ drift layer 2 having a low impurity concentration is formed on an n + SiC substrate 1 by epitaxial growth is prepared in the same procedure as in the first embodiment.
- the n + SiC substrate 1 and the n ⁇ drift layer 2 use the same impurity concentration and thickness specifications as those in the first embodiment.
- a pattern is formed on the mask material 7 by usual lithography and dry etching.
- the mask material 7 and its processing pattern are the same as those in the first embodiment.
- a p-type semiconductor region 3 is formed on the surface of the n ⁇ drift layer 2 by implantation of ions 12.
- the acceleration energy and the total dose amount at the time of ion implantation are the same as those in the first embodiment.
- the mask material 7 at the time of forming the p-type semiconductor region 3 is processed and reduced, and n-type impurity ions are implanted to form the n semiconductor region 4.
- the mask material 7 uses SiO 2 formed by the CVD method, diluted hydrofluoric acid is used for processing.
- the etching amount of the mask material 7 is not particularly limited, and it is sufficient that the width of the n-type semiconductor region 4 is wider than that of the p-type semiconductor region 3.
- the impurity concentration of the n-type semiconductor region 4 only needs to be relatively higher than the impurity concentration of the n ⁇ drift layer 2 and is set so that the peak impurity concentration is near the PN junction position below the p-type semiconductor region 3. .
- N nitrogen
- P phosphorus
- a multi-dose implantation is performed with an acceleration energy of 360 to 480 keV with a total dose of 1.8 ⁇ 10 12 cm ⁇ 2 so that the peak impurity concentration is about 7 ⁇ 10 16 cm ⁇ 3.
- An n-type semiconductor region 4 was formed. Further, in order to increase the width of the n-type semiconductor region 4 serving as the current spreading layer, multi-stage implantation may be performed with higher acceleration energy, for example, up to about 700 keV. It is necessary to determine the size of the PN junction leak when applying the reverse voltage.
- the semiconductor device of the present invention shown in FIG. 9 is completed by patterning the Schottky electrode 5 to a desired size.
- the electric field concentration relaxation structure usually formed around the chip is not limited to the conventional lithography and dry process before, during or after the manufacturing process shown in FIGS. It is formed using etching and ion implantation.
- the n-type semiconductor region 4 is formed after the p-type semiconductor region 3 is formed, but the formation order may be reversed. In that case, after the n-type semiconductor region 4 is formed, a mask material 7 is additionally deposited, and an etch-back process by a usual dry etching is performed, so that the p-type semiconductor region 3 having a narrower width than the n-type semiconductor region 4 is formed. A forming mask material 7 is formed.
- the n-type semiconductor region 4 is formed wider than the p-type semiconductor region 3, but may be formed with the same mask pattern. In this case, since the process of reworking the mask material 7 can be omitted, the process can be simplified.
- FIG. 10 illustrates a cross-sectional structure.
- the back and front electrodes are formed immediately after the implantation impurity activation annealing.
- the oxidation treatment is performed, and n ⁇ You may perform the sacrificial oxidation process which removes the damage layer which entered the surface of the drift layer 2.
- the back surface and front surface electrodes are formed immediately after the activation annealing of the implanted impurities.
- the surface of the n ⁇ drift layer 2 is protected by a CVD method such as SiO 2.
- a film may be formed to protect the surface of the n ⁇ drift layer 2.
- the surface protective film after forming the surface protective film, processing is performed so that only the region where the Schottky electrode is formed is opened. Further, the surface protective film may be formed after performing the above-described sacrificial oxidation step.
- FIG. 13 is an explanatory diagram showing a cross-sectional structure of the semiconductor device according to the fourth embodiment of the present invention.
- the difference from FIG. 9 shown in the third embodiment is that the n-type semiconductor region 4 is also arranged on the side surface of the p-type semiconductor region 3 and is formed up to the surface of the n ⁇ drift layer 2 to be Schottky connected. It is. It is arranged with a predetermined distance from adjacent n-type semiconductor regions.
- the effect is essentially the same as that shown in the first embodiment although the degree is different.
- FIG. 14 to FIG. 15 are cross-sectional structure explanatory diagrams in the manufacturing process showing an example of the manufacturing process of the fourth embodiment.
- the difference from the third embodiment is the ion implantation conditions when forming the n-type semiconductor region 4 in FIG.
- the n-type semiconductor region 4 is formed up to the surface of the n ⁇ drift layer 2.
- the SiC layer that becomes the n-type semiconductor region 4 and the SiC that becomes the p-type semiconductor region 3 There is a method in which a layer is epitaxially grown, and planarization polishing is performed up to the surface of the n ⁇ drift layer 2 by CMP (Chemical Mechanical Polishing).
- CMP Chemical Mechanical Polishing
- FIG. 16 is an explanatory diagram showing a cross-sectional structure of the semiconductor device according to the fifth embodiment of the present invention.
- the difference from FIG. 9 shown in the third embodiment is that the n-type semiconductor regions 4 are formed as one layer without being divided. That is, it is disposed between the p-type semiconductor region 3 and also between the Schottky electrode 5 and the SiC substrate 1. Further, it is arranged at a predetermined distance from the Schottky electrode 5.
- the effect is essentially the same as that shown in the first embodiment although the degree is different.
- FIG. 17 to FIG. 18 are cross-sectional structure explanatory views in the manufacturing process showing an example of the manufacturing process of the fifth embodiment.
- the difference from the third embodiment is the implantation region when forming the n-type semiconductor region 4 in FIG.
- the n-type semiconductor region 4 is formed by ion-implanting n-type impurities over the entire region where the JBS structure is to be formed.
- the present invention has been described using the first to fifth embodiments.
- the second embodiment has been described using the first embodiment, the second embodiment can also be applied to the third to fifth embodiments.
- the p-type semiconductor region 3 and the p-type semiconductor region 3 in FIG. The arrangement of the n-type semiconductor region 4 between the n-type semiconductor region 9 and the n-type semiconductor region 9 may be replaced with the arrangement of the n-type semiconductor regions 4 of the third to fifth embodiments.
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Abstract
Description
(数式)
Y=exp(-DA)
D:逆方向特性に異常をきたす異物や欠陥の密度
A:ショットキー界面の面積
図21に、数式1で示した良品率Yとショットキー界面の面積Aの関係を、欠陥密度Dに対してプロットしたものを示す。例えば、ショットキー界面の面積Aが0.1cm2のとき、D=1個/cm2の場合良品率Yは90%程度となるが、D=10個/cm2の場合Yは40%以下と大幅に減少することが分かる。この値に、JBS構造やチップ周辺に形成される電界集中緩和構造に用いられている接合障壁領域の総面積に対応する良品率を掛け合わせた値が、JBSダイオードの良品率と考えることができる。
図1は本発明の実施の形態1における半導体装置の断面構造を示す説明図である。本実施の形態1による半導体装置は、第1導電型(n型)の高不純物濃度(n+型)SiC基板1上に形成される第1導電型の低不純物濃度(n-型)SiCドリフト層2と、第2導電型(p型)のp型半導体領域3と、n-ドリフト層2表面に設けられたショットキー電極5と、n+SiC基板1裏面に設けられたオーミック電極6とを備えているJBSダイオードである。さらに、このダイオードは、p型半導体領域3の下側かつSiC基板との間の領域に、相対的にn-ドリフト層2(n-SiC半導体層8)より高い不純物濃度のn型半導体領域4を備えている。このため、順方向動作時においてp型半導体領域3の下部に十分に電流が広がることが可能で、オン電圧の上昇を抑えることができる。本実施の形態1では、p型半導体領域3の下側のn型半導体領域4は、p型半導体領域3と接触して配置され、また、n型半導体領域4はn-ドリフト層2の表面全体に形成されているため、p型半導体領域3の間の領域にも存在する。なお、Wはドリフト層の厚さを示し、Sは複数配置されたp型半導体領域3同士の間隔を示し、Pはp型半導体領域3の幅を示す。
実施の形態2では、実施の形態1についてショットキー電極5端近辺の構造について、さらにn型半導体領域4を設けた構造である。図8は、図22のB-B’切断面における断面図であり、JBSダイオードのショットキー電極5端近辺の断面構造を示している。図8に示しているように、ショットキー電極5端の構造としては、(a)n-型SiCドリフト層2上にショットキー電極5を形成し、p型半導体領域(ガードリング)9上で端部が形成されるように電極を加工する構造と、(b)n-型SiCドリフト層2上に形成した絶縁膜10を通例のリソグラフィとドライエッチングもしくはウェットエッチングにより加工し、ショットキー電極5を形成し、p型半導体領域(ガードリング)9の上部であり絶縁膜10上で端部が形成されるように電極を加工する構造が一般的に用いられる。ここでp型半導体領域(ガードリング)9は、ショットキー電極5端部、もしくは電極と絶縁膜10の境界部分に電界が集中しないように設けられている。いずれの場合でも、ショットキー電極の端部若しくはショットキー電極と絶縁膜10の境界部分(ショットキー電極の端部)は、このp型半導体領域上に配置されている。ここでは、p型半導体領域(ガードリング)9を、p型半導体領域3とは別工程で形成された領域として示しているが、p型半導体領域3と同一工程で形成しても良い。いずれの場合においても、p型半導体領域(ガードリング)9をn型半導体領域4内に形成することで、順方向動作時においてp型半導体領域(ガードリング)9の下部に十分に電流が広がることが可能であり、実施の形態1の効果と同様にショットキー電極5端近辺のオン電圧の上昇を抑えることができる。
図9は本発明の実施の形態3における半導体装置の断面構造を示す説明図である。また、図10に本実施の形態3における他の半導体装置の断面構造の説明図を示す。図9との違いは、n型半導体領域4がp型半導体領域3の幅と同じという点である。この違いは、製造工程における若干の変更によって実現することができる。本実施の形態3の実施の形態1との違いは、n型半導体領域4がp型半導体領域3の下部領域のみに形成されている点であり、製造工程が異なる。しかし、その効果は、程度の違いはあるが本質的に実施の形態1で示したものと同様である。
図13は本発明の実施の形態4における半導体装置の断面構造を示す説明図である。実施の形態3で示した図9との違いは、n型半導体領域4がp型半導体領域3の側面にも配置され、n-ドリフト層2の表面まで形成されてショットキー接続している点である。なお、隣接するn型半導体領域と所定の間隔が設けられて配置されている。しかし、その効果は、程度の違いはあるが本質的に実施の形態1で示したものと同様である。
図16は本発明の実施の形態5における半導体装置の断面構造を示す説明図である。実施の形態3で示した図9との違いは、n型半導体領域4がそれぞれ分断されずに、1つの層として形成されている点である。すなわち、p型半導体領域3の間であって、ショットキー電極5とSiC基板1の間にも配置されている。さらに、ショットキー電極5と所定の距離離れて配置されている。しかし、その効果は、程度の違いはあるが本質的に実施の形態1で示したものと同様である。
2 n-型SiCドリフト層
3 p型半導体領域
4 n型半導体領域
5 ショットキー電極
6 オーミック電極
7 マスク材料
8 n-型SiC層
9 ガードリング
10 絶縁膜
11 開口部
12 イオン
Claims (15)
- 第1導電型の炭化珪素基板と、
前記炭化珪素基板上に形成され、第1不純物濃度を有する前記第1導電型のドリフト層と、
前記ドリフト層内の表面に所定の間隔で形成された、前記第1導電型と反対の第2導電型を有する複数の第1半導体領域と、
前記ドリフト層とショットキー接続するショットキー電極と、
前記炭化珪素基板の裏面とオーミック接続するオーミック電極と、
前記第1半導体領域と前記炭化珪素基板との間の領域に、前記第1不純物濃度より高い第2不純物濃度を有する、前記第1導電型の第2半導体領域と、を備えることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記第2半導体領域は、前記第1半導体領域と接触して配置されていることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記ショットキー電極は、前記第1半導体領域の表面にも設けられていることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記第2半導体領域は、前記第1半導体領域の間であって、前記ショットキー電極と前記炭化珪素基板との間にも配置されていることを特徴とする半導体装置。 - 請求項4記載の半導体装置において、
前記ショットキー電極は、前記第2半導体領域とショットキー接続されていることを特徴とする半導体装置。 - 請求項4記載の半導体装置において、
前記第2半導体領域は、前記ショットキー電極と所定の距離離れて配置されていることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記第2半導体領域は、前記第1半導体領域の幅よりも広い幅を有することを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記第2半導体領域は、前記第1半導体領域の側面にも配置され、
前記第2半導体領域は、隣接する第2半導体領域と所定の間隔が設けられて、配置されていることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記第1半導体領域の幅は、前記ドリフト層の厚さの1/4倍よりも広いことを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
さらに、前記ドリフト層内に配置され、上面から見て複数の前記第1半導体領域を取り囲むように配置された前記第2導電型の第3半導体領域を備え、
前記ショットキー電極の端部は、前記第3半導体領域上に配置され、
前記第2半導体領域は、前記第3半導体領域と前記炭化珪素基板との間の領域にも配置されていることを特徴とする半導体装置。 - 第1導電型の炭化珪素基板と、
前記炭化珪素基板上に形成され、第1不純物濃度を有する前記第1導電型の第1半導体層と、
前記第1半導体層上に形成された、前記第1不純物濃度よりも高い第2不純物濃度を有する前記第1導電型の第2半導体層と、
前記第2半導体層内の表面に所定の間隔で形成された、前記第1導電型と反対の第2導電型を有する複数の第1半導体領域と、
前記第2半導体層とショットキー接続するショットキー電極と、
前記炭化珪素基板の裏面とオーミック接続するオーミック電極と、を備えることを特徴とする半導体装置。 - 請求項11記載の半導体装置において、
ドリフト層は前記第1半導体層と前記第2半導体層により構成され、
前記第1半導体領域の幅は、前記ドリフト層の厚さの1/4倍よりも広いことを特徴とする半導体装置。 - 第1導電型の炭化珪素基板と、
前記炭化珪素基板上に形成され、第1不純物濃度を有する前記第1導電型の第1半導体層と、
前記第1半導体層上に形成された、前記第1不純物濃度よりも高い第2不純物濃度を有する前記第1導電型の第2半導体層と、
前記第2半導体層内の表面に所定の間隔で形成された、前記第1導電型と反対の第2導電型を有する複数の第1半導体領域と、
前記第2半導体層内に形成され、上面から見て複数の前記第1半導体領域を取り囲みように配置された前記第2導電型を有する第2半導体領域と、
前記第2半導体層とショットキー接続するショットキー電極と、
前記炭化珪素基板の裏面とオーミック接続するオーミック電極と、を備えることを特徴とする半導体装置。 - 請求項13記載の半導体装置において、
ドリフト層は前記第1半導体層と前記第2半導体層により構成され、
前記第1半導体領域の幅は、前記ドリフト層の厚さの1/4倍よりも広いことを特徴とする半導体装置。 - 請求項13記載の半導体装置において、
前記第2半導体領域は、ガードリングであることを特徴とする半導体装置。
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Also Published As
Publication number | Publication date |
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JP5452718B2 (ja) | 2014-03-26 |
US20130140584A1 (en) | 2013-06-06 |
DE112010005626T5 (de) | 2013-03-21 |
JPWO2011151901A1 (ja) | 2013-07-25 |
DE112010005626B4 (de) | 2024-02-15 |
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