WO2011127727A1 - 一种防漏电的半导体结构 - Google Patents

一种防漏电的半导体结构 Download PDF

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Publication number
WO2011127727A1
WO2011127727A1 PCT/CN2010/078526 CN2010078526W WO2011127727A1 WO 2011127727 A1 WO2011127727 A1 WO 2011127727A1 CN 2010078526 W CN2010078526 W CN 2010078526W WO 2011127727 A1 WO2011127727 A1 WO 2011127727A1
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strained
layer
semiconductor layer
bandgap semiconductor
band gap
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PCT/CN2010/078526
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English (en)
French (fr)
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王敬
许军
郭磊
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清华大学
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Priority to US13/120,122 priority Critical patent/US8455858B2/en
Publication of WO2011127727A1 publication Critical patent/WO2011127727A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7391—Gated diode structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Definitions

  • the present invention relates to the field of semiconductor fabrication and design, and more particularly to a semiconductor structure, and more particularly to a semiconductor structure capable of suppressing leakage of MOS device BTBT (Band-To-Band Tunneling). Background technique
  • the forbidden band width of the high mobility narrow band gap semiconductor material is relatively small, for example, the forbidden band width of Ge is about 0.67 ev, the forbidden band width of InSb is about 0.18 eV, and the forbidden band width is smaller than the forbidden band width of the Si material. More. Therefore, with the use of Ge and other high mobility narrow bandgap semiconductor materials, the problem of BTBT leakage has become more and more serious.
  • an aspect of the present invention provides a semiconductor structure including a substrate, a transition layer or an insulating layer formed over the substrate, and a first strain formed on the transition layer or the insulating layer.
  • a wide bandgap semiconductor layer a strained narrow bandgap semiconductor layer formed over the first strained wide bandgap semiconductor layer, and a second strained wide bandgap semiconductor layer formed over the strained narrow bandgap semiconductor layer, a gate stack formed over the second strained wide bandgap semiconductor layer, and formed in the first strained wide band gap semiconductor layer, the strained narrow band gap semiconductor layer, and the second strained wide band gap semiconductor layer Source and drain.
  • This type of semiconductor structure not only suppresses the leakage of two kinds of BTBT, but also generates a hole potential well in an intermediate strain-narrow band gap semiconductor layer such as a strained Ge layer, improves carrier mobility, and improves device performance.
  • Another aspect of the invention also provides a semiconductor structure including a substrate, a transition layer or an insulating layer formed over the substrate, and a first strained wide band gap formed over the transition layer or the insulating layer a semiconductor layer, a strained narrow bandgap semiconductor layer formed over the first strained wide bandgap semiconductor layer, a gate stack formed over the strained narrow bandgap semiconductor layer, and formed at the first strain width
  • the source and the drain are in the semiconductor layer and the strain-narrowed-band semiconductor layer.
  • This type of semiconductor structure can effectively suppress the leakage of BTBT generated at the source-drain junction at the high bias of the drain terminal by increasing the first strain-bandgap semiconductor layer, such as the strained Si layer, thereby reducing the influence of BTBT leakage.
  • leakage of such BTBT can be better suppressed by the insulating layer under the first strained wide bandgap semiconductor layer.
  • FIG. 1 is a schematic structural view of a semiconductor according to Embodiment 1 of the present invention.
  • FIG. 2 is a schematic structural view of a semiconductor according to a second embodiment of the present invention.
  • FIG. 3 is a schematic structural view of a semiconductor device according to Embodiment 3 of the present invention.
  • FIG. 4 is a schematic structural view of a FinFET according to an embodiment of the present invention. Specific travel mode
  • the following disclosure provides many different embodiments or examples for implementing different structures of the present invention.
  • the components and arrangements of the specific examples are described below. Of course, they are merely examples and are not intended to limit the invention.
  • the present invention may repeat reference numerals and/or letters in different examples. This repetition is for the purpose of clarity and clarity and does not in itself indicate the relationship between the various embodiments and/or arrangements discussed.
  • the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art will recognize the applicability of other processes and/or the use of other materials.
  • the structure of the first feature described below "on" the second feature may include embodiments in which the first and second features are formed in direct contact, and may include additional features formed between the first and second features. The embodiment, such that the first and second features may not be in direct contact.
  • the BTBT leakage is analyzed.
  • the BTBT leakage mainly includes the BTBT leakage generated at the source and drain junctions at the high end of the drain, and the GIDL (gate induced drain leakage) leakage, wherein GIDL Leakage refers to the leakage of BTBT generated when the drain is at a high potential and the gate is at a potential.
  • GIDL Leakage refers to the leakage of BTBT generated when the drain is at a high potential and the gate is at a potential.
  • FIG. 1 is a schematic diagram of a semiconductor structure according to Embodiment 1 of the present invention.
  • the semiconductor structure 1000 can include a substrate 100, which can be any semiconductor substrate material including, but not limited to, silicon, germanium, silicon germanium, SOI (silicon on insulator), silicon carbide, gallium arsenide, or any III/ A substrate such as a group V compound semiconductor.
  • a substrate 100 can be any semiconductor substrate material including, but not limited to, silicon, germanium, silicon germanium, SOI (silicon on insulator), silicon carbide, gallium arsenide, or any III/ A substrate such as a group V compound semiconductor.
  • the semiconductor structure 1000 can also include a transition layer or insulating layer 200 formed over the substrate 100.
  • the transition layer 200 can be a relaxed SiGe dummy substrate layer, although other materials can be used as the transition layer.
  • the insulating layer 200 may include an insulating material such as SiO 2 to better suppress BTBT leakage generated at the source and drain junctions.
  • the semiconductor structure 1000 may further include a first strained wide band gap semiconductor layer 400 formed over the transition layer or the insulating layer 200, and a strained narrow band gap semiconductor layer formed over the first strained wide band gap semiconductor layer 400 500.
  • the wide band gap semiconductor material may include, but is not limited to, Si, SiC, GaN, InAlAs, InP, or a combination thereof
  • the narrow bandgap semiconductor material may include, but not limited to, Ge, InSb, GaAs, InGaAs. Or a combination thereof.
  • those skilled in the art can also choose other materials to implement the present invention, and any equivalents to the above materials should be included in the scope of the present invention without departing from the scope of the present invention.
  • the first strained wide bandgap semiconductor layer 400 may comprise a strained Si layer
  • the strained narrow bandgap semiconductor layer 500 may comprise a strained Ge or strained SiGe layer.
  • the first strained wide band gap semiconductor layer 400 and the strained narrow band gap semiconductor layer 500 may each comprise a strained SiGe layer, but the concentration of Ge in the strain narrow band gap semiconductor layer 500 is large
  • the concentration of Ge in the first strained wide bandgap semiconductor layer 400 It should be noted that those skilled in the art should be aware that the first strained wide bandgap semiconductor layer 400 and the strained narrow bandgap semiconductor layer 500 can also be used as a layer of strained SiGe layer in this embodiment.
  • the impurity condition is such that the Ge concentration in the upper portion of the strained SiGe layer is greater than the Ge concentration in the lower portion, thereby achieving the same technical effect as the present invention.
  • first strained wide band gap semiconductor layer 400 and the strained narrow band gap semiconductor layer 500 may also include multiple layers of strained SiGe layers, or the first strained wide band gap semiconductor layer 400 includes The multilayer structure composed of the multilayer strained Si layer and the strained SiGe layer, or the strained narrow band gap semiconductor layer 500 may include a multilayer structure composed of a multilayer strained Ge layer and a strained SiGe layer, etc., and thus these may be considered The equivalents of the above-described embodiments of the present invention are intended to be included within the scope of the present invention.
  • the semiconductor structure 1000 may further include a gate stack 300 formed over the strained narrow bandgap semiconductor layer 500, and source and drain formed in the first strained wide bandgap semiconductor layer 400 and the strained narrow bandgap semiconductor layer 500. Extreme 600.
  • the gate stack 300 may include a gate shield layer and a gate, and preferably may include a high-k gate shield layer and a metal gate, and of course other nitride or oxide shield layers or polysilicon. Gates are also applicable to the present invention and are therefore intended to be included within the scope of the present invention.
  • the gate stack 300 may also include other material layers to improve certain other characteristics of the gate. It can be seen that the present invention is not limited to the structure of the gate stack, and any type of gate structure may be employed. In another embodiment, one or more side walls may also be included on both sides of the gate stack 300.
  • the semiconductor structure is capable of effectively suppressing BTBT leakage generated at the source-drain junction at the high bias of the drain terminal by increasing the first strain-wide wide band gap semiconductor layer 400, such as a strained Si layer, thereby reducing the influence of the BTBT leakage.
  • This type of BTBT leakage can also be better suppressed by the insulating layer 200 under the first strained wide bandgap semiconductor layer 400.
  • a wide band gap semiconductor layer is added over the narrow band gap semiconductor material such as Ge, InSb, etc., thereby suppressing GIDL leakage, also in this embodiment, so-called
  • the wide bandgap semiconductor material is only relative to narrow bandgap semiconductor materials such as Ge and InSb.
  • FIG. 2 is a schematic diagram of a semiconductor structure according to a second embodiment of the present invention.
  • the semiconductor structure 2000 is similar to the semiconductor structure 1000 of the first embodiment, and also includes a substrate 100 and a transition layer or insulating layer 200 over the substrate 100, and a gate stack 300, etc., except that the semiconductor structure 2000 is included in the transition layer or A strain-narrowed band gap semiconductor layer 500 over the insulating layer 200, and a second strained wide band gap semiconductor layer 700 formed over the strained band gap semiconductor layer 500.
  • the source and drain electrodes 600 are formed in the strained narrow bandgap semiconductor layer 500 and the second strained wide bandgap semiconductor layer 700.
  • the wide bandgap semiconductor material may include, but is not limited to, Si, SiC, GaN, InAlAs, InP, or combinations thereof, and the like
  • the narrow bandgap semiconductor material may include, but is not limited to, Ge, InSb, GaAs, InGaAs. Or a combination thereof.
  • the narrow bandgap semiconductor layer 500 may comprise a strained Ge or strained SiGe layer
  • the second strained wide bandgap semiconductor layer 700 may comprise a strained Si layer.
  • the narrowed band gap semiconductor layer 500 and the second strained wide band gap semiconductor layer 700 may each comprise a strained SiGe layer, but the concentration of Ge in the strained narrow bandgap semiconductor layer 500 is much greater than the second strain width. The concentration of Ge in the semiconductor layer 700 is forbidden.
  • the semiconductor structure 2000 can effectively suppress the generation of GIDL leakage, thereby reducing the influence of BTBT leakage.
  • Embodiment 3 Embodiment 3,
  • this embodiment has an additional advantage in that a hole potential well can be formed, thereby increasing the carrier mobility and improving device performance.
  • FIG. 3 is a schematic diagram of a semiconductor structure according to a third embodiment of the present invention.
  • the semiconductor structure 3000 is similar to the above-described semiconductor structures 1000 and 2000, except that in this embodiment, the wide band gap semiconductor layer surrounds the narrow band gap semiconductor layer to suppress the above two BTBT leakage.
  • the semiconductor structure 3000 further includes a first strained wide bandgap semiconductor layer 400 formed on the transition layer or the insulating layer 200, formed in the first strain wide band gap.
  • the wide bandgap semiconductor material may include, but is not limited to, Si, SiC, GaN, InAlAs, InP, or combinations thereof, and the like
  • the narrow bandgap semiconductor material may include, but is not limited to, Ge, InSb, GaAs, InGaAs. Or a combination thereof.
  • the wide band gap semiconductor material and the narrow band gap semiconductor material may be arbitrarily combined, that is, the first strain wide band gap
  • the semiconductor layer 400 and the second strained wide bandgap semiconductor layer 700 may use the same wide bandgap semiconductor material, such as strained Si, or may use different wide bandgap semiconductor materials, such as a first strain band gap band.
  • the semiconductor layer 400 is made of strained Si
  • the second strained wide bandgap semiconductor layer 700 is made of strained SiGe, and the like.
  • the first strained wide bandgap semiconductor layer 400 and the second strained wide bandgap semiconductor layer 700 comprise a strained Si layer
  • the strained narrow bandgap semiconductor layer 500 comprises a strained Ge layer or strained SiGe.
  • the first strained wide bandgap semiconductor layer 400, the second strained wide bandgap semiconductor layer 700, and the strained narrow bandgap semiconductor layer 500 each comprise a strained SiGe layer, wherein the strained narrow bandgap semiconductor layer 500 is The concentration of Ge is much larger than the concentration of Ge in the first strained wide band gap semiconductor layer 400 and the second strained wide band gap semiconductor layer 700.
  • the strained narrow bandgap semiconductor layer 500 is used as a channel layer, such as a strained Ge layer or a strained SiGe layer, so that most of the hole carriers are concentrated at high due to the different shield band structure.
  • the mobility of the strain is narrow in the forbidden band semiconductor layer 500, so that the saturation current can be effectively improved and the device performance can be improved.
  • the thickness and doping of the first strained wide band gap semiconductor layer 400, the strained narrow band gap semiconductor layer 500, and the second strained wide band gap semiconductor layer 700 are as needed, and the present invention makes the thickness of the above layer
  • the thickness of each of the above layers cannot exceed the critical thickness to avoid relaxation and introduce new defects in the material layer, such as the first strain relief
  • the thickness of the semiconductor layer 400 is about 3 _ 5 nm, and the thicker the better than the critical thickness
  • the thickness of the narrow band gap semiconductor layer 500 is about 3 - lOnm, does not exceed the critical thickness, but must satisfy the carrier Transport requirements, and low or no doping to obtain higher carrier mobility
  • the second strained wide bandgap semiconductor layer 700 has a thickness of about 2 _ 5 nm, preferably 3 nm, heavily doped to provide suitable Carrier density.
  • the FinFET structure includes a gate 4100 and a gate shield layer 4300, and a source/drain 4200 including a first strain-gap semiconductor on a substrate (not shown).
  • the first strained wide bandgap semiconductor layer 4400 and the second strained wide bandgap semiconductor layer 4600 may be strained Si layers, and the strained narrow bandgap semiconductor layer 4500 may be strained Ge layers or strains. SiGe layer.
  • the first strained wide bandgap semiconductor layer 4400, the strained narrow bandgap semiconductor layer 4500, and the second strained wide bandgap semiconductor layer 4600 may each be a strained SiGe layer, but the strain narrow band gap semiconductor The Ge concentration in layer 4500 is much higher than the first strained wide band gap semiconductor layer 4400 and the second strained wide band gap semiconductor layer 4600. While the embodiments of the present invention have been shown and described, it will be understood by those skilled in the art The scope of the invention is defined by the appended claims and their equivalents.

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Description

一种防漏电的半导体结构 技术领域
本发明涉及半导体制造及设计领域， 特别涉及一种半导体结构， 更特别地涉及一种 能够抑制 MOS器件 BTBT ( Band-To-Band Tunneling, 带带隧穿） 漏电的半导体结构。 背景技术
随着半导体制造工艺的不断进步， 漏电流已经成为了非常关键而且不可忽视的问 题。 由于高迁移率的窄禁带半导体材料的禁带宽度比较小， 例如 Ge 的禁带宽度约为 0.67ev, InSb的禁带宽度约为 0.18eV, 其禁带宽度比 Si材料的禁带宽度小的多。 因此， 随着 Ge等高迁移率窄禁带半导体材料的使用， BTBT漏电的问题也变得越来越严重。
现有技术存在的缺点是， 随着半导体尺寸的不断减小， 以及窄禁带半导体材料的使 用， 使得 BTBT漏电变得越来越严重。 发明内容
本发明的目的旨在至少解决上述技术缺陷之一， 特别是解决 BTBT漏电的问题。 为达到上述目的， 本发明一方面提出了一种半导体结构， 包括衬底， 形成在所述衬 底之上的过渡层或绝缘层， 形成在所述过渡层或绝缘层之上的第一应变宽禁带半导体 层， 形成在所述第一应变宽禁带半导体层之上的应变窄禁带半导体层， 形成在所述应变 窄禁带半导体层之上的第二应变宽禁带半导体层， 形成在所述第二应变宽禁带半导体层 之上的栅堆叠， 和形成在所述第一应变宽禁带半导体层、 应变窄禁带半导体层和第二应 变宽禁带半导体层之中的源极和漏极。该类半导体结构不仅能抑制两种 BTBT漏电的产 生， 另外还能在中间的应变窄禁带半导体层， 例如应变 Ge层中产生空穴势阱， 提高载 流子的迁移率， 改善器件性能。
本发明另一方面还提出了一种半导体结构， 包括衬底， 形成在所述衬底之上的过渡 层或绝缘层， 形成在所述过渡层或绝缘层之上的第一应变宽禁带半导体层， 形成在所述 第一应变宽禁带半导体层之上的应变窄禁带半导体层， 形成在所述应变窄禁带半导体层 之上的栅堆叠， 和形成在所述第一应变宽禁带半导体层和应变窄禁带半导体层之中的源 极和漏极。 该类半导体结构通过增加的第一应变宽禁带半导体层， 例如应变 Si 层， 能 够有效抑制在漏端高偏压时源漏结处产生的 BTBT漏电， 从而减轻 BTBT漏电的影响。 另外， 通过在第一应变宽禁带半导体层之下的绝缘层能够更好的抑制该类 BTBT漏电。
本发明附加的方面和优点将在下面的描述中部分给出，部分将从下面的描述中变得 明显， 或通过本发明的实践了解到。 酎團说明
本发明上述的和 /或附加的方面和优点从下面结合附图对实施例的描述中将变得明 显和容易理解， 需要说明的是， 本发明的附图仅是示意性的， 因此没有必要按比例绘制， 其巾：
图 1为本发明实施例一的半导体结构示意图；
图 2为本发明实施例二的半导体结构示意图；
图 3为本发明实施例三的半导体结构示意图；
图 4为本发明实施例的 FinFET结构示意图。 具体实旅方式
下面详细描述本发明的实施例， 所述实施例的示例在附图中示出， 其中自始至终相 同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。 下面通过参考附 图描述的实施例是示例性的， 仅用于解释本发明， 而不能解释为对本发明的限制。
下文的公开提供了许多不同的实施例或例子用来实现本发明的不同结构。 为了筒化 本发明的公开， 下文中对特定例子的部件和设置进行描述。 当然， 它们仅仅为示例， 并 且目的不在于限制本发明。 此外， 本发明可以在不同例子中重复参考数字和 /或字母。 这 种重复是为了筒化和清楚的目的， 其本身不指示所讨论各种实施例和 /或设置之间的关 系。 此外， 本发明提供了的各种特定的工艺和材料的例子， 但是本领域普通技术人员可 以意识到其他工艺的可应用于性和 /或其他材料的使用。 另外， 以下描述的第一特征在第 二特征之"上"的结构可以包括第一和第二特征形成为直接接触的实施例， 也可以包括另 外的特征形成在第一和第二特征之间的实施例， 这样第一和第二特征可能不是直接接 触。
在本发明中， 对 BTBT漏电进行了分析， 目前 BTBT漏电主要包括漏端高偏压时在 源漏结处产生的 BTBT 漏电， 和 GIDL (栅极感应漏极漏电） 漏电两类， 其中， GIDL 漏电是指在栅漏交叠处， 当漏端处于高电位， 栅极处于氏电位时， 产生的 BTBT漏电。 以下就以具体实施例的方式进行描述， 以下实施例可至少抑制上述两类 BTBT漏电中的 一种， 但需要说明的是以下实施例仅是实现本发明的优选方式， 并不是说本发明仅能够 通过以下实施例实现， 本领域技术人员可对以下实施例中的部分特征做出等同的修改或 替换， 在不脱离本发明思想的范围内， 这些等同的修改或替换均应包含在本发明的保护 范围之内。
实施例一，
该实施例通过在 Ge、 InSb等窄禁带半导体材料的下方增加一层宽禁带半导体层， 从而可抑制漏端高偏压时在源漏结处产生的 BTBT漏电。 需要说明的是， 在本发明的本 实施例及以下实施例中， 所谓宽禁带半导体材料仅是相对于 Ge、 InSb等窄禁带半导体 材料来说， 例如 Si, 其自身的禁带宽度并不大， 但相对于 Ge来说， 在本发明的各个实 施例中 Si可被称为宽禁带半导体材料。 如图 1所示， 为本发明实施例一的半导体结构示意图。 该半导体结构 1000可包括 衬底 100 , 该衬底可为任何半导体衬底材料， 包括但不限于硅、 锗、 锗化硅、 SOI (绝 缘体上硅）、 碳化硅、 砷化镓或者任何 III/ V族化合物半导体等衬底。
该半导体结构 1000还可包括形成在衬底 100之上的过渡层或绝缘层 200。在本发明 的一个实施例中， 过渡层 200可为驰豫 SiGe虚拟衬底层， 当然也可釆用其他材料作为 过渡层。 在本发明的另一个实施例中， 绝缘层 200可包括 Si02等绝缘材料， 从而能够 更好地抑制源漏结处产生的 BTBT漏电。
该半导体结构 1000还可包括形成在过渡层或绝缘层 200之上的第一应变宽禁带半 导体层 400 , 和形成在该第一应变宽禁带半导体层 400之上的应变窄禁带半导体层 500。 其中， 在本发明实施例中， 宽禁带半导体材料可包括但不限于 Si、 SiC、 GaN、 InAlAs、 InP或其组合等， 窄禁带半导体材料可包括但不限于 Ge、 InSb、 GaAs、 InGaAs或其组 合等。 当然本领域技术人员还可选择其他材料实现本发明， 但是在不脱离本发明思想的 范围内， 任何对上述材料的等同替换也均应包含在本发明的保护范围之内。
其中， 优选地， 在本发明的一个实施例中， 第一应变宽禁带半导体层 400可包括应 变 Si层， 应变窄禁带半导体层 500可包括应变 Ge或应变 SiGe层。
其中， 在本发明的另一个优选实施例中， 第一应变宽禁带半导体层 400和应变窄禁 带半导体层 500可均包括应变 SiGe层，但是应变窄禁带半导体层 500中 Ge的浓度远大 于第一应变宽禁带半导体层 400中 Ge的浓度。 在此需要说明的是， 本领域技术人员应 当可以意识到， 在该实施例中第一应变宽禁带半导体层 400和应变窄禁带半导体层 500 也可作为一层应变 SiGe层， 通过控制掺杂条件使得该应变 SiGe层中上部分的 Ge浓度 大于下部的 Ge浓度， 从而达到与本发明相同的技术效果。 另外， 本领域技术人员还可 意识到， 上述第一应变宽禁带半导体层 400和应变窄禁带半导体层 500也可包括多层的 应变 SiGe层， 或者第一应变宽禁带半导体层 400包括由多层应变 Si层和应变 SiGe层 组成的多层结构， 再或者应变窄禁带半导体层 500可包括由多层应变 Ge层和应变 SiGe 层组成的多层结构等等， 因此这些均可认为是对本发明上述实施例的等同替换， 均应包 含在本发明的保护范围之内。
该半导体结构 1000还可包括形成在应变窄禁带半导体层 500之上的栅堆叠 300 ,和 形成在第一应变宽禁带半导体层 400和应变窄禁带半导体层 500之中的源极和漏极 600。 在本发明的一个实施例中， 栅堆叠 300可包括栅介盾层和栅极， 优选地， 可包括高 k栅 介盾层和金属栅极， 当然其他氮化物或氧化物介盾层或多晶硅栅极也可应用在本发明 中， 因此也应包含在本发明的保护范围之内。 在其他实施例中， 栅堆叠 300还可包含其 他材料层以改善栅极的某些其他特性， 可以看出本发明对栅堆叠的结构并没有限制， 可 釆用任何类型的栅结构。 在另一个实施例中， 在栅堆叠 300的两侧还可包括一层或多层 侧墙。
该半导体结构通过增加的第一应变宽禁带半导体层 400 , 例如应变 Si层， 从而能够 有效抑制在漏端高偏压时源漏结处产生的 BTBT漏电， 减轻 BTBT漏电的影响。 另外， 通过在第一应变宽禁带半导体层 400之下的绝缘层 200也能够更好的抑制该类 BTBT漏 电。 实施例二，
与实施例一不同的是， 在该实施例中， 是在 Ge、 InSb等窄禁带半导体材料的上方 增加一层宽禁带半导体层， 从而可抑制 GIDL漏电， 同样在该实施例中， 所谓宽禁带半 导体材料仅是相对于 Ge、 InSb等窄禁带半导体材料而言的。
如图 2所示， 为本发明实施例二的半导体结构示意图。 该半导体结构 2000与实施 例一的半导体结构 1000类似， 也包括衬底 100和衬底 100之上的过渡层或绝缘层 200 以及栅堆叠 300等， 不同的是该半导体结构 2000包括在过渡层或绝缘层 200之上的应 变窄禁带半导体层 500, 和形成在应变窄禁带半导体层 500之上的第二应变宽禁带半导 体层 700。 其中源极和漏极 600形成在应变窄禁带半导体层 500和第二应变宽禁带半导 体层 700之中。 其中， 在本发明的其他实施例中， 在过渡层或绝缘层 200与应变窄禁带 半导体层 500之间还可以包括其他的层， 以改善两者之间的应力条件或接触条件， 或者 为了其他目的。 在本发明的一个实施例中， 宽禁带半导体材料可包括但不限于 Si、 SiC、 GaN、 InAlAs、 InP或其组合等， 窄禁带半导体材料可包括但不限于 Ge、 InSb, GaAs、 InGaAs或其组合等。 优选地， 在本发明的一个实施例中， 变窄禁带半导体层 500可包 括应变 Ge或应变 SiGe层， 第二应变宽禁带半导体层 700可包括应变 Si层。 在另一个 优选实施例中， 变窄禁带半导体层 500 和第二应变宽禁带半导体层 700 可均包括应变 SiGe层，但是应变窄禁带半导体层 500中 Ge的浓度远大于第二应变宽禁带半导体层 700 中 Ge的浓度。 该半导体结构 2000能够有效抑制 GIDL漏电的产生， 从而减轻 BTBT漏 电的影响。 实施例三，
在该实施例中综合了上述两个实施例的优点，从而可以同时抑制两种 BTBT漏电的 产生。 另外， 该实施例还有一个附加的优点， 即可形成空穴势阱， 从而提高载流子的迁 移率， 改善器件性能。
如图 3所示， 为本发明实施例三的半导体结构示意图。 该半导体结构 3000与上述 半导体结构 1000和 2000类似， 不同的是在该实施例中， 釆用宽禁带半导体层包围窄禁 带半导体层的方式来抑制上述两种 BTBT漏电。 如图 3所示， 不同于上述实施例的是， 该半导体结构 3000还包括形成在过渡层或绝缘层 200之上的第一应变宽禁带半导体层 400、形成在该第一应变宽禁带半导体层 400之上的应变窄禁带半导体层 500、和形成在 应变窄禁带半导体层 500之上的第二应变宽禁带半导体层 700。 在本发明的一个实施例 中， 宽禁带半导体材料可包括但不限于 Si、 SiC、 GaN、 InAlAs、 InP或其组合等， 窄禁 带半导体材料可包括但不限于 Ge、 InSb, GaAs、 InGaAs或其组合等。 在本发明实施例 中， 上述宽禁带半导体材料和窄禁带半导体材料可任意组合， 也就是说第一应变宽禁带 半导体层 400和第二应变宽禁带半导体层 700可釆用相同的宽禁带半导体材料， 如都釆 用应变 Si, 也可以釆用不同的宽禁带半导体材料， 例如第一应变宽禁带半导体层 400釆 用应变 Si, 而第二应变宽禁带半导体层 700釆用应变 SiGe, 等等。
优选地， 在本发明的一个实施例中， 第一应变宽禁带半导体层 400和第二应变宽禁 带半导体层 700包括应变 Si层， 应变窄禁带半导体层 500包括应变 Ge层或应变 SiGe 层。在其他优选实施例中， 第一应变宽禁带半导体层 400、 第二应变宽禁带半导体层 700 和应变窄禁带半导体层 500均包括应变 SiGe层， 其中， 应变窄禁带半导体层 500中 Ge 的浓度远大于第一应变宽禁带半导体层 400和第二应变宽禁带半导体层 700中 Ge的浓 度。 在该实施例中， 釆用了应变窄禁带半导体层 500作为沟道层， 例如应变 Ge层或应 变 SiGe层， 因此由于异盾能带结构， 大部分的空穴载流子都聚集在高迁移率的应变窄 禁带半导体层 500中， 因此可以有效提高饱和电流， 改善器件性能。 在本发明中上述第 一应变宽禁带半导体层 400、 应变窄禁带半导体层 500和第二应变宽禁带半导体层 700 的厚度和掺杂根据需要而定， 本发明对上述层的厚度做了一个筒单的介绍， 例如根据驰 豫 SiGe虚拟衬底层中 Ge的含量， 上述各层的厚度不能超过临界厚度， 以免发生驰豫从 而在材料层中引入新的缺陷， 例如第一应变宽禁带半导体层 400的厚度约为 3 _ 5nm, 不超过临界厚度情况下越厚越好； 应变窄禁带半导体层 500的厚度约为 3 - lOnm, 不超 过临界厚度， 但又必须保证满足载流子运输的要求， 且低掺杂或者不掺杂以得到更高的 载流子迁移率； 第二应变宽禁带半导体层 700的厚度约为 2 _ 5nm, 优选为 3nm, 重掺 杂以提供合适的载流子密度。 本发明所提出的上述半导体结构不仅可适用于垂直栅结 构， 还可适用于 FinFET结构， 当然其他结构或者今后发展的新的半导体结构也可釆用 本发明的各个实施例来抑制 BTBT漏电。
如图 4所示， 为本发明实施例的 FinFET结构示意图。 如图 4, FinFET结构包括栅 极 4100和栅介盾层 4300 , 以及源极 /漏极 4200, 源极 /漏极 4200包括位于衬底 (未示出） 之上的第一应变宽禁带半导体层 4400, 位于第一应变宽禁带半导体层 4400之上的应变 窄禁带半导体层 4500 , 以及包围应变窄禁带半导体层 4500的第二应变宽禁带半导体层 4600。 其中， 在本发明的一个实施例中， 第一应变宽禁带半导体层 4400和第二应变宽 禁带半导体层 4600可为应变 Si层， 应变窄禁带半导体层 4500可为应变 Ge层或应变 SiGe层。 在本发明的另一个实施例中， 第一应变宽禁带半导体层 4400、 应变窄禁带半 导体层 4500和第二应变宽禁带半导体层 4600均可为应变 SiGe层， 但应变窄禁带半导 体层 4500中 Ge浓度远高于第一应变宽禁带半导体层 4400和第二应变宽禁带半导体层 4600。 尽管已经示出和描述了本发明的实施例， 但是对于本领域的普通技术人员而言， 可以理解在不脱离本发明的原理和精神的情况下可以对这些实施例进行多种变化、 修 改、 替换和变型， 本发明的范围由所附权利要求及其等同限定。

Claims

权利要求书
1、 一种防漏电的半导体结构， 其特征在于， 包括：
衬底；
形成在所述衬底之上的过渡层或绝缘层；
形成在所述过渡层或绝缘层之上的第一应变宽禁带半导体层；
形成在所述第一应变宽禁带半导体层之上的应变窄禁带半导体层；
形成在所述应变窄禁带半导体层之上的第二应变宽禁带半导体层；
形成在所述第二应变宽禁带半导体层之上的栅堆叠； 和
形成在所述第一应变宽禁带半导体层、应变窄禁带半导体层和第二应变宽禁带半导 体层之中的源极和漏极。
2、 如权利要求 1 所述的防漏电的半导体结构， 其特征在于， 所述过渡层包括驰豫 SiGe虚拟衬底层。
3、 如权利要求 1或 2所述的防漏电的半导体结构， 其特征在于， 所述第一应变宽 禁带半导体层和第二应变宽禁带半导体层包括应变 Si 层， 所述应变窄禁带半导体层包 括应变 Ge或应变 SiGe层。
4、 如权利要求 1或 2所述的防漏电的半导体结构， 其特征在于， 所述第一应变宽 禁带半导体层、 第二应变宽禁带半导体层和所述应变窄禁带半导体层均包括应变 SiGe 层， 其中， 所述应变窄禁带半导体层中 Ge的浓度大于所述第一应变宽禁带半导体层和 第二应变宽禁带半导体层中 Ge的浓度。
5、 如权利要求 1 所述的防漏电的半导体结构， 其特征在于， 宽禁带半导体材料包 括 Si、 SiC、 GaN、 InAlAs、 InP或其组合。
6、如权利要求 1所述的半导体结构，其特征在于，窄禁带半导体材料包括 Ge、InSb、 GaAs、 InGaAs或其组合。
7、 一种防漏电的半导体结构， 其特征在于， 包括：
衬底；
形成在所述衬底之上的过渡层或绝缘层；
形成在所述过渡层或绝缘层之上的第一应变宽禁带半导体层；
形成在所述第一应变宽禁带半导体层之上的应变窄禁带半导体层；
形成在所述应变窄禁带半导体层之上的栅堆叠； 和
形成在所述第一应变宽禁带半导体层和应变窄禁带半导体层之中的源极和漏极。
8、 如权利要求 7所述的防漏电的半导体结构， 其特征在于， 在所述应变窄禁带半 导体层和所述栅堆叠之间还包括第二应变宽禁带半导体层， 所述第二应变宽禁带半导体 层中形成有所述源极和漏极。
9、 如权利要求 7所述的防漏电的半导体结构， 其特征在于， 所述过渡层包括驰豫 SiGe虚拟衬底层。
10、 如权利要求 7 - 9任一项所述的防漏电的半导体结构， 其特征在于， 所述第一 应变宽禁带半导体层包括应变 Si 层， 所述应变窄禁带半导体层包括应变 Ge 层或应变 SiGe层。
11、 如权利要求 10所述的防漏电的半导体结构， 其特征在于， 所述第二应变宽禁 带半导体层包括应变 Si层或应变 SiGe层。
12、 如权利要求 7 - 9任一项所述的防漏电的半导体结构， 其特征在于， 所述第一 应变宽禁带半导体层和所述应变窄禁带半导体层均包括应变 SiGe层， 其中， 所述应变 窄禁带半导体层中 Ge的浓度大于所述第一应变宽禁带半导体层中 Ge的浓度。
13、 如权利要求 12所述的防漏电的半导体结构， 其特征在于， 所述第二应变宽禁 带半导体层包括应变 SiGe层或应变 Si层， 且当所述第二应变宽禁带半导体层包括应变 SiGe层时， 所述应变窄禁带半导体层中 Ge的浓度远大于所述第二应变宽禁带半导体层 中 Ge的浓度。
14、 如权利要求 7所述的防漏电的半导体结构， 其特征在于， 宽禁带半导体材料包 括 Si、 SiC、 GaN、 InAlAs、 InP或其组合。
15、 如权利要求 7所述的防漏电的半导体结构， 其特征在于， 窄禁带半导体材料包 括 Ge、 InSb、 GaAs、 InGaAs或其组合。
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