WO2018182687A1

WO2018182687A1 - Field effect transistor structures

Info

Publication number: WO2018182687A1
Application number: PCT/US2017/025382
Authority: WO
Inventors: Willy Rachmady; Matthew V. Metz; Gilbert Dewey; Sean T. MA
Original assignee: Intel Corporation
Priority date: 2017-03-31
Filing date: 2017-03-31
Publication date: 2018-10-04

Abstract

Solid-state devices having a semiconductor layer passivating a portion of a carrier transport medium are provided. Processes to form such devices also are provided. The semiconductor layer can be adjacent to a transport electrode of a solid-state device, and can form an interface with a spacer layer that separates a gate electrode and the transport electrode. In some embodiments, the carrier transport medium can be formed from a first III-V semiconductor compound, and the semiconductor layer can be formed from a second III-V semiconductor compound. The energy bandgap of the first III-V semiconductor compound can be less than the energy bandgap of the second III-V semiconductor compound. In addition or in other embodiments, the semiconductor layer can have a substantially uniform thickness in a range from about 1 nm to about 5 nm.

Description

FIELD EFFECT TRANSISTOR STRUCTURES

BACKGROUND

[0001] Some InGaAs compounds have an energy bandgap that is smaller than the indirect bandgap of Si. Therefore, the effect of gate induced barrier lowering (GIDL) in a drain electrode of a field effect transistor (FET) formed with one such compound can be more pronounced that in other FETs formed from Si. Thus, InGaAs FETs can present significantly greater parasitic source-drain leakage than Si FETs. Therefore, much remains to be improved in the design of InGaAs FETs in order to reduce parasitic source-drain leakage. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] The accompanying drawings are an integral part of the disclosure and are incorporated into the subject specification. The drawings illustrate example embodiments of the disclosure and, in conjunction with the description and claims, serve to explain at least in part various principles, features, or aspects of the disclosure. Certain embodiments of the disclosure are described more fully below with reference to the accompanying drawings.

However, various aspects of the disclosure can be implemented in many different forms and should not be construed as limited to the implementations set forth herein. Like numbers refer to like, but not necessarily the same or identical, elements throughout.

[0003] FIG. 1 illustrates a schematic cross-sectional view of a solid-state assembly 100 that can embody or can constitute a solid-state device, in accordance with one or more embodiments of the disclosure.

[0004] FIGS. 2A-2B illustrate schematic cross-sectional views of an example solid structure representative of a stage of an example process for fabricating a semiconductor device, in accordance with one or more embodiments of the disclosure. Specifically, FIG. 2A illustrates a schematic cross-sectional view of the solid structure in a cut across a length of a gate member, in accordance with one or more embodiments of the disclosure; and FIG. IB illustrates another schematic cross-sectional view of the solid structure in a cut across a fin member of the semiconductor device, in accordance with one or more embodiments of the disclosure.

[0005] FIGS. 3A-3B illustrate schematic cross-sectional views of an example solid structure representative of another stage of an example process for fabricating a

semiconductor device, in accordance with one or more embodiments of the disclosure.

Specifically, FIG. 3A illustrates a schematic cross-sectional view of the solid structure in a l cut across a length of a gate member of the semiconductor device, in accordance with one or more embodiments of the disclosure; and FIG. 3B illustrates another schematic cross- sectional view of the solid structure in a cut across a fin member of the semiconductor device, in accordance with one or more embodiments of the disclosure.

[0006] FIGS. 4A-4B illustrate schematic cross-sectional views of an example solid structure representative of another stage of the example process for fabricating a

Specifically, FIG. 4A illustrates a schematic cross-sectional view of the solid structure in a cut across a length of a gate member of the semiconductor device, in accordance with one or more embodiments of the disclosure; and FIG. 4B illustrates another schematic cross- sectional view of the solid structure in a cut across a fin member of the semiconductor device, in accordance with one or more embodiments of the disclosure.

[0007] FIGS. 5A-5B illustrate schematic cross-sectional views of an example solid structure representative of another stage of the example process for fabricating a

Specifically, FIG. 5A illustrates a schematic cross-sectional view of the solid structure in a cut across a length of a gate member of the semiconductor device, in accordance with one or more embodiments of the disclosure; and FIG. 5B illustrates another schematic cross- sectional view of the solid structure in a cut across a fin member of the semiconductor device, in accordance with one or more embodiments of the disclosure.

[0008] FIG. 6 illustrates a schematic cross-sectional view of an example solid structure representative of another stage of the example process for fabricating a semiconductor device, in accordance with one or more embodiments of the disclosure. The schematic cross- sectional view corresponds to a cut across a length of a gate member of the semiconductor device, in accordance with one or more embodiments of the disclosure.

[0009] FIG. 7 illustrates schematic cross-sectional views of an example solid structure representative of another stage of the example process for fabricating a semiconductor device, in accordance with one or more embodiments of the disclosure. The schematic cross- sectional view of the solid structure in a cut across a length of a gate member of the semiconductor device, in accordance with one or more embodiments of the disclosure.

[0010] FIG. 8 illustrates an example of a method of fabricating solid-state structures in accordance with one or more embodiments of the disclosure.

[0011] FIG. 9 presents an example of a system that utilizes solid-state devices in accordance with one or more embodiments of the disclosure. DETAILED DESCRIPTION

[0012] The disclosure recognizes and addresses, in at least some embodiments, the issue of parasitic source-drain leakage in III-V FETs. In some approaches, GIDL leakage current in an InGaAs FET can be mitigated by including a thin layer of a high energy bandgap material between a transport channel of the FET and a source electrode extension layer and/or a drain electrode extension layer of the FET. Such approaches can be difficult to achieve because the inclusion of the high energy bandgap material usually increases external resistance R_ext of the device. Without intending to be bound by theory and/or modeling, R_ext increases due to a charge carrier— an electron in NMOS InGaAs FET or a hole in a PMOS InGaAs FET— having to overcome a significant tunneling barrier through the high energy bandgap layer.

[0013] Further, due to higher charge-carrier mobility in an InGaAs compound, a source electrode extension and/or a drain electrode extension can be pulled back away from a gate with minimal impact on drive current. It is required now that the area under the spacers need to be well passivated as they are now part of the transport channel. As described in greater detail below, embodiments of the disclosure provide solid-state devices having a

semiconductor layer passivating a portion of a carrier transport medium. Other embodiments also provide processes to form such devices. The semiconductor layer can be adjacent to a transport electrode of a solid-state device, and can form an interface with a spacer layer that separates a gate electrode and the transport electrode. In some embodiments, the transport medium can be formed from a first III-V semiconductor compound, and the semiconductor layer can be formed from a second III-V semiconductor compound. The energy bandgap of the first III-V semiconductor compound can be less than the energy bandgap of the second III-V semiconductor compound. In addition or in other embodiments, the semiconductor layer can have a substantially uniform thickness in a range from about 1 nm to about 5 nm.

[0014] Embodiments of the disclosure can provide various advantages over conventional technologies. Specifically, in contrast to conventional technologies to reduce GIDL leakage current, at least some embodiments of the present disclosure do not yield increments in R_ext of InGaAs FETs.

[0015] FIG. 1 illustrates a schematic cross-sectional view of a solid-state assembly 100 that can embody or can constitute a solid-state device, in accordance with one or more embodiments of the disclosure. As mentioned, in some embodiments, the solid-state device can embody or can constitute a non-planar FET, such as a finFET, all-around-gate FETs, tri- gate FETs, dual-gate FETs, or other types of non-planar FETs having contact members (e.g., a source contact member and/or a drain contact member) embodied in one or more nanowires. The solid-state assembly 100 can include a semiconductor substrate 110 that can be formed from Si or another intrinsic semiconductor material. The solid-state assembly 100 also can include a first semiconductor slab 120 that can be partially embedded in the semiconductor substrate 110. In embodiments in which the solid-state device is embodied in a finFET, the first semiconductor slab 120 can constitute a first fin member. The

semiconductor slab 120 can be formed from or can include an intrinsic semiconductor material having an energy bandgap material comparable to (or, in some embodiments, greater than) silicon, for example. As such, in some embodiments, the intrinsic semiconductor material can include III-V semiconductor compounds (such GaAs, InSb, InAs, In_xGa_yAs, InP, GaP, AlAs, GaSb, In_xAl_yAs, Ga_xAl_yAs, InSb, GaAs_xSb_y, InAs_xSby, In_xGa_yAs_zPi_-z, and the like); II-VI compounds; a combination thereof; or the like. In addition, the solid-state assembly 100 also can include a second semiconductor slab 130 formed from an intrinsic III- V semiconductor compound, such as Ini_-xGa_xAs, where the index x is a real number indicative of a defined stoichiometry of the compound. The second semiconductor slab 130 can embody or can constitute a carrier transport channel. In embodiments in which the solid- state device is embodied in a finFET, the second semiconductor slab 120 can constitute a second fin member. In such embodiments, the first semiconductor slab 120 and the second semiconductor slab 130 can form the fin of the finFET.

[0016] The second semiconductor slab 130 can include a first recess and a second recess, each forming respective interfaces with a first conductive electrode member 140a and a second conductive electrode member 140b. Each of the first conductive electrode member 140a and the second conductive electrode member 140b can be formed from or can include, in some embodiments, a heavily-doped semiconductor material or another type of conductive material. In one example, the heavily-doped semiconductor material can be embodied in an «+ +-type III-V semiconductor compound having an energy bandgap that is less than the energy bandgap of the first semiconductor slab 120. The parameter n+ + is a real number in units of carrier density (e.g., number of carriers per unit of surface) indicative of a defined electron concentration within each of the first conductive electrode member 140a and the second conductive electrode member 140b. In some embodiments, n+ + can be greater than about 10²¹ cm^"3. In some aspects, the first conductive electrode member 140a and the second conductive electrode member 140b can embodied in or can constitute respective transport electrodes, e.g., a source contact and a drain contact. [0017] The solid-state assembly 100 also can include a first passivation layer 180a and a second passivation layer 180b. In one aspect, the first passivation layer 180a and the second passivation layer 180b form respective interfaces with a first portion and a second portion of the second semiconductor slab 130. The first passivation layer 180a and the second passivation layer can have respective substantially uniform thicknesses in a range from about 1 nm to about 5 nm. Each of the first passivation layer 180a and the second passivation layer 170b can be formed from or can include a III-V semiconductor compound. In one aspect, the III-V semiconductor compound can have an energy bandgap that is greater than the energy bandgap of the second semiconductor slab 130. For instance, the III-V semiconductor compound can be embodied in or can include InP or InSb. In addition or in another aspect, the first passivation layer 180a and the second passivation layer 180b can form respective second interfaces with a first spacer layer 170a and a second spacer layer 170b.

[0018] Each of the first spacer layer 170a and the second spacer layer 170b can be formed from or can include a low-i^ dielectric material, such as an oxide, a nitride, a carbide, a silicate, a combination thereof (e.g., multiple layers of different materials), or the like. In some examples, the oxide can be embodied in or can include beryllium oxide, magnesium oxide, aluminum oxide, hafnium oxide, zirconium oxide, lanthanum oxide, yttrium oxide, scandium oxide, gadolinium oxide, and the like. In other examples, the nitride can be embodied in or can include boron nitride, aluminum nitride, silicon nitride, and the like. In yet other example, the carbide can be embodied in or can include wide-bandgap polytypes of silicon carbide, such as 2H and 4H, and the like. In still other examples, the silicates (e.g., hafnium silicate, zirconium silicate, and the like). As such, in some aspects, the first spacer layer 170a can mitigate capacitive coupling between the first conductive electrode member 140a and a gate electrode member 150, and the second spacer layer 170b can mitigate capacitive coupling between the second conductive electrode member 170b and the gate member 150. In some embodiments, in regions proximate to the first electrode member 170a and the second electrode member 170b, respectively, the first spacer layer 170a and the second spacer layer 170b can have respective thicknesses within a range from about 2 nm to about 10 nm.

[0019] In some embodiments, the gate electrode member 150 can be formed from or can include a metal, such as one or more of copper, aluminum, tungsten, titanium, tantalum, silver, gold, palladium, platinum, zinc, nickel, or an alloy of two or more of the foregoing metals. The disclosure is not so limited and, in other embodiments, the gate electrode member 150 can be formed from another type of conductive material, such as a doped semiconductor, a conductive ceramic, or the like.

[0020] As illustrated in FIG. 1, a dielectric liner 160 can isolate the gate electrode member 150 from the second semiconductor slab 130, and each of the first spacer layer 170a and the second spacer layer 170b. The dielectric liner 160 can be referred to as a gate dielectric liner and can be formed from or can include a high-i^ dielectric material. In some embodiments, high-i^ dielectric materials can include, for example, alumina; silicon monoxide (SiO, K of about 5.0); silicon dioxide (Si0₂, ^ of about 3.9); titanium dioxide; silicon nitride (Si0₃N₄, K of about 6); boron nitride (BN, K of about 4.5); alkali halides (such as rubidium bromide (RbBr, K of about 4.7), lithium fluoride (LiF, K of about 9.2), barium titanate (BaTi0₃, K varies from about 130 to about 1000), lead titanate (PbTi0₃, K ranges between about 200 to about 400); and metal oxides (e.g., hafnium dioxide (Hf0₂, ^ of about 40), tantalum oxide (TaO_¾ K of about 27), tungsten oxide (WO₃, ^ of about 42) and zirconium dioxide (Zr0₂, K of about 24.7). Other high-i^ materials can include, for example, La₂0₃, SrTi0₃, LaA10₃, Y₂0₃, Al₂O_xN_y, HfO_xN_y, ZrO_xN_y, La₂O_xN_y, TiO_xN_y, SrTiO_xN_y, LaA10_xN_y,Y₂O_xN_y, SiON, SiN, a silicate thereof, or an alloy thereof.

[0021] Numerous processes can be implemented to form a semiconductor device including the solid assembly 100 or similar solid assemblies. Each of such processes can include multiple stages. After an initial stage to treat a solid structure that embodies or constitutes an initial solid structure (such as a substrate, finned or otherwise), subsequent stages can include treating respective solid structures resulting from previous stages of the process.

[0022] FIGS. 2A-2B illustrate schematic cross-sectional views of an example solid structure 200 representative of a stage of an example process for fabricating a semiconductor device, in accordance with one or more embodiments of the disclosure. Specifically, FIG. 2A illustrates a schematic cross-sectional view of the solid structure 200 in a cut across a length of a gate member, in accordance with one or more embodiments of the disclosure. The solid structure 200 includes a semiconductor substrate 210, such as a Si substrate or a Ge substrate. The solid structure 200 also includes a fin member 220 that can be formed within the substrate 210 by means of an aspect ratio trapping (ART) process. In some embodiments, the fin member 220 can be formed from a semiconductor material having a high energy bandgap, such as GaAs or another III-V semiconductor compound having a high energy bandgap. As such, in one embodiment, the solid structure 200 can include a Si substrate embodying the semiconductor substrate 210 and a slab of GaAs embodying the fin member 220. In addition, the solid structure 200 can include a semiconductor slab 230 forming an interface with the fin member 220. The semiconductor slab 230 can be formed from a semiconductor material having an energy bandgap less than another energy bandgap of the semiconductor compound that forms or otherwise constitute the fin member 220. In some embodiments, the semiconductor material can include a III-V semiconductor compound, such as Ini_-xGa_xAs or InSb.

[0023] As illustrated in FIG. IB, the fin member 220 can be partially embedded within the substrate 210, and can be bound by an isolation member 260a (e.g., a shallow trench isolation layer) and an isolation member 260b (e.g., another shallow trench isolation layer). Thus, in one aspect, the fin member 220 can form a first interface with the isolation member 260a and also can form a second interface with the isolation member 260b. As mentioned, the semiconductor slab 230 can form an interface with the fin member 230. The cut illustrated in FIG. IB is along the segment AA' shown in FIG. 2A and can be referred to as a fincut.

[0024] With further reference to FIG. 2A, the solid structure 200 also can include a dielectric layer 240 and a sacrificial gate member 250 forming an interface with the dielectric layer 240. The sacrificial gate member 250 can be formed from a dielectric material or semiconductor material (e.g., polysilicon), and can preserve a region for formation of a functional gate member at a later stage of the deposition process.

[0025] As part of another stage of the example process for forming a semiconductor device in accordance with aspects of the disclosure, the solid structure 200 can be treated to form a solid structure 300, as is shown in FIG. 3A. Treating the solid structure 200 can include forming semiconductor layers in order to encapsulate (or passivate) an exposed surface of the semiconductor slab 230. Such layers can be formed from InP. In some embodiments, each (or, in other embodiments, at least one) of the semiconductor layers can have a substantially uniform thickness having a magnitude in a range from about 1 nm to about 3 nm. Specifically, in some embodiments, a first semiconductor layer 310a can be formed selectively on a first portion of the semiconductor slab 230, and a second

semiconductor layer 310b can be formed selectively on a second portion of the

semiconductor slab 230. In one example, each of the first semiconductor layer 310a and the second semiconductor layer 310b can have a substantially uniform thickness of a magnitude in a range from about 1 nm to about 5 nm. As illustrated in FIG. 3B, the second

semiconductor layer 310b can encapsulate at least a portion of the of the semiconductor slab 230. FIG. 3B schematic cross-sectional view of the solid structure 300 shown in FIG. 3A. In FIG. 3B, the cross-sectional cut is across a fin member of the semiconductor device, in accordance with one or more embodiments of the disclosure. Such a cut is along the segment AA' and can be referred to as a fmcut.is a cross-sectional cut is along the segment AA' and can be referred to as a fincut.

[0026] As part of another stage of the example process for forming a semiconductor device in accordance with aspects of the disclosure, the solid structure 300 can be treated to form a solid structure 400, as is shown in FIG. 4A. Treating the solid structure 300 can include depositing an amount of low-i^ material (e.g., an oxide, a nitride, a carbide, a silicate) on the sacrificial gate member 250 and on at least respective portions of the first

semiconductor layer 310a and the second semiconductor layer 310b. In some aspects, the amount of the low-i^ material can form a solid film that can be treated (e.g., patterned) to form a first spacer layer 410a and a second spacer layer 410b. In one aspect, each of the first spacer layer 410a and the second spacer layer 410b forms an interface with the sacrificial gate member 250. In another aspect, as is illustrated in FIG. 4B, the second spacer layer 410b can cap a portion of the semiconductor slab 230. While not shown, the first spacer layer 410a also can cap another portion of the semiconductor slab 230. FIG. 4B schematic cross-sectional view of the solid structure 400 shown in FIG. 4A. In FIG. 4B, the cross- sectional cut is across a fin member of the semiconductor device, in accordance with one or more embodiments of the disclosure. Such a cut is along the segment AA' and can be referred to as a fmcut.is a cross-sectional cut is along the segment AA' and can be referred to as a fincut.

[0027] As part of another stage of the example process, the solid structure 400 can be treated to form a solid structure 500 as is shown in FIG. 5A. To that end, in some aspects, treating the solid structure 400 can include removing a portion of the first semiconductor layer 310a and another portion of the second semiconductor layer 310b. Removal of such portions can result in first semiconductor layer 510a and a second semiconductor layer 510b, each of such layers also encapsulate a portion of the semiconductor slab 230, as is illustrated in FIG. 5B. As described herein, FIG. 5B illustrated schematic cross-sectional view of the solid structure 500 shown in FIG. 4A. In FIG. 5B, the cross-sectional cut is across a fin member of the semiconductor device, in accordance with one or more embodiments of the disclosure. Such a cut is along the segment AA' and can be referred to as a fmcut.is a cross- sectional cut is along the segment AA' and can be referred to as a fincut.In one embodiment, removing the portion of the first semiconductor layer 310a can include selectively etching an amount of the semiconductor material that constitutes the first semiconductor layer 310a. In addition, removing the portion of the second semiconductor layer 310b can include selectively etching an amount of the semiconductor material that constitutes the second semiconductor layer 310b. To that end, the etching can include subjecting each of the first semiconductor layer 310a and the second semiconductor layer 310b to a wet etch process or a dry etch process. In some embodiments, wet etching relies on a liquid solution for the removal of a material and generally is isotropic. Wet etching can utilize or otherwise rely upon aqueous hydroxide chemistries, including ammonium hydroxide and potassium hydroxide, solution of carboxylic acid/nitric acid/hydrofluoric acid, and solutions of citric acid/nitric acid/hydrofluoric acid. In other aspects, dry etching generally refers to etching that does not rely on a solution for the removal of a material, and generally is anisotropic. Dry etching can rely on plasma (e.g., a gas of electrons) or ions. Thus, dry etching can include plasma etching and reactive-ion etching (RIE) and its variants, such as deep REI.

[0028] In another stage of the example process to form a semiconductor device in accordance with aspects of the present disclosure, the solid structure 500 can be treated to form a solid structure 600, as is illustrated in FIG. 6. In some embodiments, treating the solid structure 500 can include etching a first portion and a second portion of the

semiconductor slab 630 to form a semiconductor slab 610. To that end, in one aspect, a surface of the semiconductor slab 630 can be subjected to an undercut etch process, forming a first recess and a second recess in the semiconductor slab 630. The first portion of the semiconductor slab 610 also can be treated to form a first electrode member 620a, and the second portion of the semiconductor slab 610 can be further treated to form a second electrode member 620b. In some embodiments, forming the first electrode member 620a can include depositing a highly-doped (e.g., «+ +-type) layer of a III-V semiconductor compound. For instance, an amount of Si-doped InGaAs or another amount of Te-doped InGaAs can be deposited to form the first electrode member 620a. Other highly-doped semiconductor materials also can be utilized to form the first electrode member 620a. In addition or in other embodiments, forming the second electrode member 620b can include depositing another highly-doped layer of a III-V semiconductor compound. For instance, as mentioned, an amount of Si-doped InGaAs or another amount of Te-doped InGaAs can be deposited to form the first electrode member 620a. Other highly-doped semiconductor materials also can be utilized to form the second electrode member 620b.

[0029] As mentioned, the sacrificial gate member 250 can preserve a region within the semiconductor device being formed for the formation of a functional gate electrode. To that end, the solid structure 600 can be treated to form the solid structure 700 illustrated in FIG. 7. Treating the solid structure 600 can include forming a first dielectric member 730a and a second dielectric member 730b. Each of the first dielectric member 730a and the second dielectric member 730b can serve as an interlay er dielectric (ILD) that can be leveraged for circuit integration of the solid structure 700. In some embodiments, after the formation of the dielectric member 730a and the dielectric member 730b, the sacrificial gate member 250 and the dielectric layer 240 can be removed, resulting in a recess (not depicted). In some embodiments, removing the sacrificial gate member 250 can include selectively etching a first material that constitutes the sacrificial gate member 250 and a second material that constitutes the dielectric layer 240. Similar to other stages of the example process, selective etching can include subjecting the sacrificial gate member 250 and the dielectric layer 240 to one or more wet etch processes or dry etch processes. The recess can be filled by depositing a high-i^ dielectric liner 710 and a gate electrode member 720. In one aspect, the high-i^ dielectric liner 710 is conformal with a surface of the recess (not depicted) and can have a substantially uniform thickness having a magnitude in a range from about 1 nm to about 5 nm. Depositing the high-i^ dielectric liner 710 can include subjecting a surface of the recess to ALD (or, in some embodiments, CVD) of an amount of a high-i^ dielectric material. In addition, depositing the gate electrode member 720 can include depositing an amount of metal on a surface of the high-i^ dielectric liner 710. The amount of the metal can be deposited, in some embodiments, by subjecting such a surface to one or a combination of deposition processes (e.g., sputtering or another type of PVD).

[0030] The example process can continue with other stages directed to form contacts and interconnects (neither depicted) to complete fabrication of a semiconductor device that includes the solid structure 700.

[0031] In view of the various aspects of solid-state assemblies and solid-state devices includes therein, a number of processes or methods for fabricating such assemblies can be implemented in accordance with aspects of this disclosure. As an illustration, FIG. 8 presents an example of a method of fabricating a solid-assembly in accordance with one or more embodiments of the disclosure. At block 810, a semiconductor slab can be provided. The semiconductor slab can include a sacrificial member extending from a surface of the semiconductor slab to a distal end. In some embodiments, providing the semiconductor slab can include forming a fin member (e.g., the semiconductor slab 230) on a substrate. As disclosed herein, the fin member can include a first III-V semiconductor compound, such GaAs, InSb, InAs, In_xGa_yAs, InP, GaP, AlAs, GaSb, In_xAl_yAs, Ga_xAl_yAs, InSb, GaAs_xSb_y, InAs_xSb_y, In_xGa_yAs_zPi-_z, and the like.

[0032] At block 820, a semiconductor passivation layer can be provided on a first portion of the semiconductor slab. In some embodiments, providing the semiconductor passivation layer (e.g., first semiconductor layer 310a and/or the second semiconductor layer 310b) can include depositing a film of a second III-V semiconductor compound on a portion of the fin member, the film having a substantially uniform thickness of a magnitude in a range from about 1 nm to about 5 nm. In addition, or in some embodiments, depositing the film of the second III-V semiconductor compound can include depositing at least an amount of InP. At block 830, a dielectric layer can be provided on a first portion of the semiconductor passivation layer, the dielectric layer adjacent to the sacrificial member. At block 840, a second portion of the semiconductor passivation layer can be removed, resulting in an exposed portion of the surface. In some embodiments, removing the second portion of the semiconductor passivation layer comprises selectively etching the second portion by means of one of a wet etch process or a dry etch process. At block 850, the exposed portion of the surface can be treated to form a recess in the semiconductor slab. In some embodiments, treating the exposed portion of the surface comprises selectively etching the semiconductor slab, resulting in the a recess in the semiconductor slab.

[0033] At block 860, a conductive electrode can be provided. In some aspects, the conductive electrode can be at least partially embedded in the recess. In some embodiments, providing the conductive electrode comprises depositing, on at least a portion of the recess, an amount of a doped III-V semiconductor compound comprising Si atoms, Sn atoms, Se atoms, or Te atoms.

[0034] FIG. 9 depicts an example of a system 900 according to one or more

embodiments of the disclosure. In one embodiment, system 900 includes, but is not limited to, a desktop computer, a laptop computer, a netbook, a tablet, a notebook computer, a personal digital assistant (PDA), a server, a workstation, a cellular telephone, a mobile computing device, a smart phone, an Internet appliance or any other type of computing device. In some embodiments, system 900 can include a system on a chip (SOC) system or a system-in-package (SiP).

[0035] In one embodiment, system 900 includes multiple processors including processor 910 and processor N 905, where processor 905 has logic similar or identical to the logic of processor 910. In one embodiment, processor 910 has one or more processing cores (represented here by processing core 912 and processing core 912N, where 912N represents the Nth processor core inside processor 910, where N is a positive integer). More processing cores can be present (but not depicted in the diagram of FIG. 9). In some embodiments, processing core 912 includes, but is not limited to, pre-fetch logic to fetch instructions, decode logic to decode the instructions, execution logic to execute instructions, a combination thereof, or the like. In some embodiments, processor 910 has a cache memory 916 to cache instructions and/or data for system 900. Cache memory 916 may be organized into a hierarchical structure including one or more levels of cache memory.

[0036] In some embodiments, processor 910 includes a memory controller (MC) 914, which is configured to perform functions that enable the processor 910 to access and communicate with memory 930 that includes a volatile memory 932 and/or a non-volatile memory 934. In some embodiments, processor 910 can be coupled with memory 930 and chipset 920. Processor 910 may also be coupled to a wireless antenna 978 to communicate with any device configured to transmit and/or receive wireless signals. In one embodiment, the wireless antenna interface 978 operates in accordance with, but is not limited to, the IEEE 802.11 standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.

[0037] In some embodiments, volatile memory 932 includes, but is not limited to, Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), RAMBUS Dynamic Random Access Memory (RDRAM), and/or any other type of random access memory device. Non-volatile memory 934 includes, but is not limited to, flash memory, phase change memory (PCM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or any other type of nonvolatile memory device.

[0038] Memory device 930 stores information and instructions to be executed by processor 910. In one embodiment, memory 930 may also store temporary variables or other intermediate information while processor 910 is executing instructions. In the illustrated embodiment, chipset 920 connects with processor 910 via Point-to-Point (PtP or P-P) interface 917 and P-P interface 922. Chipset 920 enables processor 910 to connect to other elements in system 900. In some embodiments of the disclosure, P-P interface 917 and P-P interface 922 can operate in accordance with a PtP communication protocol, such as the Intel® QuickPath Interconnect (QPI) or the like. In other embodiments, a different interconnect may be used.

[0039] In some embodiments, chipset 920 can be configured to communicate with processor 910, 905N, display device 940, and other devices 972, 976, 974, 960, 962, 964, 966, 977, etc. Chipset 920 may also be coupled to the wireless antenna 978 to communicate with any device configured to transmit and/or receive wireless signals.

[0040] Chipset 920 connects to display device 940 via interface 926. Display 940 may be, for example, a liquid crystal display (LCD), a plasma display, cathode ray tube (CRT) display, or any other form of visual display device. In some embodiments of the disclosure, processor 910 and chipset 920 are integrated into a single SOC. In addition, chipset 920 connects to bus 950 and/or bus 955 that interconnect various elements 974, 960, 962, 964, and 966. Bus 950 and bus 955 may be interconnected via a bus bridge 972. In one embodiment, chipset 920 couples with a non-volatile memory 960, a mass storage device(s) 962, a keyboard/mouse 964, and a network interface 966 via interface 924 and/or 904, smart TV 976, consumer electronics 977, etc.

[0041] In one embodiment, mass storage device(s) 962 can include, but not be limited to, a solid state drive, a hard disk drive, a universal serial bus flash memory drive, or any other form of computer data storage medium. In one embodiment, network interface 966 is implemented by any type of well-known network interface standard including, but not limited to, an Ethernet interface, a universal serial bus (USB) interface, a Peripheral Component Interconnect (PCI) Express interface, a wireless interface and/or any other suitable type of interface. In one embodiment, the wireless interface operates in accordance with, but is not limited to, the IEEE 802.11 standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.

[0042] While the modules shown in FIG. 9 are depicted as separate blocks within the system 900, the functions performed by some of these blocks may be integrated within a single semiconductor circuit or may be implemented using two or more separate integrated circuits. For example, although cache memory 916 is depicted as a separate block within processor 910, cache memory 916 or selected elements thereof can be incorporated into processor core 912.

[0043] It is noted that the system 900 described herein may be any suitable type of microelectronics packaging and configurations thereof, including, for example, system in a package (SiP), system on a package (SOP), package on package (PoP), interposer package, 3D stacked package, etc. Further, any suitable type of microelectronic components may be provided in the semiconductor packages, as described herein. For example, microcontrollers, microprocessors, baseband processors, digital signal processors, memory dies, field gate arrays, logic gate dies, passive component dies, MEMSs, surface mount devices, application specific integrated circuits, baseband processors, amplifiers, filters, combinations thereof, or the like may be packaged in the semiconductor packages, as disclosed herein. The semiconductor devices (for example, the semiconductor device described in connection with FIG. 1) or other types of semiconductor devices, as disclosed herein, may be provided in any variety of electronic device including consumer, industrial, military, communications, infrastructural, and/or other electronic devices.

[0044] The semiconductor devices or other types of solid-state devices, as described herein, may be embody or may constitute one or more processors. The one or more processors may include, without limitation, a central processing unit (CPU), a digital signal processor(s) (DSP), a reduced instruction set computer (RISC), a complex instruction set computer (CISC), a microprocessor, a microcontroller, a field programmable gate array (FPGA), or any combination thereof. The processors may also include one or more application specific integrated circuits (ASICs) or application specific standard products (ASSPs) for handling specific data processing functions or tasks. In certain embodiments, the processors may be based on an Intel® Architecture system and the one or more processors and any chipset included in an electronic device may be from a family of Intel® processors and chipsets, such as the Intel® Atom® processor(s) family or Intel-64 processors (e.g., Sandy Bridge®, Ivy Bridge®, Haswell®, Broadwell®, Skylake®, etc.).

[0045] Additionally or alternatively, the semiconductor devices, as described herein, may embody or may constitute one or more memory chips or other types of memory devices. The memory chips may include one or more volatile and/or non-volatile memory devices including, but not limited to, magnetic storage devices, read-only memory (ROM), random access memory (RAM), dynamic RAM (DRAM), static RAM (SRAM), synchronous dynamic RAM (SDRAM), double data rate (DDR) SDRAM (DDR-SDRAM), RAM-BUS DRAM (RDRAM), flash memory devices, electrically erasable programmable read-only memory (EEPROM), non-volatile RAM (NVRAM), universal serial bus (USB) removable memory, or combinations thereof.

[0046] In example embodiments, the electronic device in which the semiconductor devices in accordance with this disclosure are provided may be a computing device. Such a computing device may house one or more boards on which the semiconductor package connections may be disposed. The board may include a number of components including, but not limited to, a processor and/or at least one communication chip. The processor may be physically and electrically connected to the board through, for example, electrical connections of the semiconductor package. The computing device may further include a plurality of communication chips. For instance, a first communication chip may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth, and a second communication chip may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, and others. In various example embodiments, the computing device may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, combinations thereof, or the like. In further example embodiments, the computing device may be any other electronic device that processes data.

[0047] The semiconductor devices and other types of solid assemblies in accordance with aspects of the disclosure may be used in connection with one or more processors. The one or more processors may include, without limitation, a central processing unit (CPU), a digital signal processor(s) (DSP), a reduced instruction set computer (RISC), a complex instruction set computer (CISC), a microprocessor, a microcontroller, a field programmable gate array (FPGA), or any combination thereof. The processors may also include one or more application specific integrated circuits (ASICs) or application specific standard products (ASSPs) for handling specific data processing functions or tasks. In certain embodiments, the processors may be based on an Intel® Architecture system and the one or more processors and any chipset included in an electronic device may be from a family of Intel® processors and chipsets, such as the Intel® Atom® processor(s) family or Intel-64 processors (for example, Sandy Bridge®, Ivy Bridge®, Haswell®, Broadwell®, Skylake®, etc.).

[0048] Additionally or alternatively, semiconductor devices and other types of solid assemblies in accordance with aspects of the disclosure may be used in connection with one or more memory chips. The memory may include one or more volatile and/or non-volatile memory devices including, but not limited to, magnetic storage devices, read-only memory (ROM), random access memory (RAM), dynamic RAM (DRAM), static RAM (SRAM), synchronous dynamic RAM (SDRAM), double data rate (DDR) SDRAM (DDR-SDRAM), RAM-BUS DRAM (RDRAM), flash memory devices, electrically erasable programmable read-only memory (EEPROM), non-volatile RAM (NVRAM), universal serial bus (USB) removable memory, or combinations thereof.

[0049] In example embodiments, an electronic device in which the semiconductor devices and other types of solid assemblies in accordance with aspects of the disclosure can be used and/or provided may be a computing device. Such a computing device may house one or more boards on which the interconnects may be disposed. The board may include a number of components including, but not limited to, a processor and/or at least one communication chip. The processor may be physically and electrically connected to the board through, for example, electrical connections of the interconnects. The computing device may further include a plurality of communication chips. For instance, a first communication chip may be dedicated to shorter range wireless communications such as Wi- Fi and Bluetooth, and a second communication chip may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, and others. In various example embodiments, the computing device may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra- mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, combinations thereof, or the like. In further example embodiments, the computing device may be any other electronic device that processes data.

[0050] Further Examples.— The following example embodiments pertain to further embodiments of this disclosure. Example 1 includes a solid-state assembly, comprising: a semiconductor slab including a recess; a conductive electrode at least partially placed in the recess; a semiconductor passivation layer forming a first interface with a portion of the semiconductor slab, the first interface being substantially perpendicular to a sidewall of the recess; and a dielectric layer adjacent to the semiconductor passivation layer and further adjacent to the conductive electrode, the dielectric layer forming a second interface with the semiconductor passivation layer, the second interface opposite to the first interface.

[0051] In Example 2, the assembly of Example 1 can optionally include a gate electrode adjacent to the semiconductor passivation layer and further adjacent to the dielectric layer, the gate electrode forming a third interface with the semiconductor passivation layer.

[0052] In Example 3, the assembly of any one of Examples 1 -2 can optionally include the semiconductor slab comprising a first III-V semiconductor compound, and wherein the semiconductor passivation layer comprises a second III-V semiconductor compound.

[0053] In Example 4, the assembly of any one of Examples 1 -3 can optionally include a first energy bandgap of the first III-V semiconductor compound being less than a second energy bandgap of the second III-V semiconductor compound.

[0054] In Example 5, the assembly of any one of Examples 1 -4 can optionally include the first III-V semiconductor compound comprising an alloy of InAs and GaAs, and the second III-V semiconductor compound comprising InP. [0055] In Example 6, the assembly of any one of Examples 1-5 can optionally include the first III-V semiconductor compound being selected from the group comprising InAs, GaAs, InP, GaP, InSb, AlAs, GaSb, a first alloy of InAl and AlAs, a second alloy of GaAs and AlAs, a third alloy of GaAs and GaSb, and a fourth alloy of InAs and InSb,

[0056] In Example 7, the assembly of any one of Examples 1-6 can optionally include a distance between the first interface and the second interface being substantially uniform and corresponding to a thickness of the semiconductor passivation layer, the thickness having a magnitude in a range from about 1 nm and about 5 nm.

[0057] In Example 8, the assembly of any one of Examples 1-7 can optionally include the conductive electrode comprises an n++-type doped III-V semiconductor compound, the conductive electrode having an average density of dopants of a magnitude of at least about 10²¹ cm^"3.

[0058] In Example 9, the assembly of any of Examples 1-8 where the «+ +-type doped III-V semiconductor compound comprises an alloy of InAs and GaAs, the alloy doped with one of Si atoms, Sn atoms, Se atoms, or Te atoms.

[0059] Example 10 includes a method of fabricating a solid-state assembly, comprising: providing a semiconductor slab including a sacrificial member extending from a surface of the semiconductor slab to a distal end; providing a semiconductor passivation layer on a first portion of the semiconductor slab; providing a dielectric layer on a first portion of the semiconductor passivation layer, the dielectric layer adjacent to the sacrificial member; removing a second portion of the semiconductor passivation layer, resulting in an exposed portion of the surface; treating the exposed portion of the surface to form a recess in the semiconductor slab; and providing a conductive electrode at least partially embedded in the recess.

[0060] In Example 11, the method of Example 10 can optionally include providing the semiconductor slab comprising forming a fin member on a substrate, the fin member comprising a first III-V semiconductor compound.

[0061] In Example 12, the method of any one of Examples 10-11 can optionally include providing the semiconductor passivation layer comprising depositing a film of a second III-V semiconductor compound on a portion of the fin member, the film having a substantially uniform thickness of a magnitude in a range from about 1 nm to about 5 nm.

[0062] In Example 13, the method of any one of Examples 1-12 can optionally include depositing the film of the second III-V semiconductor compound comprising depositing at least an amount of InP. [0063] In Example 14, the method of any one of Examples 10-13 can optionally include removing the second portion of the semiconductor passivation layer comprising selectively etching the second portion by means of one of a wet etch process or a dry etch process.

[0064] In Example 15, the method of any one of Examples 10-14 can optionally include treating the exposed portion of the surface comprising selectively etching the semiconductor slab, resulting in the a recess in the semiconductor slab.

[0065] In Example 16, the method of any one of Examples 10-15 can optionally include providing the conductive electrode comprising depositing, on at least a portion of the recess, an amount of a doped III-V semiconductor compound comprising Si atoms, Sn atoms, Se atoms, or Te atoms.

[0066] Example 17 includes an electronic device, comprising: at least one semiconductor die having circuitry assembled therein, the circuitry comprising a plurality of solid-state assemblies, at least one of the plurality of solid-state assemblies comprising, a semiconductor slab including a recess; a conductive electrode at least partially placed in the recess; a semiconductor passivation layer forming a first interface with a portion of the semiconductor slab, the first interface being substantially perpendicular to a sidewall of the recess; and a dielectric layer adjacent to the semiconductor passivation layer and further adjacent to the conductive electrode, the dielectric layer forming a second interface with the carrier-doped semiconductor layer, the second interface opposite to the first interface.

[0067] In Example 18, the electronic device of Example 17 can optionally include a gate electrode adjacent to the semiconductor passivation layer and further adjacent to the dielectric layer, the gate electrode forming a third interface with the semiconductor passivation layer.

[0068] In Example 19, the electronic device of any one of Examples 17-18 can optionally include semiconductor slab comprising a first III-V semiconductor compound, and the semiconductor passivation layer comprising a second III-V semiconductor compound. In

Example 20, the electronic device of any one of Examples 17-19 can optionally include a first energy bandgap of the first III-V semiconductor compound being less than a second energy bandgap of the second III-V semiconductor compound.

[0069] In Example 21 , the electronic device of any one of Examples 17-20 can optionally include the first III-V semiconductor compound comprising an InGaAs alloy, and the second III-V semiconductor compound comprising InP.

[0070] In Example 22, the electronic device of any one of Examples 17-21 can optionally include the first III-V semiconductor compound being selected from the group comprising InAs, GaAs, InP, GaP, InSb, AlAs, GaSb, a first alloy of InAl and AlAs, a second alloy of GaAs and AlAs, a third alloy of GaAs and GaSb, and a fourth alloy of InAs and InSb.

[0071] In Example 23, the electronic device of any one of Examples 17-22 can optionally include a distance between the first interface and the second interface being substantially uniform and corresponding to a thickness of the semiconductor passivation layer, the thickness having a magnitude in a range from about 1 nm and about 5 nm.

[0072] In Example 24, the electronic device of any one of Examples 17-23 can optionally include the conductive electrode comprising an n++-type doped III-V semiconductor compound, the conductive electrode having an average density of dopants of a magnitude of at least about 10²¹ cm^"3.

[0073] In Example 25, the electronic device of any one of Examples 17-24 can optionally include the n++-type doped III-V semiconductor compound comprising an alloy of InAs and GaAs, the alloy doped with one of Si atoms, Sn atoms, Se atoms, or Te atoms..

[0074] As mentioned, unless otherwise expressly stated, it is in no way intended that any protocol, procedure, process, or method set forth herein be construed as requiring that its acts or steps be performed in a specific order. Accordingly, where a process or method claim does not actually recite an order to be followed by its acts or steps or it is not otherwise specifically recited in the claims or descriptions of the subject disclosure that the steps are to be limited to a specific order, it is no way intended that an order be inferred, in any respect. This holds for any possible non-express basis for interpretation, including: matters of logic with respect to arrangement of steps or operational flow; plain meaning derived from grammatical organization or punctuation; the number or type of embodiments described in the specification or annexed drawings, or the like.

[0075] Conditional language, such as, among others, "can," "could," "might," or "may," unless specifically stated otherwise, or otherwise understood within the context as used, is generally intended to convey that certain implementations could include, while other implementations do not include, certain features, elements, and/or operations. Thus, such conditional language generally is not intended to imply that features, elements, and/or operations are in any way required for one or more implementations or that one or more implementations necessarily include logic for deciding, with or without user input or prompting, whether these features, elements, and/or operations are included or are to be performed in any particular implementation.

[0076] As used herein, the term "substantially" indicates that each of the described dimensions is not a strict boundary or parameter and does not exclude functionally similar variations therefrom. Unless context or the description indicates otherwise, the use of the term "substantially" in connection with a numerical parameter indicates that the numerical parameter includes variations that, using mathematical and industrial principles accepted in the art (e.g., rounding, measurement or other systematic errors, manufacturing tolerances, etc.), would not vary the least significant digit.

[0077] Further, certain relationships between dimensions of layers of a semiconductor device in accordance with this disclosure and between other elements of the semiconductor device are described herein using the term "substantially equal." As used herein, the term "substantially equal" indicates that the equal relationship is not a strict relationship and does not exclude functionally similar variations therefrom. Unless context or the description indicates otherwise, the use of the term "substantially equal" in connection with two or more described dimensions indicates that the equal relationship between the dimensions includes variations that, using mathematical and industrial principles accepted in the art (e.g., rounding, measurement or other systematic errors, manufacturing tolerances, etc.), would not vary the least significant digit of the dimensions. As used herein, the term "substantially constant" indicates that the constant relationship is not a strict relationship and does not exclude functionally similar variations therefrom.

[0078] As used herein, the term "substantially parallel" indicates that the parallel relationship is not a strict relationship and does not exclude functionally similar variations therefrom. As used herein the term "substantially perpendicular" indicates that the perpendicular relationship between two or more elements of a semiconductor device in accordance with this disclosure are not a strict relationship and does not exclude functionally similar variations therefrom.

[0079] The term "horizontal" as used herein may be defined as a direction parallel to a plane or surface (e.g., surface of a substrate), regardless of its orientation. The term

"vertical," as used herein, may refer to a direction orthogonal to the horizontal direction as just described. Terms, such as "on," "above," "below," "bottom," "top," "side"

(as in "sidewall"), "higher," "lower," "upper," "over," and "under," may be referenced with respect to the horizontal plane. The term "processing" as used herein is generally intended to include deposition of material or photoresist, patterning, exposure, development, etching, cleaning, ablating, polishing, and/or removal of the material or photoresist as

required in forming a described structure.

[0080] What has been described herein in the present specification and annexed drawings includes examples of solid-state devices having a semiconductor layer passivating a portion of a carrier transport medium, and processes to form such devices. It is, of course, not possible to describe every conceivable combination of elements and/or methodologies for purposes of describing the various features of the disclosure, but one of ordinary skill in the art can recognize that many further combinations and permutations of the claimed subject matter are possible. Accordingly, it may be apparent that various modifications can be made to the disclosure without departing from the scope or spirit thereof. In addition or in the alternative, other embodiments of the disclosure may be apparent from consideration of the specification and annexed drawings, and practice of the disclosure as presented herein. It is intended that the examples put forward in the specification and annexed drawings be considered, in all respects, as illustrative and not restrictive. Although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.

Claims

claimed is:

A solid-state assembly, comprising:

a semiconductor slab including a recess;

a conductive electrode at least partially disposed in the recess;

a semiconductor passivation layer forming a first interface with a portion of the

semiconductor slab, the first interface being substantially perpendicular to a sidewall of the recess; and

a dielectric layer adjacent to the semiconductor passivation layer and further adjacent to the conductive electrode, the dielectric layer forming a second interface with the semiconductor passivation layer, the second interface opposite to the first interface.

The solid-state assembly of claim 1, further comprising a gate electrode adjacent to the semiconductor passivation layer and further adjacent to the dielectric layer, the gate electrode forming a third interface with the semiconductor passivation layer.

The solid-state assembly of claim 1, wherein the semiconductor slab comprises a first III-V semiconductor compound, and wherein the semiconductor passivation layer comprises a second III-V semiconductor compound.

The solid-state assembly of claim 3, wherein a first energy bandgap of the first III-V semiconductor compound is less than a second energy bandgap of the second III-V semiconductor compound.

The solid-state assembly of claim 3, wherein the first III-V semiconductor compound comprises an alloy of InAs and GaAs, and wherein the second III-V semiconductor compound comprises InP.

The solid-state assembly of claim 3, wherein the first III-V semiconductor compound is selected from a group comprising InAs, GaAs, InP, GaP, InSb, AlAs, GaSb, a first alloy of InAl and AlAs, a second alloy of GaAs and AlAs, a third alloy of GaAs and GaSb, and a fourth alloy of InAs and InSb.

7. The solid-state assembly of claim 1, wherein a distance between the first interface and the second interface is substantially uniform and corresponds to a thickness of the semiconductor passivation layer, the thickness having a magnitude in a range from about 1 nm and about 5 nm.

8. The solid-state assembly of claim 1, wherein the conductive electrode comprises an «+ +-type doped III-V semiconductor compound, the conductive electrode having an average density of dopants of a magnitude of at least about 10²¹ cm^"3.

9. The solid-state assembly of claim 8, wherein the «+ +-type doped III-V

semiconductor compound comprises an alloy of InAs and GaAs, the alloy doped with one of Si atoms, Sn atoms, Se atoms, or Te atoms.

10. A method of fabricating a solid-state assembly, comprising:

providing a semiconductor slab including a sacrificial member extending from a surface of the semiconductor slab to a distal end;

providing a semiconductor passivation layer on a first portion of the semiconductor slab;

providing a dielectric layer on a first portion of the semiconductor passivation layer, the dielectric layer adjacent to the sacrificial member;

removing a second portion of the semiconductor passivation layer, resulting in an exposed portion of the surface;

treating the exposed portion of the surface to form a recess in the semiconductor slab; and

providing a conductive electrode at least partially embedded in the recess.

11. The method of claim 10, wherein the providing the semiconductor slab comprises forming a fin member on a substrate, the fin member comprising a first III-V semiconductor compound.

12. The method of claim 11 , wherein the providing the semiconductor passivation layer comprises depositing a film of a second III-V semiconductor compound on a portion of the fin member, the film having a substantially uniform thickness of a magnitude in a range from about 1 nm to about 5 nm.

13. The method of claim 12, wherein the depositing the film of the second III-V

semiconductor compound comprises depositing at least an amount of InP.

14. The method of claim 10, wherein the removing the second portion of the

semiconductor passivation layer comprises selectively etching the second portion by means of one of a wet etch process or a dry etch process.

15. The method of claim 10, wherein the treating the exposed portion of the surface comprises selectively etching the semiconductor slab, resulting in the a recess in the semiconductor slab. 16. The method of claim 10, wherein the providing the conductive electrode comprises depositing, on at least a portion of the recess, an amount of a doped III-V

semiconductor compound comprising Si atoms, Sn atoms, Se atoms, or Te atoms.

17. An electronic device, comprising:

at least one semiconductor die having circuitry assembled therein, the circuitry

comprising a plurality of solid-state assemblies, at least one of the plurality of solid-state assemblies comprising,

a semiconductor slab including a recess;

a conductive electrode at least partially placed in the recess;

a semiconductor passivation layer forming a first interface with a portion of the semiconductor slab, the first interface being substantially perpendicular to a sidewall of the recess; and

18. The electronic device of claim 17, further comprising a gate electrode adjacent to the semiconductor passivation layer and further adjacent to the dielectric layer, the gate electrode forming a third interface with the semiconductor passivation layer.

19. The electronic device of claim 17, wherein the semiconductor slab comprises a first III-V semiconductor compound, and wherein the semiconductor passivation layer comprises a second III-V semiconductor compound.

20. The electronic device of claim 19, wherein a first energy bandgap of the first III-V semiconductor compound is less than a second energy bandgap of the second III-V semiconductor compound.

21. The electronic device of claim 19, wherein the first III-V semiconductor compound comprises an InGaAs alloy, and wherein the second III-V semiconductor compound comprises InP.

22. The electronic device of claim 19, wherein the first III-V semiconductor compound is selected from a group comprising InAs, GaAs, InP, GaP, InSb, AlAs, GaSb, a first alloy of InAl and AlAs, a second alloy of GaAs and AlAs, a third alloy of GaAs and GaSb, and a fourth alloy of InAs and InSb.

23. The electronic device of claim 17, wherein a distance between the first interface and the second interface is substantially uniform and corresponds to a thickness of the semiconductor passivation layer, the thickness having a magnitude in a range from about 1 nm and about 5 nm.

24. The electronic device of claim 17, wherein the conductive electrode comprises an «+ +-type doped III-V semiconductor compound, the conductive electrode having an average density of dopants of a magnitude of at least about 10²¹ cm^"3.

25. The electronic device of claim 23, wherein the «+ +-type doped III-V semiconductor compound comprises an alloy of InAs and GaAs, the alloy doped with one of Si atoms, Sn atoms, Se atoms, or Te atoms.