WO2011125235A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- WO2011125235A1 WO2011125235A1 PCT/JP2010/060945 JP2010060945W WO2011125235A1 WO 2011125235 A1 WO2011125235 A1 WO 2011125235A1 JP 2010060945 W JP2010060945 W JP 2010060945W WO 2011125235 A1 WO2011125235 A1 WO 2011125235A1
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- region
- igbt
- lifetime control
- diode
- semiconductor layer
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 94
- 210000000746 body region Anatomy 0.000 claims abstract description 28
- 239000010410 layer Substances 0.000 claims description 57
- 239000002344 surface layer Substances 0.000 claims description 12
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- 238000011084 recovery Methods 0.000 description 34
- 230000003071 parasitic effect Effects 0.000 description 25
- 239000012535 impurity Substances 0.000 description 14
- 238000002955 isolation Methods 0.000 description 13
- 238000000034 method Methods 0.000 description 12
- 235000008733 Citrus aurantifolia Nutrition 0.000 description 9
- 235000011941 Tilia x europaea Nutrition 0.000 description 9
- 239000004571 lime Substances 0.000 description 9
- 239000013078 crystal Substances 0.000 description 8
- 230000007547 defect Effects 0.000 description 8
- 239000000969 carrier Substances 0.000 description 7
- 238000005468 ion implantation Methods 0.000 description 7
- 238000010992 reflux Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 229910052734 helium Inorganic materials 0.000 description 4
- 239000001307 helium Substances 0.000 description 4
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 4
- 230000006798 recombination Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000005215 recombination Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000001678 irradiating effect Effects 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 229920006395 saturated elastomer Polymers 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
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- 229910052697 platinum Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0641—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region without components of the field effect type
- H01L27/0647—Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. vertical bipolar transistor and bipolar lateral transistor and resistor
- H01L27/0652—Vertical bipolar transistor in combination with diodes, or capacitors, or resistors
- H01L27/0664—Vertical bipolar transistor in combination with diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
- H01L29/0834—Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
- H01L29/32—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being within the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
Definitions
- the present invention relates to a semiconductor device including a semiconductor layer in which a diode region and an IGBT (Insulated Gate Bipolar Transistor) region are formed.
- IGBT Insulated Gate Bipolar Transistor
- Japanese Unexamined Patent Application Publication Nos. 2009-267394 and 2008-192737 propose a technique for forming a lifetime control region in a semiconductor layer in order to improve reverse recovery characteristics of a diode region.
- the lifetime control region is formed in order to eliminate excess carriers injected when the load current recirculates by recombination and to reduce a reverse recovery charge amount (Qrr) at the time of reverse recovery.
- Japanese Unexamined Patent Application Publication No. 2009-267394 discloses a technique for forming a life lime control region over both the diode region and the IGBT region.
- Japanese Patent Application Laid-Open No. 2008-192737 discloses a technique for selectively forming a life lime control region only in a diode region.
- the technology disclosed in the present specification was created based on the above-described novel knowledge, and aims to improve both the on-voltage and the reverse recovery charge amount (Qrr).
- the semiconductor device disclosed in the present specification has a first lifetime control region located in a diode region and a second lifetime control region located in a part of the IGBT region when viewed in plan.
- the second life lime control region is characterized by extending from the boundary between the diode region and the IGBT region into the IGBT region. More specifically, the second life lime control region is formed so as to overlap with a part of the formation region of the body region of the IGBT region when seen in a plan view. As a result, at least a part of carriers injected via the parasitic diode in the IGBT region can be eliminated by the second lifetime control region, so that an increase in the reverse recovery charge amount (Qrr) can be suppressed. .
- the second lifetime control region is formed in a part of the IGBT region, and is not formed over the entire region of the IGBT region. For this reason, an increase in on-voltage due to the formation of the second lifetime control region can also be suppressed. According to the technology disclosed in this specification, a semiconductor device in which both the on-voltage and the reverse recovery charge amount (Qrr) are improved can be realized.
- FIG. 1 schematically shows a cross-sectional view of an essential part of the semiconductor device of the first embodiment.
- FIG. 2 shows the relationship between the forward voltage of the diode region and the reverse recovery charge amount (Qrr).
- FIG. 3 shows the relationship between the length from the boundary between the diode region and the IGBT region and the amount of reverse recovery charge (Qrr).
- FIG. 4 schematically shows a cross-sectional view of the main part of the semiconductor device of the second embodiment.
- the semiconductor device disclosed in this specification includes a semiconductor layer in which a diode region and an IGBT region are formed.
- the diode region has a p-type anode region formed in the surface layer portion of the semiconductor layer and an n-type cathode region formed in the back layer portion of the semiconductor layer.
- the IGBT region has a p-type body region formed in the surface layer portion of the semiconductor layer and a p-type collector region formed in the back layer portion of the semiconductor layer.
- the range in which the p-type collector region is formed in the back layer portion of the semiconductor layer is defined as the IGBT region. Therefore, the boundary between the diode region and the IGBT region is the boundary between the formation range and the non-formation range of the collector region.
- the n-type cathode region in the diode region and the p-type collector region in the IGBT region are often adjacent. Therefore, the boundary between the diode region and the IGBT region may be a junction surface between the cathode region and the collector region.
- a lifetime control region extending continuously in the horizontal direction of the semiconductor layer is formed in the semiconductor layer.
- the lifetime control area is an area in which the lifetime of the carrier is shorter than the surrounding area.
- the lifetime control region is a region where crystal defects are intentionally formed.
- the lifetime control region includes a first lifetime control region located in the diode region and a second lifetime control region located in a part of the IGBT region when viewed in plan. Have.
- the second lifetime control region extends from the boundary between the diode region and the IGBT region into the IGBT region.
- the tip of the second lifetime control region is located in the formation region of the body region of the IGBT region when viewed in plan.
- the tip of the second lifetime control region is located in a range equal to or greater than the hole diffusion length in the horizontal direction from the boundary between the diode region and the IGBT region.
- the hole diffusion length can be estimated to be about 60 ⁇ m. Therefore, it is desirable that the tip of the second lifetime control region is located in a range of 60 ⁇ m or more in the horizontal direction from the boundary between the diode region and the IGBT region.
- a plurality of trench gates provided through the body region may be formed.
- the tip of the second lifetime control region is located in a range beyond the trench gate provided on the most diode region side when viewed in plan.
- the range beyond the trench gate includes the range below the trench gate.
- the second lifetime control region is formed in the entire region below the body region existing on the diode region side with respect to the trench gate provided on the most diode region side of the IGBT region.
- the tip of the second lifetime control region is located in a range of 500 ⁇ m or less in the horizontal direction from the boundary between the diode region and the IGBT region.
- the effect of reducing the reverse recovery charge amount (Qrr) is saturated even when the second life lime control region is formed to exceed 500 ⁇ m. Therefore, in consideration of an increase in on-voltage, it is desirable that the tip of the second lifetime control region is located in the above range. As a result, a semiconductor device in which both the on-voltage and the reverse recovery charge amount (Qrr) are improved is realized.
- the lifetime control region is formed by irradiation with charged particles, and is formed in a part of a plane of a predetermined depth of the semiconductor layer.
- the semiconductor device 10 includes a semiconductor layer 12 in which a diode region 20 and an IGBT region 40 are mixed.
- the diode region 20 is used as a free wheel diode, and when the IGBT region 40 is off, the load current is circulated.
- the IGBT region 40 may be formed so as to make a round around the diode region 20 when viewed in plan.
- region 40 may be arrange
- the semiconductor device 10 includes a common electrode 60 formed on the back surface of the semiconductor layer 12, and an anode electrode 28 and an emitter electrode 48 formed on the surface of the semiconductor layer 12.
- the common electrode 60 is formed over both the diode region 20 and the IGBT region 40, is a cathode electrode in the diode, and is a collector electrode in the IGBT.
- the anode electrode 28 is formed corresponding to the diode region 20.
- the emitter electrode 48 is formed corresponding to the IGBT region 40. If necessary, the anode electrode 28 and the emitter electrode 48 may be a single common electrode.
- the semiconductor device 10 further includes an n-type cathode region 22, an n-type intermediate region 24, and a p-type anode region 26 at a portion corresponding to the diode region 20 of the semiconductor layer 12.
- the cathode region 22 is formed in the back layer portion of the semiconductor layer 12 using, for example, an ion implantation technique.
- the cathode region 22 has a high impurity concentration and is in ohmic contact with the common electrode 60.
- the intermediate region 24 is provided between the cathode region 22 and the anode region 26.
- the intermediate region 24 includes a low concentration intermediate region 24a and a buffer region 24b.
- the low concentration intermediate region 24a and the buffer region 24b have different impurity concentrations, and the impurity concentration of the low concentration intermediate region 24a is lower than that of the buffer region 24b.
- the low-concentration intermediate region 24a is a remaining portion where other regions are formed in the semiconductor layer 12, and the impurity concentration is constant in the thickness direction.
- the buffer region 24b is formed by using, for example, an ion implantation technique.
- the anode region 26 is formed in the surface layer portion of the semiconductor layer 12 using, for example, an ion implantation technique.
- the anode region 26 includes a plurality of high concentration anode regions 26a and a low concentration anode region 26b surrounding the plurality of high concentration anode regions 26a.
- the plurality of high concentration anode regions 26 a are arranged in a distributed manner in the surface layer portion of the semiconductor layer 12.
- the plurality of high concentration anode regions 26 a have a high impurity concentration and are in ohmic contact with the anode electrode 28.
- the impurity concentration of the low concentration anode layer 26b is thinner than that of the high concentration anode region 26a.
- the position of the lower end of the anode region 26 is shallower than the position of the lower end of a trench gate 52 described later.
- the low concentration anode region 26b may be provided only between the adjacent high concentration anode regions 26a.
- Various forms of the anode region 26 can be adopted depending on the characteristics desired for the diode region 20.
- the semiconductor device 10 further includes a p-type collector region 42, an n-type drift region 44, a p-type body region 46, and an n-type emitter region 47 at portions corresponding to the IGBT region 40 of the semiconductor layer 12. I have.
- the collector region 42 is formed in the back layer portion of the semiconductor layer 12 using, for example, an ion implantation technique.
- the collector region 42 has a high impurity concentration and is in ohmic contact with the common electrode 60.
- the collector region 42 of the IGBT region 40 and the cathode region 22 of the diode region 20 are located at substantially the same depth of the semiconductor layer 12 and are adjacent to the semiconductor layer 12 in the horizontal direction.
- the junction surface between the collector region 42 and the cathode region 22 is a boundary between the diode region 20 and the IGBT region 40.
- the drift region 44 is provided between the collector region 42 and the body region 46.
- the drift region 44 includes a low concentration drift region 44a and a buffer region 44b.
- the low concentration drift region 44a and the buffer region 44b have different impurity concentrations, and the impurity concentration of the low concentration drift region 44a is lower than that of the buffer region 44b.
- the low concentration drift region 44a is a remaining portion in which other regions are formed in the semiconductor layer 12, and the impurity concentration is constant in the thickness direction.
- the buffer region 44b is formed by using, for example, an ion implantation technique.
- the body region 46 is formed in the surface layer portion of the semiconductor layer 12 using, for example, an ion implantation technique.
- the body region 46 includes a plurality of body contact regions 46a and a low concentration body region 46b surrounding the body contact region 46a.
- the body contact regions 46 a are arranged in a distributed manner on the surface layer portion of the semiconductor layer 12.
- the plurality of body contact regions 46 a have a high impurity concentration and are in ohmic contact with the emitter electrode 48.
- the impurity concentration of the low concentration body region 46b is lower than that of the plurality of body contact regions 46a.
- the plurality of emitter regions 47 are formed in the surface layer portion of the semiconductor layer 12 using, for example, an ion implantation technique.
- the plurality of emitter regions 47 are distributed in the surface layer portion of the semiconductor layer 12.
- the plurality of emitter regions 47 have a high impurity concentration and are in ohmic contact with the emitter electrode 48.
- the semiconductor device 10 further includes a plurality of trench gates 52 formed at portions corresponding to the IGBT regions 40.
- the plurality of trench gates 52 are distributed in the surface layer portion of the semiconductor layer 12.
- the trench gate 52 includes a trench gate electrode 54 and a gate insulating film 56 that covers the trench gate electrode 54.
- the trench gate 52 extends from the front surface to the back surface of the semiconductor layer 12 and extends through the body region 46.
- the trench gate 52 is in contact with the emitter region 47, the low concentration body region 46b, and the low concentration drift region 44a.
- the trench gate electrode 54 is insulated from the emitter electrode 48 by the insulating film 58.
- the semiconductor device 10 further includes a lifetime control region 39 formed at a predetermined depth of the semiconductor layer 12.
- the lifetime control region 39 is formed in a part of the surface of the semiconductor layer 12 at a predetermined depth.
- the lifetime control region 39 includes a first lifetime control region 39A that is continuously formed along the horizontal direction in the entire range of the diode region 20 when viewed in plan.
- the lifetime control region 39 further includes a second lifetime control region 39B formed continuously in the horizontal direction in a part of the IGBT region 40 when viewed in plan.
- the first lifetime control region 39A of the diode region 20 and the second lifetime control region 39B of the IGBT region 40 are continuous at the boundary between the diode region 20 and the IGBT region 40.
- the second lifetime control region 39B of the IGBT region 40 extends from the boundary between the diode region 20 and the IGBT region 40 into the IGBT region 40. More specifically, the tip 39a of the second lifetime control region 39B is located in the formation range of the body region 46 of the IGBT region 40 when viewed in plan. Further, the tip 39a of the second lifetime control region 39B is located in a range exceeding the body contact region 46a closest to the diode region 20 of the IGBT region 40 when viewed in plan. Furthermore, the tip 39a of the second lifetime control region 39B is located in a range beyond the trench gate 52 on the diode region 20 side of the IGBT region 40 when viewed in plan.
- the lifetime control region 39 is formed in the low concentration intermediate region 24a in the diode region 20, and is formed in the low concentration drift region 44a in the IGBT region 40. More specifically, the first lifetime control region 39A of the diode region 20 is formed on the low concentration intermediate region 24a side of the joint surface between the low concentration intermediate region 24a and the low concentration anode region 26b. The second lifetime control region 39B of the IGBT region 40 is formed on the low concentration drift region 44a side of the joint surface between the low concentration drift region 44a and the low concentration body region 46b.
- the lifetime control region 39 can be formed using various known methods.
- the semiconductor layer 12 is irradiated with helium (He), and the lifetime control region 39 is formed at a predetermined depth.
- the lifetime control region 39 may be formed by irradiating the semiconductor layer 12 with other charged particles.
- the lifetime control region 39 may be formed by irradiating the semiconductor layer 12 with an electron beam.
- the lifetime control region 39 may be formed by diffusing heavy metal such as gold or platinum in the semiconductor layer 12.
- the lifetime control region 39 includes a larger amount of crystal defects than the surrounding due to damage caused by irradiation with helium.
- the crystal defect density of the lifetime control region 39 has a peak at a predetermined depth of the semiconductor layer 12, and is higher than the crystal defect density of the surrounding low concentration intermediate region 24a and low concentration drift region 44a. For this reason, the lifetime control region 39 can provide a field where electrons and holes are recombined.
- the semiconductor device 10 is used as one of six transistors constituting a vehicle-mounted three-phase inverter circuit, and is connected to an AC motor (not shown).
- a reflux current flows toward the AC motor via the diode region 20 when the IGBT region 40 is off.
- the diode region 20 is in a forward bias state
- the anode electrode 28 is at a high potential
- the common electrode 60 is at a low potential. Therefore, a large amount of holes are injected from the anode region 26 toward the low concentration intermediate region 24a.
- the reflux current is cut off.
- the anode electrode 28 in the diode region 20 is at a low potential, and the common electrode 60 is at a high potential.
- the holes injected into the low concentration intermediate region 24 a by the reflux current start to flow in the reverse direction toward the anode region 26. This phenomenon is observed as a reverse recovery current.
- the product of the magnitude of the reverse recovery current and the duration is the reverse recovery charge amount (Qrr). It is important to suppress the reverse recovery charge amount (Qrr) to reduce power loss.
- the first lifetime control region 39 ⁇ / b> A is formed over the entire diode region 20. Since the first lifetime control region 39A has a crystal defect, it functions as a carrier recombination center. For this reason, in the diode region 20, excess holes injected by the reflux current disappear due to recombination in the first lifetime control region 39A.
- the anode electrode 28 when the reflux current is flowing, the anode electrode 28 is at a high potential and the common electrode 60 is at a low potential. In the semiconductor device 10, the anode electrode 28 and the emitter electrode 48 are short-circuited and used. Therefore, when the anode electrode 28 is at a high potential, the emitter electrode 48 is also at a high potential. As shown in FIG. 1, a parasitic diode exists between the body region 46 and the drift region 44 in the IGBT region 40. Most of the parasitic diodes do not operate because the p-type collector region 42 is provided in the back layer portion.
- the parasitic diode existing near the boundary between the diode region 20 and the IGBT region 40 operates when the forward voltage of the diode region 20 increases.
- the crystal defect density in the lifetime control region 39 is increased, the forward voltage of the diode region 20 when the return current flows is increased.
- the parasitic diode existing near the boundary between the diode region 20 and the IGBT region 40 is forward-biased.
- the semiconductor device 10 is characterized in that measures are also taken against parasitic diodes existing in the vicinity of this boundary.
- the second lifetime control region 39 ⁇ / b> B is formed in a part of the IGBT region 40. For this reason, the holes injected through the parasitic diode in the IGBT region 40 disappear due to recombination in the second lifetime control region 39B. For this reason, in the semiconductor device 10, the reverse recovery charge amount (Qrr) is suppressed from increasing due to holes injected through the parasitic diode in the IGBT region 40.
- FIG. 2 shows the relationship between the forward voltage (Vf) applied to the diode region 20 and the reverse recovery charge amount (Qrr). This shows a case where the larger the forward voltage (Vf) is, the more crystal defects are included in the lifetime control region 39 and the greater the irradiation amount of helium when the lifetime control region 39 is formed.
- the conventional structure in the figure is an example in which the lifetime control region 39 is formed only in the diode region 20 and the lifetime control region 39 is not formed in the IGBT region 40.
- 100, 200, 300, 500 and 800 ⁇ m in the figure indicate the lengths of the second lifetime region 39B extending from the boundary between the diode region 20 and the IGBT region 40 into the IGBT region 40, respectively.
- the reverse recovery charge (Qrr) is smaller than that of the conventional structure in any of the present examples in which the second lifetime control region 39B is formed in a part of the IGBT region 40.
- the reverse recovery charge amount (Qrr) increases in the conventional structure, whereas in this embodiment, the reverse recovery charge amount (Qrr) in both cases. Is decreasing. This is because, by forming the second lifetime control region 39B in a part of the IGBT region 40, the holes injected through the parasitic diode in the IGBT region 40 are favorably eliminated, thereby the reverse recovery charge amount. This shows that the increase in (Qrr) could be prevented.
- FIG. 3 shows the relationship between the length of the lifetime region 39 extending from the boundary between the diode region 20 and the IGBT region 40 toward the IGBT region 40 and the amount of reverse recovery charge (Qrr). Regardless of the amount of helium irradiation when forming the lifetime control region 39, it was confirmed that the reverse recovery charge (Qrr) reduction effect was saturated in any example when the length from the boundary exceeded 500 ⁇ m. .
- the semiconductor device 10 by forming the second lifetime control region 39 ⁇ / b> B in a part of the IGBT region 40, at least a part of holes injected through the parasitic diode in the IGBT region 40 is obtained. It can be eliminated by the second lifetime control region 39B formed in the IGBT region 40. Thereby, an increase in the reverse recovery charge amount (Qrr) can be suppressed. Further, the second lifetime control region 39B is formed in a part of the IGBT region 40 and is not formed over the entire region of the IGBT region 40. For this reason, an increase in on-voltage due to the formation of the second lifetime control region 39B can also be suppressed. In the semiconductor device 10, both the on-voltage and the reverse recovery charge amount (Qrr) are improved.
- the semiconductor device 100 is characterized in that a p-type isolation region 72 is formed in the vicinity of the boundary between the diode region 20 and the IGBT region 40.
- the isolation region 72 is formed in the surface layer portion of the semiconductor layer 12.
- the isolation region 72 is formed deeper than the lower end of the anode region 26 and the lower end of the body region 46. More specifically, the isolation region 72 is formed deeper from the upper surface of the semiconductor layer 12 than the lower end of the trench gate. Further, the separation region 72 is in contact with both the anode region 26 and the body region 46.
- the impurity concentration of the isolation region 72 is higher than that of the low concentration anode region 26b and the low concentration body region 46b.
- the isolation region 72 extends a depletion layer toward the low-concentration intermediate region 24a and the low-concentration drift region 44a when the IGBT region 40 is off, and suppresses electric field concentration near the boundary between the diode region 20 and the IGBT region 40. To do. In particular, since the isolation region 72 is formed deeper than the trench gate, electric field concentration in the trench gate near the isolation region 72 is suppressed.
- the semiconductor device 100 is characterized in that the lifetime control region 39 is also formed at the lower end of the separation region 72.
- the isolation region 72 also constitutes a parasitic diode. For this reason, in the semiconductor device having the isolation region 72, when the parasitic diode of the isolation region 72 is forward-biased, the reverse recovery charge amount (Qrr) increases.
- the lifetime control region 39 is also formed at the lower end of the isolation region 72, holes injected through the parasitic diode in the isolation region 72 can be eliminated well.
- the second lifetime control region 39B is formed below the body region 46 of the IGBT 40, the holes injected through the parasitic diode in the body region 46 are also well lost. Can be made.
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Abstract
Description
本発明は、ダイオード領域とIGBT(Insulated Gate Bipolar Transistor)領域が形成されている半導体層を備える半導体装置に関する。
図1に示されるように、半導体装置10は、ダイオード領域20とIGBT領域40が混在した半導体層12を備えている。半導体装置10では、ダイオード領域20がフリーホイールダイオードとして利用されており、IGBT領域40がオフのときに、負荷電流を還流させる。一例では、IGBT領域40は、平面視したときに、ダイオード領域20の周囲を一巡するように形成されていてもよい。あるいは、ダイオード領域20とIGBT領域40は、平面視したときに、一方向に並んで隣接して配置されていてもよい。
図4に示されるように、半導体装置100は、ダイオード領域20とIGBT領域40の境界近傍に、p型の分離領域72が形成されていることを特徴としている。分離領域72は、半導体層12の表層部に形成されている。分離領域72は、アノード領域26の下端及びボディ領域46の下端よりも深く形成されている。より詳細には、分離領域72は、半導体層12の上面からトレンチゲートの下端よりも深く形成されている。また、分離領域72は、アノード領域26とボディ領域46の双方に接している。分離領域72の不純物濃度は、低濃度アノード領域26b及び低濃度ボディ領域46bよりも濃い。分離領域72は、IGBT領域40がオフしているときに、低濃度中間領域24a及び低濃度ドリフト領域44aに向けて空乏層を伸ばし、ダイオード領域20とIGBT領域40の境界近傍の電界集中を抑制する。特に、分離領域72がトレンチゲートよりも深く形成されているので、分離領域72近傍のトレンチゲートにおける電界集中が抑制される。
本明細書または図面に説明した技術要素は、単独であるいは各種の組み合わせによって技術的有用性を発揮するものであり、出願時の請求項に記載の組み合わせに限定されるものではない。また、本明細書または図面に例示した技術は複数の目的を同時に達成するものであり、そのうちの一つの目的を達成すること自体で技術的有用性を持つものである。
Claims (4)
- 半導体装置であって、
ダイオード領域とIGBT領域が形成されている半導体層を備えており、
前記ダイオード領域は、前記半導体層の表層部に形成されているp型のアノード領域と、前記半導体層の裏層部に形成されているn型のカソード領域を有しており、
前記IGBT領域は、前記半導体層の表層部に形成されているp型のボディ領域と、前記半導体層の裏層部に形成されているp型のコレクタ領域を有しており、
前記半導体層には、前記半導体層の水平方向に連続して伸びているライフタイム制御領域が形成されており、
前記ライフタイム制御領域は、平面視したときに、前記ダイオード領域に位置する第1ライフライム制御領域と、前記IGBT領域の一部に位置する第2ライフタイム制御領域を有しており、
前記第2ライフタイム制御領域は、前記ダイオード領域と前記IGBT領域の境界から前記IGBT領域内に向けて伸びており、
前記第2ライフタイム制御領域の先端が、平面視したときに、前記IGBT領域の前記ボディ領域の形成範囲に位置する半導体装置。 - 前記第2ライフタイム制御領域の先端が、前記境界から前記水平方向において60μm以上の範囲に位置する請求項1に記載の半導体装置。
- 前記ボディ領域を貫通して設けられている複数のトレンチゲートが形成されており、
前記第2ライフタイム制御領域の先端が、平面視したときに、最も前記ダイオード領域側に設けられている前記トレンチゲートを超えた範囲に位置する請求項1又は2に記載の半導体装置。 - 前記第2ライフタイム制御領域の先端が、前記境界から前記水平方向において500μm以下の範囲に位置する請求項1~3のいずれか一項に記載の半導体装置。
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DE112010002017.5T DE112010002017B4 (de) | 2010-04-02 | 2010-06-28 | Halbleitervorrichtung |
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KR101544332B1 (ko) | 2011-08-30 | 2015-08-12 | 도요타 지도샤(주) | 반도체 장치 |
JP2013197122A (ja) * | 2012-03-15 | 2013-09-30 | Toshiba Corp | 半導体装置 |
JP6078961B2 (ja) * | 2012-03-19 | 2017-02-15 | 富士電機株式会社 | 半導体装置の製造方法 |
JP6073092B2 (ja) * | 2012-09-07 | 2017-02-01 | 株式会社 日立パワーデバイス | ダイオード及び電力変換システム、並びにダイオードの製造方法 |
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JP2015018951A (ja) * | 2013-07-11 | 2015-01-29 | 株式会社東芝 | 半導体装置 |
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JP6421570B2 (ja) * | 2013-12-20 | 2018-11-14 | 株式会社デンソー | 半導体装置 |
JP6158123B2 (ja) * | 2014-03-14 | 2017-07-05 | 株式会社東芝 | 半導体装置 |
JP6277814B2 (ja) * | 2014-03-25 | 2018-02-14 | 株式会社デンソー | 半導体装置 |
JP6181597B2 (ja) * | 2014-04-28 | 2017-08-16 | トヨタ自動車株式会社 | 半導体装置及び半導体装置の製造方法 |
JP2016029685A (ja) * | 2014-07-25 | 2016-03-03 | 株式会社東芝 | 半導体装置 |
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JP6384425B2 (ja) * | 2015-08-21 | 2018-09-05 | 株式会社デンソー | 半導体装置 |
JP6443267B2 (ja) * | 2015-08-28 | 2018-12-26 | 株式会社デンソー | 半導体装置 |
JP6531589B2 (ja) | 2015-09-17 | 2019-06-19 | 株式会社デンソー | 半導体装置 |
CN105552112B (zh) * | 2015-12-03 | 2018-09-21 | 厦门元顺微电子技术有限公司 | 一种绝缘栅双极晶体管及其制造方法 |
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JP6560142B2 (ja) * | 2016-02-26 | 2019-08-14 | トヨタ自動車株式会社 | スイッチング素子 |
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JP6665713B2 (ja) * | 2016-06-28 | 2020-03-13 | トヨタ自動車株式会社 | 半導体装置 |
DE112017005529B4 (de) * | 2016-11-01 | 2024-03-14 | Mitsubishi Electric Corporation | Siliciumcarbid-halbleitereinheit und leistungswandlereinheit |
JP2018092968A (ja) | 2016-11-30 | 2018-06-14 | ルネサスエレクトロニクス株式会社 | 半導体装置、rc−igbt及び半導体装置の製造方法 |
WO2019013286A1 (ja) | 2017-07-14 | 2019-01-17 | 富士電機株式会社 | 半導体装置 |
JP6909666B2 (ja) * | 2017-07-27 | 2021-07-28 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
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US11183387B2 (en) * | 2018-04-11 | 2021-11-23 | Mitsubishi Electric Corporation | Semiconductor device, semiconductor wafer and method for manufacturing semiconductor device |
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