WO2010034194A1 - 多层电路板及其制作方法和通信设备 - Google Patents

多层电路板及其制作方法和通信设备 Download PDF

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Publication number
WO2010034194A1
WO2010034194A1 PCT/CN2009/071450 CN2009071450W WO2010034194A1 WO 2010034194 A1 WO2010034194 A1 WO 2010034194A1 CN 2009071450 W CN2009071450 W CN 2009071450W WO 2010034194 A1 WO2010034194 A1 WO 2010034194A1
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WO
WIPO (PCT)
Prior art keywords
sub
circuit board
conducting block
board
heat conducting
Prior art date
Application number
PCT/CN2009/071450
Other languages
English (en)
French (fr)
Inventor
黄明利
张顺
杨曦晨
赵俊英
罗兵
李志海
汪国亮
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP18195346.4A priority Critical patent/EP3457823A1/en
Priority to EP09815564A priority patent/EP2227076A4/en
Priority to EP14179125.1A priority patent/EP2822369B1/en
Publication of WO2010034194A1 publication Critical patent/WO2010034194A1/zh
Priority to US12/767,634 priority patent/US8330051B2/en

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203—Cooling of mounted components
    • H05K1/0204—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate
    • H05K1/0206—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate by printed thermal vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203—Cooling of mounted components
    • H05K1/0204—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/0929—Conductive planes
    • H05K2201/09309—Core having two or more power planes; Capacitive laminate of two power planes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09554—Via connected to metal substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10416—Metallic blocks or heatsinks completely inserted in a PCB
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/06—Lamination
    • H05K2203/063—Lamination of preperforated insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.

Definitions

  • Multilayer circuit board manufacturing method thereof and communication device
  • the application date is September 28, 2008, and the application number is 200810216597. 8.
  • the application name is 200910005975. 2, the title of which is the priority of the Chinese patent application of the present invention, the entire disclosure of which is incorporated herein by reference.
  • the present invention relates to the field of electronic communication technologies, and in particular, to a multilayer circuit board, a manufacturing method thereof, and a communication device. Background technique
  • circuit boards are becoming more and more widely used, and electronic devices are assembled on circuit boards for operation, such as: power tube, QFN (quad flat non-leaded package) , BGA (ball grid array), CSP (chip scale package), QFP (quad flat package), etc., with the increasing number of electronic devices on the board, The issue of heat dissipation is becoming more and more important.
  • Embodiments of the present invention provide a circuit board having a heat conductive block, a manufacturing method thereof, and a communication device, which embed the heat conductive block when the circuit board is pressed, thereby simplifying the assembly process of the heat conductive block.
  • a method of making a multilayer circuit board comprising:
  • At least one sub-board is opened, and a stage slot is formed to form a first sub-board;
  • the sub-board includes the first sub-board, the first sub-board being placed in such a manner that the set phase slots are connected, the stage slots are connected Forming a receiving groove, placing a heat conducting block in the receiving groove, the dielectric layer being located between the daughter boards;
  • the stacked sub-boards, dielectric layers, and thermally conductive blocks are pressed together, and the laminated sub-boards and thermally conductive blocks are formed into a multilayer circuit board.
  • a multi-layer circuit board comprising: a heat conducting block, and a plurality of sub-boards and a dielectric layer stacked together, the sub-board comprising a first sub-board, the first sub-board being provided with a stage slot, a plurality of The stage slots of the first sub-board are connected to form a receiving slot, and the heat conducting block is received in the receiving slot, and the dielectric layer is located between the daughter boards.
  • a communication device comprising at least one multi-layer circuit board, the multi-layer circuit board comprising: a thermal block, and a plurality of sub-boards and dielectric layers stacked together, the sub-board comprising a first sub-board, The first sub-board is provided with a stage slot, and the plurality of the first sub-boards are connected to each other to form a receiving slot. The heat conducting block is received in the receiving slot, and the dielectric layer is located in the sub-board. between.
  • the assembly process of the thermal block is simplified by embedding the thermally conductive block when the circuit board is pressed.
  • FIG. 1 is a schematic view of a daughter board in an embodiment of a method for fabricating a multilayer circuit board of the present invention
  • FIG. 2 is a schematic view of an embodiment of a method for fabricating a multilayer circuit board of the present invention
  • 3 is a schematic view showing another embodiment of a method for fabricating a multilayer circuit board according to the present invention
  • 4 is a schematic view of an embodiment of a multilayer circuit board of the present invention
  • Figure 5 is a schematic view showing another embodiment of the multilayer circuit board of the present invention.
  • FIG. 6 is a schematic view showing a first embodiment of a plurality of accommodating slots of a multilayer circuit board according to the present invention
  • FIG. 7 is a schematic view showing a second embodiment of a plurality of accommodating slots of a multilayer circuit board according to the present invention
  • FIG. 9 is a schematic view showing an embodiment of a heat conducting block of a multilayer circuit board of the present invention
  • FIG. 9 is a schematic view showing a third embodiment of a multilayer circuit board of the present invention.
  • Figure 10 is a schematic illustration of another embodiment of a thermally conductive block of a multilayer circuit board of the present invention.
  • Figure 11 is a top plan view showing still another embodiment of the heat conducting block of the multilayer circuit board of the present invention.
  • Figure 12 is a schematic view showing still another embodiment of the heat conducting block of the multilayer circuit board of the present invention.
  • the present invention provides an embodiment of a method for fabricating a multi-layer circuit board, comprising: step 201, at least one sub-board 2, opening a stage slot 20 to form a first sub-board 21;
  • Step 202 stacking at least one sub-board 2 with the dielectric layer 3, wherein the sub-board 2 includes the first sub-board 21, the first sub-board 21 to make the set stage slot 20 Placed in a continuous manner, the stage slots 20 are connected to form a receiving slot 6, the heat conducting block 7 is placed in the receiving slot 6, the dielectric layer 3 is located between the daughter boards 2;
  • Step 203 pressing the stacked sub-board 2, the dielectric layer 3, and the thermal block 7 together, and forming the laminated sub-board and the thermal block into a multi-layer circuit board.
  • the heat conducting block is buried in the circuit board when the daughter board is pressed, the process flow is simple, and the assembly efficiency of the heat conducting block is improved.
  • the heat conducting block in step 203, after the pressing, the heat conducting block is lower or flush with the surface of the circuit board, and may even be higher than the surface of the circuit board.
  • the sub-board may include a first sub-board 21 and a second sub-board 22 not provided with a stage slot.
  • the second sub-board 22 is located at one end or both ends of the accommodating groove 6.
  • the implementation of the present invention may further include a step 204, on the side of the heat conducting block, a heat conducting hole 8 connected to the heat conducting block; and a heat conducting hole may be drilled elsewhere in the multilayer circuit board 8.
  • the medium layer is located between the adjacent sub-boards, and includes:
  • the dielectric layer 3 is located between the two first sub-boards 21, and a stage slot is also opened between the two stages of the first sub-board 21; or, the dielectric layer 3 is located at two Between the second sub-boards 22; or, the dielectric layer 3 is located between the first sub-board 21 and the second sub-board 22, and the dielectric layer 3 is provided with a stage slot, the medium a stage slot of the layer, communicating with the stage slot 20 of the first sub-board 21; or, the dielectric layer 3 is located between the first sub-board 21 and the second sub-board 22, the dielectric layer 3 There is no stage slot.
  • the heat conducting hole 8 is connected to the heat conducting block 7 and the electronic device 91, or the heat conducting block 7 and the surface of the circuit board are connected. Or connecting the heat conducting block 7, the electronic device 91, and the surface of the circuit board, or connecting the heat conducting block 7, the electronic device 91, and a heat sink member embedded inside the circuit board.
  • the heat conducting hole 8 can transfer the heat of the electronic device 91 to the heat conducting block 7; or transfer the heat in the heat conducting block 7 to the surface of the circuit board, or transfer the heat of the electronic device 91 to the heat conducting block 7, and then conduct heat
  • the heat in block 7 is transferred to the surface of the board (the arrows in Figures 4 and 5 indicate the heat transfer path), or the heat of the electronic device 91 is transferred to the heat conducting block 7, and the heat in the heat conducting block 7 is transferred to Radiator parts.
  • the heat generated by the electronic device is transferred through the heat conducting block in the circuit board, thereby reducing the thermal resistance and improving the local heat dissipation capability of the circuit board.
  • the heat conducting hole may be filled with electroplating, or inserted into a conductive silver paddle or the like to improve the heat dissipating effect, or the heat conducting hole may further contain a heat conducting liquid.
  • Thermal fluid The body can be: water or oil or silicone oil.
  • the heat conducting block is made of a material having a higher thermal conductivity than the circuit board medium, such as copper, or aluminum, or a metal alloy; and the heat conducting block may also be a cavity containing a heat conducting liquid.
  • the heat transfer liquid can flow out through the heat conduction hole.
  • the shape of the heat conducting block may be a regular cylindrical shape, a spherical shape or a tapered shape; or may be an irregular three-dimensional shape.
  • the shape of the accommodating groove is matched with the shape of the heat conducting block, so that the heat conducting block can be accommodated in the accommodating groove, and the slab is not pressed by the heat conducting block because the accommodating groove is too large.
  • the sub-boards may all be the first sub-board, and the heat-conducting block 7 is disposed after the accommodating slot, and the two ends are located on the outer surface of the multi-layer circuit board.
  • the end face of the heat conducting block 7 is flush with the surface of the circuit board, or higher than the surface of the circuit board, or lower than the surface of the circuit board.
  • the heat conducting block 7 includes a main body 71 and a connecting body 72 fixedly connected to the main body 71.
  • the cross-sectional area of the connecting body 72 is smaller than the cross-sectional area of the main body 71.
  • the shape of the slot is matched to the heat conducting block.
  • the main body 71 and the connecting body 72 may be integrally provided, that is, form a unitary structure.
  • the connecting body 72 at the top of the heat conducting block 7 has a small cross-sectional area, and the connecting body 72 can be connected to the heat dissipating disk at the bottom of the electronic device through the bismuth tin, and the main body 71 at the bottom of the heat conducting block 7 is cut off.
  • the area is large, and it is in contact with the bottom of the circuit or the substrate of the circuit, that is, the thermal resistance of the stepped heat conduction block is much smaller than that of the via hole, so that the contact area can be fully ensured and the contact resistance can be reduced.
  • the main body 71 has a shoulder 711 at a position corresponding to the coupling body 72.
  • the shoulder 711 is parallel to the surface of the sub-board 21, and the shoulder 711 is preferably located on the lower surface of the dielectric layer 3.
  • the connecting body may be a whole, as shown in FIG. 9; or has two or more connecting bodies 721, each connecting body 721 is separately provided, and each connecting body 721 is connected with the main body 71, as shown in FIG. Two of the connecting bodies 721 are fixedly connected above the main body 71 in a single, parallel, and spaced manner.
  • the connecting body 72 can be designed into any shape according to the requirements of electrical performance, which is a regular or irregular shape, as shown in FIG.
  • the connecting body 72 may also be stepped as needed, so that the heat conducting block has a plurality of steps in the height direction.
  • the heat conducting block 7 further includes a connecting member 73.
  • the connecting member 73 is fixedly connected under the main body 71, and the cross-sectional area of the connecting member 73 is smaller than that.
  • the cross-sectional area of the main body 71 is smaller than that.
  • the upper and lower surfaces of the multilayer circuit board are respectively provided with a plating layer 9, and the height of the heat conducting block is preferably flush with the height of the multilayer circuit board to make heat conduction.
  • Block 7 is in contact with the two plating layers 4 to form a heat transfer path.
  • a plurality of the first sub-boards in the embodiment of the present invention can be combined into multiple stages by adjusting the order of stacking or opening the stage slots at different positions. Or a plurality of stage slots may be opened at different positions of the first sub-board, and the plurality of stage slots are respectively connected to the stage slots of the other first sub-boards to form a plurality of receiving slots. 6.
  • a heat conducting hole may be disposed between the plurality of receiving slots 6.
  • the plurality of accommodating grooves 6 may be arranged side by side, vertically arranged vertically, or vertically arranged upside down.
  • the cross-sectional shapes of the stage grooves of the plurality of sub-boards may be the same or different, and the cross-sectional areas may be the same or different.
  • the dielectric layer may be: a low flow adhesive B-stage PrePreg (low flow adhesive B state prepreg), or a low flow adhesive B-stage Prepreg combined with a C-Stage Prepreg (low flow adhesive B state)
  • the prepreg is combined with the C-state cured sheet); the dielectric layer has a ductile property and can absorb the height error of the heat-conducting block, which is beneficial to ensure the flatness of the surface of the multilayer circuit board; of course, the dielectric layer can also be other bonding medium. As shown in FIG.
  • the sub-board may be composed of at least one inner core board 28, wherein in the case where the sub-board has a plurality of inner core sheets 28, a plurality of inner layers
  • the core plates 28 are pressed together, and the dielectric layers 27 are filled between the adjacent inner core plates 28.
  • the outer layers of the inner core plates 28 may further include a pattern layer 29, the graphic layer 29 and the inner core.
  • a dielectric layer 27 is filled between the plates 28.
  • the outer layer of the sub-board may be an inner core board or a separate pattern layer, because the sub-board is to be composed of a multi-layer board in the future, so the sub-layer is located at the outermost layer of the multi-layer board.
  • the plate may have a graphic layer on only one side surface facing inward. It should be noted that the graphic layer of the inward side surface of the sub-board may be a separate graphic layer or a graphic layer of the inner core plate.
  • the outwardly facing side surface of the sub-board of the outermost layer of the multi-layer board may or may not have a pattern layer. It should be noted that the pattern layer of the outward-facing side surface of the sub-board may be separate.
  • the graphics layer is either the graphics layer of the inner core board.
  • the graphics layer is either the graphics layer of the inner core board.
  • the storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM). According to the above embodiment, as shown in FIG. 2 or FIG.
  • the present invention further provides an embodiment of a multilayer circuit board, comprising: a heat conducting block 7, and a plurality of sub-boards 2 and dielectric layers 3 stacked together,
  • the sub-board 2 includes the first sub-board 21, the first sub-board 21 is provided with a stage slot 20, and the plurality of stage slots 20 of the first sub-board 21 are connected to form a receiving slot 6, the heat-conducting block 7 is accommodated in the accommodating groove 6, and the dielectric layer 3 is located between the sub-boards 2.
  • heat generated by the electronic device is transferred through the heat conducting block in the circuit board, thereby reducing thermal resistance and improving local heat dissipation capability of the circuit board.
  • the heat conducting block is lower or flush with the surface of the circuit board, and may even The surface of the circuit board is based on the above embodiment.
  • the present invention further provides an embodiment of a communication device, comprising: at least one multi-layer circuit board, the multi-layer circuit board comprising: a block 7 and a plurality of sub-boards 2 and a dielectric layer 3 stacked together, the sub-board 2 includes the first sub-board 21, and the first sub-board 21 is provided with a stage slot 20, and the plurality of The stage slots 20 of a sub-board 21 are connected to form a receiving slot 6 .
  • the heat conducting block 7 is received in the receiving slot 6
  • the dielectric layer 3 is located between the sub-boards 2 .
  • heat generated by the electronic device is transferred through the heat conducting block in the circuit board, thereby reducing thermal resistance and improving local heat dissipation capability of the circuit board.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Structure Of Printed Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Cooling Or The Like Of Electrical Apparatus (AREA)

Description

多层电路板及其制作方法和通信设备
本申请要求申请日为 2008年 9月 28日， 申请号为 200810216597. 8，发明 名称为 "一种多层电路板及其制作方法"的中国专利申请； 以及申请日为 2009 年 1月 22日， 申请号为 200910005975. 2， 发明名称为 "多层电路板及其制作 方法和通信设备"的中国专利申请的优先权， 其全部内容通过引用结合在本申 请中。
技术领域
本发明涉及电子通信技术领域，特别涉及一种多层电路板及其制作方法和 通信设备。 背景技术
随着电子产业的蓬勃发展， 电路板应用的越来越广泛， 电子器件多组装在 电路板上进行运行， 例如： 功率管、 QFN ( quad flat non-leaded package,四 侧无引脚扁平封装）、 BGA (ball grid array, 球形触点陈列）、 CSP (chip scale package，芯片尺寸封装）、 QFP (quad flat package,四侧引脚扁平封装）等， 随 着电路板上的电子器件不断增多， 散热问题变得越来越重要。
对功率较大的电子器件， 目前多采用通过在电路板局部嵌入金属衬底的方 式， 对电子器件进行散热。
发明人在实现本发明的过程中， 发现现有技术至少存在以下缺点： 局部金属衬底需要单独组装， 增加了工艺流程， 还需要辅助工装， 影响生 产效率。 发明内容
本发明实施例提供一种具有导热块的电路板及其制作方法和通信设备， 通 过在电路板压合时嵌入导热块， 从而简化了导热块的组装过程。
本发明的实施例采用如下技术方案： 一种制作多层电路板的方法， 其包括：
将至少一个子板， 开设阶段槽， 形成第一子板；
将至少一个子板与介质层叠放在一起，其中，所述子板包括所述第一子板， 所述第一子板以使所述设置的阶段槽连通的方式放置，所述阶段槽连通后形成 容置槽， 将导热块放置在所述容置槽内， 所述介质层位于所述子板之间；
将所述叠放在一起的子板， 介质层， 以及导热块进行压合， 并将所述压合 在一起的子板和导热块制成多层电路板。
一种多层电路板，其包括： 导热块， 以及叠放在一起的多个子板和介质层， 所述子板包括第一子板， 所述第一子板开设有阶段槽， 多个所述第一子板的阶 段槽连通形成容置槽， 所述导热块容设在所述容置槽内， 所述介质层位于所述 子板之间。
一种通信设备， 其包括至少一个多层电路板， 所述多层电路板包括： 导热 块， 以及叠放在一起的多个子板和介质层， 所述子板包括第一子板， 所述第一 子板开设有阶段槽， 多个所述第一子板的阶段槽连通形成容置槽， 所述导热块 容设在所述容置槽内， 所述介质层位于所述子板之间。
上述技术方案中具有如下的优点：
在本发明的实施例中， 通过在电路板压合时嵌入导热块， 从而简化了导热 块的组装过程。 附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案， 下面将对实施 例或现有技术描述中所需要使用的附图作简单地介绍， 显而易见地， 下面描述 中的附图仅仅是本发明的一些实施例， 对于本领域普通技术人员来讲， 在不付 出创造性劳动的前提下， 还可以根据这些附图获得其他的附图。
图 1为本发明多层电路板制作方法的实施例中， 子板的示意图；
图 2为本发明多层电路板制作方法的一种实施例的示意图；
图 3为本发明多层电路板制作方法的另一种实施例的示意图； 图 4为本发明多层电路板的一种实施例的示意图；
图 5为本发明多层电路板的另一种实施例的示意图；
图 6为本发明多层电路板的设置多个容置槽的第一种实施例的示意图 图 7为本发明多层电路板的设置多个容置槽的第二种实施例的示意图 图 8为本发明多层电路板的设置多个容置槽的第三种实施例的示意图 图 9是本发明多层电路板的导热块的一种实施例的示意图；
图 10是本发明多层电路板的导热块的另一种实施例的示意图；
图 11是本发明多层电路板的导热块的再一种实施例的俯视示意图； 图 12是本发明多层电路板的导热块的又一种实施例的示意图。 具体实施方式
下面将结合本发明实施例中的附图， 对本发明实施例中的技术方案进行清 楚、 完整地描述， 显然， 所描述的实施例仅仅是本发明一部分实施例， 而不是 全部的实施例。 基于本发明中的实施例， 本领域普通技术人员在没有作出创造 性劳动前提下所获得的所有其他实施例， 都属于本发明保护的范围。 如图 2或图 3所示，本发明提供一种制作多层电路板的方法的实施例，包括: 步骤 201， 将至少一个子板 2， 开设阶段槽 20， 形成第一子板 21 ;
步骤 202， 将至少一个子板 2与介质层 3叠放在一起， 其中， 所述子板 2 包括所述第一子板 21，所述第一子板 21以使所述设置的阶段槽 20连通的方式 放置， 所述阶段槽 20连通后形成容置槽 6， 将导热块 7放置在所述容置槽 6 内， 所述介质层 3位于所述子板 2之间；
步骤 203，将所述叠放在一起的子板 2，介质层 3，以及导热块 7进行压合， 并将所述压合在一起的子板和导热块制成多层电路板。
在本发明的实施例中，将导热块在子板压合时埋入电路板，工艺流程简单， 提高了导热块的组装效率。 在本发明的实施例中， 在步骤 203中， 压合后， 所述导热块低于或平齐于 电路板的表面， 甚至可以高出电路板的表面。
如图 2至图 5所示，在本发明的实施例中，所述子板可以包括第一子板 21 和未开设有阶段槽的第二子板 22。 所述第二子板 22位于所述容置槽 6的一端 或者两端。 此时， 本发明的实施还可包括步骤 204， 在所述导热块一侧， 开设 与所述导热块连接的导热孔 8; 此外还可在所述多层电路板的其它地方钻设导 热孔 8。
如图 2至图 5所示， 在本发明的实施例中， 所述介质层位于所述相邻子板 之间， 包括：
所述介质层 3位于两个所述第一子板 21之间， 并且在两个所述第一子板 21的阶段槽 20之间也开设有阶段槽； 或者， 所述介质层 3位于两个所述第二 子板 22之间； 或者， 所述介质层 3位于所述第一子板 21和所述第二子板 22 之间， 所述介质层 3开设有阶段槽， 所述介质层的阶段槽， 与所述第一子板 21 的阶段槽 20连通； 或者， 所述介质层 3位于所述第一子板 21和所述第二子板 22之间， 所述介质层 3未开设有阶段槽。
参见图 2， 图 3， 图 4及图 5， 在本发明的实施例中， 所述导热孔 8， 连接 所述导热块 7与电子器件 91，或者连接所述导热块 7与电路板表面，或者连接 所述导热块 7， 所述电子器件 91， 以及电路板表面， 或者连接所述导热块 7， 所述电子器件 91， 以及嵌入电路板内部的一散热器件。所述导热孔 8可以将电 子器件 91的热量传递到导热块 7; 或者，将导热块 7中的热量传递到电路板表 面， 或者， 将电子器件 91的热量传递到导热块 7， 再将导热块 7中的热量传递 到电路板表面 （图 4及图 5中的箭头表示了传热路径）， 或者， 将电子器件 91 的热量传递到导热块 7， 再将导热块 7中的热量传递到散热器件。
通过在多层电路板内设置导热块， 通过导热块将电子器件产生的热量在电 路板内进行传递， 从而减少了热阻， 提高电路板局部散热能力。
在本发明的实施例中， 所述导热孔可以采用电镀填实， 或者塞入导电银桨 等方式以提高散热效果， 或者， 所述导热孔还可以容设导热液体。 所述导热液 体可以为： 水或油或者硅油等。
在本发明的实施例中， 所述导热块由导热率高于电路板介质的材料制成， 如铜、 或铝、 或金属合金等； 所述导热块也可以为盛放有导热液体的腔体， 所 述导热液体可以通过导热孔流出。 所述导热块的形状可以为规则的柱形， 球形或者锥形； 也可以为不规则的 立体形状。 相应地， 容置槽的形状与导热块的形状相匹配， 可以使得导热块容 设于所述容置槽内， 不会因为容置槽太大， 而导致在子板与导热块压合在一起 后， 导热块从容置槽内脱落， 或者， 导热块在容置槽内晃动； 也不会因为容置 槽太小， 而导致在子板与导热块压合在一起后， 导热块与子板因相互挤压， 而 受到损坏。 如图 5所示， 在本发明的实施例中， 所述子板可以全部为第一子板， 所述 导热块 7设置于容置槽后， 两端位于所述多层电路板的外侧表面上， 所述导热 块 7的端面平齐于电路板的表面， 或者高于电路板的表面， 或者低于电路板的 表面。
在本发明的实施例中， 所述导热块 7包括一个主体 71和一个固定连接在 所述主体 71上方的连接体 72， 所述连接体 72的截面积小于所述主体 71的截 面积； 所述容置槽的形状与所述导热块相匹配。 其中， 所述主体 71和连接体 72可以是一体设置， 即形成一个整体结构。
本发明的实施例中， 其导热块 7顶部的连接体 72的截面积较小， 该连接 体 72可通过悍锡连接到电子器件的底部的散热悍盘， 导热块 7底部的主体 71 的截面积较大， 与电路的技术外壳底部或者衬底接触， 也就是说， 通过内埋阶 梯状导热块， 其热阻远远小于过孔散热的方式， 从而能充分保证接触面积， 降 低接触热阻， 而且还能使多层电路板的双面均可贴装元器件， 便于器件布局。
所述主体 71上对应与连接体 72结合的位置处， 具有一个台肩 711， 所述 台肩 711与子板 21的表面平行， 且台肩 711最好是位于介质层 3的下表面上。 所述连接体可为一个整体，如图 9所示；或者具有两个以上连接分体 721， 每个连接分体 721单独设置，各连接分体 721均与主体 71相连，如图 10所示， 两个所述连接分体 721单独、 平行、 间隔地固定连接在所述主体 71上方。 另 外， 连接体 72可根据电气性能的要求设计成任意的形状， 为规则或不规则的 形状， 如图 11所示。 此处， 连接体 72根据需要也可呈阶梯状， 从而使得导热 块在高度方向上具有多段阶梯。
在本发明的实施例中，如图 12所示，所述导热块 7还包括一个连接件 73， 所述连接件 73固定连接在所述主体 71下方， 所述连接件 73的截面积小于所 述主体 71的截面积。
在本发明的实施例中， 所述多层电路板的上、 下表面分别设有一个电镀层 9， 此时导热块的高度最好是平齐于所述多层电路板的高度， 使导热块 7与两 个电镀层 4保持接触， 形成热量传导通道。 如图 6-8所示， 本发明实施例中的多个所述第一子板， 可以通过调整叠放 的顺序， 或者将阶段槽开设在不同的位置， 从而将多个阶段槽组合为多个容置 槽 6; 或者， 所述第一子板也可以在不同位置开设多个阶段槽， 将所述多个阶 段槽分别与其他第一子板的阶段槽连通， 形成多个容置槽 6， 所述多个容置槽 6之间可以设置有导热孔。
所述多个容置槽 6可以并排设置， 上下垂直设置， 或者上下错开设置等。 所述多个子板的阶段槽的截面形状可以相同也可以不同，截面积大小可以相同 也可以不同。 在本发明的实施例中， 所述介质层可以为： 低流胶 B-stage PrePreg (低 流胶 B态半固化片）， 或者低流胶 B-stage Prepreg结合 C-Stage Prepreg (低 流胶 B态半固化片结合 C态固化片）； 使所述介质层具有延展特性而能吸收导 热块制作的高度误差， 有利于保证多层电路板表面的平整度； 当然， 所述介质 层也可以为其它粘合介质。 如图 1所示，在本发明的实施例中，所述子板可以由至少一个内层芯板 28 组成， 其中， 在子板具有多个内层芯板 28的情况下， 多个内层芯板 28压合在 一起，相邻内层芯板 28之间填充介质层 27，在多个内层芯板 28的外侧还可以 进一步包括有图形层 29，所述图形层 29和内层芯板 28之间填充有介质层 27。
在本发明的实施例中，所述子板的外层，可以为内层芯板或单独的图形层， 因为子板将来是要组成多层板的， 所以位于多层板最外层的子板， 可以仅在朝 内的一侧表面具有图形层， 需说明的是， 所述的子板朝内的一侧表面的图形层 可以为单独的图形层或者为内层芯板的图形层。在多层板最外层的子板的朝外 的一侧表面可以具有图形层， 也可以不具有图形层， 需说明的是， 子板的朝外 的一侧表面的图形层可以为单独的图形层或者为内层芯板的图形层。 本领域普通技术人员可以理解实现上述实施例方法中的全部或部分流程， 是可以通过计算机程序来指令相关的硬件来完成，所述的程序可存储于一计算 机可读取存储介质中，该程序在执行时，可包括如上述各方法的实施例的流程。 其中， 所述的存储介质可为磁碟、 光盘、 只读存储记忆体（Read-Only Memory, ROM) 或随机存储记忆体 (Random Access Memory, RAM) 等。 根据上述实施例， 如图 2或图 3所示， 本发明还提供一种多层电路板的实 施例， 包括： 导热块 7， 以及叠放在一起的多个子板 2和介质层 3， 所述子板 2 包括所述第一子板 21， 所述第一子板 21开设有阶段槽 20， 多个所述第一子板 21的阶段槽 20连通形成容置槽 6， 所述导热块 7容设在所述容置槽 6内， 所 述介质层 3位于所述子板 2之间。
在本发明的实施例中， 通过在多层电路板内设置导热块， 通过导热块将电 子器件产生的热量在电路板内进行传递， 从而减少了热阻， 提高电路板局部散 热能力。
在本发明的实施例中， 所述导热块低于或平齐于电路板的表面， 甚至可以 高出电路板的表面 基于上述实施例， 如图 2或图 3所示， 本发明还提供一种通信设备的实施 例， 包括： 至少一个多层电路板， 所述多层电路板包括： 导热块 7， 以及叠放 在一起的多个子板 2和介质层 3， 所述子板 2包括所述第一子板 21， 所述第一 子板 21开设有阶段槽 20， 多个所述第一子板 21的阶段槽 20连通形成容置槽 6， 所述导热块 7容设在所述容置槽 6内， 所述介质层 3位于所述子板 2之间。
在本发明的实施例中， 通过在多层电路板内设置导热块， 通过导热块将电 子器件产生的热量在电路板内进行传递， 从而减少了热阻， 提高电路板局部散 热能力。
以上所述仅为本发明的几个实施例， 本领域的技术人员依据申请文件公开 的可以对本发明进行各种改动或变型而不脱离本发明的精神和范围。

Claims

权 利 要 求 书
1、 一种制作多层电路板的方法， 其特征在于， 包括：
将至少一个子板， 开设阶段槽， 形成第一子板；
将至少一个子板与介质层叠放在一起，其中，所述子板包括所述第一子板， 所述第一子板以使所述设置的阶段槽连通的方式放置，所述阶段槽连通后形成 容置槽， 将导热块放置在所述容置槽内， 所述介质层位于所述子板之间；
将所述叠放在一起的子板， 介质层， 以及导热块进行压合， 并将所述压合 在一起的子板和导热块制成多层电路板。
2、 如权利要求 1所述的制作多层电路板的方法， 其特征在于， 所述子板 包括第一子板和未开设有阶段槽的第二子板， 所述第二子板位于所述容置槽的 一端或者两端； 在所述导热块一侧， 开设与所述导热块连接的导热孔。
3、 根据权利要求 2所述的制作多层电路板的方法， 其特征在于， 所述导 热孔， 连接所述导热块与电路板上的电子器件， 或者， 连接所述导热块与电路 板表面， 或者， 连接所述导热块， 所述电路板上的电子器件， 以及电路板表面， 或者， 连接所述导热块， 所述电路板上的电子器件， 以及嵌入电路板内部的散 热器件。
4、 根据权利要求 1所述的制作多层电路板的方法， 其特征在于， 所述子 板全部为第一子板， 所述导热块设置于容置槽后， 两端位于所述多层电路板的 外侧表面上。
5、 根据权利要求 1所述的制作多层电路板的方法， 其特征在于， 所述导 热块包括一个主体和一个固定连接在所述主体上方的连接体， 所述连接体的截 面积小于所述主体的截面积； 所述容置槽的形状与所述导热块相匹配。
6、 根据权利要求 5所述的制作多层电路板的方法， 其特征在于， 所述连 接体为一个整体， 或者具有两个以上连接分体。
7、 根据权利要求 6所述的制作多层电路板的方法， 其特征在于， 所述导 热块还包括一个连接件， 所述连接件固定连接在所述主体下方， 所述连接件的 截面积小于所述主体的截面积。
8、根据权利要求 1一 7任一项所述的制作多层电路板的方法，其特征在于， 所述导热块由导热率高于电路板的材料制成， 或者， 所述导热块为盛放有导热 液体的腔体。
9、 一种多层电路板， 其特征在于， 包括： 导热块， 以及叠放在一起的多 个子板和介质层， 所述子板包括第一子板， 所述第一子板开设有阶段槽， 多个 所述第一子板的阶段槽连通形成容置槽， 所述导热块容设在所述容置槽内， 所 述介质层位于所述子板之间。
10、 根据权利要求 9所述的多层电路板， 其特征在于， 所述子板包括第一 子板和未开设有阶段槽的第二子板， 所述第二子板位于所述容置槽的一端或者 两端； 在所述导热块一侧， 开设与所述导热块连接的导热孔。
11、 根据权利要求 10所述的多层电路板， 其特征在于， 所述导热孔， 连 接所述导热块与电路板上的电子器件， 或者， 连接所述导热块与电路板表面， 或者， 连接所述导热块， 所述电路板上的电子器件， 以及电路板表面， 或者， 连接所述导热块，所述电路板上的电子器件，以及嵌入电路板内部的散热器件。
12、 根据权利要求 9所述的多层电路板， 其特征在于， 所述子板全部为第 一子板，所述导热块设置于容置槽后，两端位于所述多层电路板的外侧表面上。
13、 根据权利要求 9所述的多层电路板， 其特征在于， 所述导热块包括一 个主体和一个固定连接在所述主体上方的连接体，所述连接体的截面积小于所 述主体的截面积； 所述容置槽的形状与所述导热块相对应。
14、 根据权利要求 13所述的多层电路板， 其特征在于， 所述连接体为一 个整体， 或者具有两个以上连接分体。
15、 根据权利要求 14所述的多层电路板， 其特征在于， 所述导热块还包 括一个连接件， 所述连接件固定连接在所述主体下方， 所述连接件的截面积小 于所述主体的截面积。
16、 根据权利要求 9一 15任一项所述的多层电路板， 其特征在于， 所述导 热块由导热率高于电路板的材料制成， 或者， 所述导热块为盛放有导热液体的 腔体。
17、 一种通信设备， 其特征在于， 包括至少一个多层电路板， 所述多层电 路板包括： 导热块， 以及叠放在一起的多个子板和介质层， 所述子板包括第一 子板， 所述第一子板开设有阶段槽， 多个所述第一子板的阶段槽连通形成容置 槽， 所述导热块容设在所述容置槽内， 所述介质层位于所述子板之间。
18、 根据权利要求 17所述的通信设备， 其特征在于， 所述子板包括第一 子板和未开设有阶段槽的第二子板， 所述第二子板位于所述容置槽的一端或者 两端； 在所述导热块一侧， 开设与所述导热块连接的导热孔。
19、 根据权利要求 17所述的通信设备， 其特征在于， 所述导热块包括一 个主体和一个固定连接在所述主体上方的连接体，所述连接体的截面积小于所 述主体的截面积； 所述容置槽的形状与所述导热块相对应。
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