WO2010016207A1 - フレキシブル半導体装置およびその製造方法 - Google Patents
フレキシブル半導体装置およびその製造方法 Download PDFInfo
- Publication number
- WO2010016207A1 WO2010016207A1 PCT/JP2009/003616 JP2009003616W WO2010016207A1 WO 2010016207 A1 WO2010016207 A1 WO 2010016207A1 JP 2009003616 W JP2009003616 W JP 2009003616W WO 2010016207 A1 WO2010016207 A1 WO 2010016207A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- electrode
- metal foil
- semiconductor device
- semiconductor layer
- sealing resin
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 579
- 238000000034 method Methods 0.000 title claims abstract description 158
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 130
- 229920005989 resin Polymers 0.000 claims abstract description 317
- 239000011347 resin Substances 0.000 claims abstract description 317
- 229910052751 metal Inorganic materials 0.000 claims abstract description 313
- 239000002184 metal Substances 0.000 claims abstract description 313
- 239000011888 foil Substances 0.000 claims abstract description 302
- 238000007789 sealing Methods 0.000 claims abstract description 240
- 238000000605 extraction Methods 0.000 claims abstract description 123
- 238000005530 etching Methods 0.000 claims abstract description 88
- 230000008569 process Effects 0.000 claims abstract description 78
- 239000000463 material Substances 0.000 claims abstract description 64
- 239000000470 constituent Substances 0.000 claims abstract description 16
- 239000003990 capacitor Substances 0.000 claims description 53
- 238000010438 heat treatment Methods 0.000 claims description 25
- 230000015572 biosynthetic process Effects 0.000 claims description 22
- 230000002093 peripheral effect Effects 0.000 claims description 18
- 238000000137 annealing Methods 0.000 claims description 9
- 238000005224 laser annealing Methods 0.000 claims description 6
- 238000009413 insulation Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 456
- 239000010408 film Substances 0.000 description 241
- 239000000758 substrate Substances 0.000 description 44
- 239000011229 interlayer Substances 0.000 description 31
- 239000011162 core material Substances 0.000 description 14
- 239000011241 protective layer Substances 0.000 description 14
- 230000006870 function Effects 0.000 description 12
- 239000011521 glass Substances 0.000 description 12
- 238000003475 lamination Methods 0.000 description 12
- 239000003822 epoxy resin Substances 0.000 description 11
- 230000008018 melting Effects 0.000 description 11
- 238000002844 melting Methods 0.000 description 11
- 229920000647 polyepoxide Polymers 0.000 description 11
- 239000010949 copper Substances 0.000 description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 9
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 9
- 239000011112 polyethylene naphthalate Substances 0.000 description 9
- 229920001955 polyphenylene ether Polymers 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- -1 polyethylene naphthalate Polymers 0.000 description 8
- 238000004544 sputter deposition Methods 0.000 description 8
- 238000010030 laminating Methods 0.000 description 7
- 230000004048 modification Effects 0.000 description 7
- 238000012986 modification Methods 0.000 description 7
- 239000004642 Polyimide Substances 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 238000000151 deposition Methods 0.000 description 6
- 239000011810 insulating material Substances 0.000 description 6
- 239000005020 polyethylene terephthalate Substances 0.000 description 6
- 229920000139 polyethylene terephthalate Polymers 0.000 description 6
- 229920001721 polyimide Polymers 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 239000000853 adhesive Substances 0.000 description 5
- 230000001070 adhesive effect Effects 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 229920003207 poly(ethylene-2,6-naphthalate) Polymers 0.000 description 5
- 238000012546 transfer Methods 0.000 description 5
- 239000004734 Polyphenylene sulfide Substances 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- 239000011889 copper foil Substances 0.000 description 4
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 4
- 239000007769 metal material Substances 0.000 description 4
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 4
- 229920000069 polyphenylene sulfide Polymers 0.000 description 4
- 239000004925 Acrylic resin Substances 0.000 description 3
- 229920000178 Acrylic resin Polymers 0.000 description 3
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 3
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 3
- 239000012298 atmosphere Substances 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 229910001220 stainless steel Inorganic materials 0.000 description 3
- 239000010935 stainless steel Substances 0.000 description 3
- 229910001936 tantalum oxide Inorganic materials 0.000 description 3
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 3
- 229910001887 tin oxide Inorganic materials 0.000 description 3
- 238000001771 vacuum deposition Methods 0.000 description 3
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 2
- 229910021193 La 2 O 3 Inorganic materials 0.000 description 2
- 239000004721 Polyphenylene oxide Substances 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 229910006404 SnO 2 Inorganic materials 0.000 description 2
- 229910010413 TiO 2 Inorganic materials 0.000 description 2
- 229910021536 Zeolite Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 239000011575 calcium Substances 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 238000002425 crystallisation Methods 0.000 description 2
- 230000008025 crystallization Effects 0.000 description 2
- HNPSIPDUKPIQMN-UHFFFAOYSA-N dioxosilane;oxo(oxoalumanyloxy)alumane Chemical compound O=[Si]=O.O=[Al]O[Al]=O HNPSIPDUKPIQMN-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 239000011777 magnesium Substances 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 229920003023 plastic Polymers 0.000 description 2
- 239000004033 plastic Substances 0.000 description 2
- 229920006380 polyphenylene oxide Polymers 0.000 description 2
- 229920000036 polyvinylpyrrolidone Polymers 0.000 description 2
- 235000013855 polyvinylpyrrolidone Nutrition 0.000 description 2
- 239000001267 polyvinylpyrrolidone Substances 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 239000010457 zeolite Substances 0.000 description 2
- 125000003184 C60 fullerene group Chemical group 0.000 description 1
- OYPRJOBELJOOCE-UHFFFAOYSA-N Calcium Chemical compound [Ca] OYPRJOBELJOOCE-UHFFFAOYSA-N 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 1
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910003363 ZnMgO Inorganic materials 0.000 description 1
- YKIOKAURTKXMSB-UHFFFAOYSA-N adams's catalyst Chemical compound O=[Pt]=O YKIOKAURTKXMSB-UHFFFAOYSA-N 0.000 description 1
- JRPBQTZRNDNNOP-UHFFFAOYSA-N barium titanate Chemical compound [Ba+2].[Ba+2].[O-][Ti]([O-])([O-])[O-] JRPBQTZRNDNNOP-UHFFFAOYSA-N 0.000 description 1
- 229910002113 barium titanate Inorganic materials 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- QHIWVLPBUQWDMQ-UHFFFAOYSA-N butyl prop-2-enoate;methyl 2-methylprop-2-enoate;prop-2-enoic acid Chemical compound OC(=O)C=C.COC(=O)C(C)=C.CCCCOC(=O)C=C QHIWVLPBUQWDMQ-UHFFFAOYSA-N 0.000 description 1
- 229910052791 calcium Inorganic materials 0.000 description 1
- WEUCVIBPSSMHJG-UHFFFAOYSA-N calcium titanate Chemical compound [O-2].[O-2].[O-2].[Ca+2].[Ti+4] WEUCVIBPSSMHJG-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- HTXDPTMKBJXEOW-UHFFFAOYSA-N dioxoiridium Chemical compound O=[Ir]=O HTXDPTMKBJXEOW-UHFFFAOYSA-N 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005401 electroluminescence Methods 0.000 description 1
- 238000001962 electrophoresis Methods 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- LNEPOXFFQSENCJ-UHFFFAOYSA-N haloperidol Chemical compound C1CC(O)(C=2C=CC(Cl)=CC=2)CCN1CCCC(=O)C1=CC=C(F)C=C1 LNEPOXFFQSENCJ-UHFFFAOYSA-N 0.000 description 1
- RBTKNAXYKSUFRK-UHFFFAOYSA-N heliogen blue Chemical compound [Cu].[N-]1C2=C(C=CC=C3)C3=C1N=C([N-]1)C3=CC=CC=C3C1=NC([N-]1)=C(C=CC=C3)C3=C1N=C([N-]1)C3=CC=CC=C3C1=N2 RBTKNAXYKSUFRK-UHFFFAOYSA-N 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910003437 indium oxide Inorganic materials 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000002923 metal particle Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- SLIUAWYAILUBJU-UHFFFAOYSA-N pentacene Chemical compound C1=CC=CC2=CC3=CC4=CC5=CC=CC=C5C=C4C=C3C=C21 SLIUAWYAILUBJU-UHFFFAOYSA-N 0.000 description 1
- CVLHDNLPWKYNNR-UHFFFAOYSA-N pentasilolane Chemical compound [SiH2]1[SiH2][SiH2][SiH2][SiH2]1 CVLHDNLPWKYNNR-UHFFFAOYSA-N 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229920000301 poly(3-hexylthiophene-2,5-diyl) polymer Polymers 0.000 description 1
- 150000004033 porphyrin derivatives Chemical class 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000003014 reinforcing effect Effects 0.000 description 1
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 1
- 239000003566 sealing material Substances 0.000 description 1
- SBIBMFFZSBJNJF-UHFFFAOYSA-N selenium;zinc Chemical compound [Se]=[Zn] SBIBMFFZSBJNJF-UHFFFAOYSA-N 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 150000003377 silicon compounds Chemical class 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- VEALVRVVWBQVSL-UHFFFAOYSA-N strontium titanate Chemical compound [Sr+2].[O-][Ti]([O-])=O VEALVRVVWBQVSL-UHFFFAOYSA-N 0.000 description 1
- JBQYATWDVHIOAR-UHFFFAOYSA-N tellanylidenegermanium Chemical compound [Te]=[Ge] JBQYATWDVHIOAR-UHFFFAOYSA-N 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 239000011787 zinc oxide Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
- H01L27/1266—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
- H10K71/80—Manufacture or treatment specially adapted for the organic devices covered by this subclass using temporary substrates
Definitions
- the present invention relates to a flexible semiconductor device and a manufacturing method thereof. More specifically, the present invention relates to a flexible semiconductor device that can be used as a TFT and a method for manufacturing the same.
- a display medium is formed using elements utilizing liquid crystal, organic EL (organic electroluminescence), electrophoresis, or the like.
- a technique using an active drive element (TFT element) as an image drive element has become mainstream in order to ensure uniformity of screen brightness, screen rewrite speed, and the like.
- TFT element active drive element
- these TFT elements are formed on a glass substrate, and liquid crystal, organic EL elements and the like are sealed.
- a semiconductor such as a-Si (amorphous silicon) or p-Si (polysilicon) can be mainly used for the TFT element.
- a TFT element is manufactured by multilayering these Si semiconductors (and a metal film if necessary) and sequentially forming source, drain, and gate electrodes on the substrate.
- a material that can withstand a high process temperature must be used as a substrate material. Therefore, in practice, it is necessary to use glass as the substrate material. Although a quartz substrate can be used, it is expensive and there is an economical problem in increasing the size of the display. Therefore, a glass substrate is generally used as the substrate on which the TFT element is formed.
- the display is heavy, lacks flexibility, and may be broken by a drop impact.
- These characteristics resulting from the formation of TFT elements on a glass substrate are undesirable in satisfying the need for an easy-to-use portable thin display accompanying the progress of computerization.
- Patent Document 2 discloses a technique in which a TFT element is manufactured on a support (for example, a glass substrate) by a process substantially similar to the conventional process, and then the TFT element is peeled off from the glass substrate and transferred onto a resin substrate. ing.
- a TFT element is formed on a glass substrate, and the TFT element is adhered to the resin substrate through a sealing layer such as an acrylic resin, and then the glass substrate is peeled off, whereby the TFT element is formed on the resin substrate. It is formed by transferring.
- a peeling process of a support becomes a problem. That is, in the step of peeling the support from the resin substrate, for example, it is necessary to perform a process for reducing the adhesion between the support and the TFT element. In addition, a peeling layer is formed between the support and the TFT element, and a process for physically or chemically removing the peeling layer is required, resulting in complicated processes, and in terms of productivity. Leaving a problem.
- a method of forming a TFT element on a resin substrate there is a method of directly forming a TFT element on a resin substrate, for example, not only by the transfer method described above.
- the resin substrate has low heat resistance, it is necessary to limit the process temperature to be low. Therefore, the TFT element directly formed on the resin substrate tends to be inferior to the TFT element formed on the glass substrate. That is, it is actually difficult to obtain desired TFT performance and reliability.
- the inventors of the present application have attempted to solve the problems of the flexible semiconductor device described above, not in the extension of the prior art, but in a new direction to solve these problems.
- the present invention has been made in view of the above points, and a main object thereof is to provide a flexible semiconductor device having high performance and excellent productivity and a method for manufacturing the same.
- a method for manufacturing a flexible semiconductor device comprising: (I) forming an insulating film on the upper surface of the metal foil; (Ii) forming an extraction electrode pattern on the upper surface of the metal foil; (Iii) forming a semiconductor layer on the insulating film so as to be in contact with the extraction electrode pattern; (Iv) forming a sealing resin layer on the upper surface of the metal foil so as to cover the semiconductor layer and the extraction electrode pattern, and (v) forming an electrode by etching the metal foil,
- the metal foil is used as a support for the insulating film formed in steps (i) to (iv), the extraction electrode pattern, the semiconductor layer and the sealing resin layer, and the constituent material of the electrode in step (v)
- the manufacturing method characterized by using as is provided.
- One feature of the present invention is that a metal foil functioned as a support in the manufacturing process of a flexible semiconductor device is used as a component of the flexible semiconductor device called an electrode constituent material.
- the term “flexible” of “flexible semiconductor device” substantially means that the semiconductor device has flexibility to bend.
- the “flexible semiconductor device” in the present invention can be referred to as a “flexible semiconductor device” or a “flexible semiconductor element” in view of its configuration.
- electrode constituent material means an electrode (for example, “source electrode”, “drain electrode”, “gate electrode”, etc., which will be described later) that forms a TFT element by performing a process such as etching.
- electrode constituent material means an electrode (for example, “source electrode”, “drain electrode”, “gate electrode”, etc., which will be described later) that forms a TFT element by performing a process such as etching.
- Substantially means a material / member that can be formed.
- the semiconductor layer forming step can be performed by a high temperature process of 180 ° C. or higher, preferably about 400 ° C. to 1000 ° C.
- the obtained semiconductor layer can be subjected to heat treatment. In such a case, it is preferable to perform thermal annealing and / or laser annealing as the heat treatment. Such heat treatment promotes crystallization of the semiconductor material.
- the source electrode and the drain electrode which are constituent elements of the TFT element are formed by etching the metal foil in the step (v).
- the gate electrode may be formed by etching the metal foil as in the formation of the source electrode and the drain electrode. Accordingly, the source electrode, the drain electrode, and the gate electrode can be formed on the same plane (more specifically, the lower surface of the sealing resin layer encapsulating the insulating film, the semiconductor layer, and the extraction electrode pattern). .
- the gate electrode may be formed so as to be “non-coplanar” with the source electrode and the drain electrode.
- a gate electrode by providing a further metal foil on the upper surface of the sealing resin layer and etching the further metal foil.
- a capacitor electrode layer may be additionally formed by etching a metal foil.
- (Ii) ′ a step of forming a semiconductor layer on the insulating film; and (iii) ′ a step of forming an extraction electrode pattern on the upper surface of the metal foil so as to be in contact with the semiconductor layer.
- the present invention also provides a method for manufacturing a flexible semiconductor device having a plurality of TFT elements.
- the manufacturing method of the present invention is a manufacturing method of a flexible semiconductor device having at least two TFT elements each having an insulating film, a semiconductor layer, a gate electrode, a source electrode, and a drain electrode, (A) A first metal foil having a TFT element formation surface provided with an insulating film and a semiconductor layer constituting the first TFT element, and an insulating film and a semiconductor layer constituting the second TFT element are provided.
- a second metal foil having a TFT element forming surface and one sealing resin film (B) By superimposing the TFT element forming surface of the first metal foil on one surface of the sealing resin film, one side of the insulating film and the semiconductor layer constituting the first TFT element with respect to the sealing resin film Embedding from the surface, (C) By superimposing the TFT element forming surface of the second metal foil on the other surface of the sealing resin film, the insulating film and the semiconductor layer constituting the second TFT element are placed on the other side of the sealing resin film.
- the first metal foil is used as the “support for the insulating film and semiconductor layer constituting the first TFT element” in the steps (a) to (c), and the electrode of the first TFT element is used in the step (d).
- the second metal foil is used as a “support for an insulating film and a semiconductor layer constituting the second TFT element” in steps (a) to (c), and in step (d). It is characterized by being used as an electrode constituent material for the second TFT element.
- a manufacturing method of a flexible semiconductor device having a plurality of such TFT elements is also characterized in that a metal foil functioning as a support at the time of manufacturing the flexible semiconductor device is used as a constituent element of a flexible semiconductor called an electrode constituent material. There is one.
- the first metal foil is etched to form the source and drain electrodes constituting the first TFT element and the gate electrode constituting the second TFT element. Then, by etching the second metal foil, a gate electrode constituting the first TFT element and a source electrode and a drain electrode constituting the second TFT element are formed.
- the first metal foil is etched to form the gate electrode, the source electrode, and the drain electrode constituting the first TFT element, and the second metal. By etching the foil, a gate electrode, a source electrode, and a drain electrode constituting the second TFT element are formed.
- the present invention also provides a flexible semiconductor device that can be obtained by the above manufacturing method.
- a flexible semiconductor device of the present invention includes: Insulation film, A semiconductor layer formed on the top surface of the insulating film; An electrode located on the lower surface side of the insulating film, An extraction electrode pattern for electrically connecting the electrode and the semiconductor layer, and a sealing resin layer for sealing the extraction electrode pattern and the semiconductor layer,
- the electrode is formed by etching a metal foil that has functioned as a support for the insulating film, the semiconductor layer, the extraction electrode pattern, and the sealing resin layer.
- the flexible semiconductor device of the present invention has an electrode formed by etching a metal foil that has functioned as a support in the manufacturing process. Due to such characteristics, in the flexible semiconductor device of the present invention, the electrode preferably has a tapered shape in the thickness direction. Preferably, the thickness of the electrode is larger than that obtained by a conventional electrode forming method (for example, vapor deposition or sputtering). For example, the electrode thickness is 4 ⁇ m to about 20 ⁇ m. Yes.
- the electrodes formed by etching the metal foil are a source electrode, a drain electrode, and a gate electrode, and the source electrode, the drain electrode, and the gate electrode are on the same plane. Is located. That is, the source electrode, the drain electrode, and the gate electrode are provided in a flush state.
- the gate electrode is provided in a “non-coplanar state” with respect to the source electrode and the drain electrode.
- the electrodes formed by etching the metal foil located on the lower side of the insulating film are the source electrode and the drain electrode, while facing the semiconductor layer with the sealing resin layer interposed therebetween.
- the electrode formed by etching another metal foil provided on the upper surface of the sealing resin layer is preferably a gate electrode.
- the lower surface of the peripheral portion of the semiconductor layer is partially in contact with the upper surface of the peripheral portion of the extraction electrode pattern for the source electrode, The lower surface of the peripheral portion of the semiconductor layer may partially contact the upper surface of the peripheral portion of the extraction electrode pattern for the drain electrode.
- the upper surface of the peripheral portion of the semiconductor layer is in partial contact with the lower surface of the peripheral portion of the extraction electrode pattern for the source electrode, and the upper surface of the peripheral portion of the semiconductor layer is the peripheral portion of the extraction electrode pattern for the drain electrode. It may be partially in contact with the lower surface.
- the flexible semiconductor device includes at least two TFT elements each including an insulating film, a semiconductor layer, a gate electrode, a source electrode, and a drain electrode.
- the “flexible semiconductor device having at least two TFT elements” is a first TFT having an insulating film, a semiconductor layer, a gate electrode, a source electrode, and a drain electrode. This can correspond to a semiconductor device having at least an element and a second TFT element.
- the sealing resin layer is formed on the metal foil so as to cover the semiconductor layer, and then the metal The electrode of the TFT element is formed by etching the foil. Therefore, the metal foil as the support can be used as an electrode (source electrode, drain electrode, gate electrode, etc.) of the TFT element, and there is no need to finally peel off the metal foil as the support. Therefore, the TFT element can be manufactured by a simple process, and productivity can be improved.
- the sealing resin layer can be formed on the metal foil after the insulating film and the semiconductor layer are formed on the metal foil, a high-temperature process can be actively introduced in the production of the insulating film and the semiconductor layer. Accordingly, for example, heat treatment can be performed during or after the formation of the semiconductor layer, and TFT characteristics (for example, carrier mobility of the semiconductor) can be preferably improved.
- TFT characteristics for example, carrier mobility of the semiconductor
- (A) is a top view of the flexible semiconductor device 100A, and (b) is a cross-sectional view showing a cross section taken along the line Ia-Ia of (a).
- (A) is a top view of the flexible semiconductor device 100B, and (b) is a cross-sectional view showing the Ib-Ib cross section of (a).
- Schematic diagram of electrode with taper shape is process sectional drawing which shows the manufacturing process of 100 A of flexible semiconductor devices (A)-(c) Process sectional drawing which shows the manufacturing process of flexible semiconductor device 100B (A)-(c) Process sectional drawing which shows the manufacturing process of flexible semiconductor device 100B (A) is a top view of the flexible semiconductor device 100C, (b) is a cross-sectional view showing a Vb-Vb cross section of (a).
- A)-(e) is process sectional drawing which shows the manufacturing process of 100 C of flexible semiconductor devices (A) is a top view of the flexible semiconductor device 100D, (b) is a cross-sectional view showing the Xb-Xb cross section of (a).
- FIG. 1 is a top view of the flexible semiconductor device 100G
- FIG. 1 is a cross-sectional view showing a IXb-IXb cross section of (a).
- (A) is a top view of the flexible semiconductor device 100H
- (b) is a cross-sectional view showing the XVb-XVb cross section of (a)
- (c) is a cross-sectional view showing the XVc-XVc cross section of (a).
- Equivalent circuit diagram of flexible semiconductor devices 100G and 100H (A) is a top view of the flexible semiconductor device 100I
- (b) is a cross-sectional view showing the XVIIb-XVIIb cross section of (a).
- (A)-(c) is process sectional drawing which shows the manufacturing process of flexible semiconductor device 100I
- A) is a top view of the flexible semiconductor device 100J
- (b) is a cross-sectional view showing the Xb-Xb cross section of (a)
- (c) is a cross-sectional view showing the Xc-Xc cross section of (a).
- A) And (b) is process sectional drawing which shows the manufacturing process of flexible semiconductor device 100J.
- (A)-(c) is process sectional drawing which shows the manufacturing process of flexible semiconductor device 100J.
- Sectional drawing which shows the cross section of the flexible semiconductor device 100K (A)-(c)
- Process sectional drawing which shows the manufacturing process of flexible semiconductor device 100K
- Sectional view of flexible semiconductor device 100L (A)-(c) is process sectional drawing which shows the manufacturing process of flexible semiconductor device 100L
- the perspective view which shows the external appearance of the whole image display apparatus (A) And (b) is a top view of flexible semiconductor device 100M, 100M '.
- Schematic diagram showing an example of product application of a flexible semiconductor device image display part of a mobile personal computer or notebook personal computer
- Schematic diagram showing a product application example of a flexible semiconductor device (image display part of a camcorder) Schematic diagram showing product application example (image display part of electronic paper) of flexible semiconductor device
- the “direction” described in this specification is a direction based on the positional relationship between the metal foil 50 and the semiconductor layer 20 and will be described in the vertical direction in the drawing for convenience. Specifically, it corresponds to the vertical direction of each figure, the side on which the insulating film 10 or the semiconductor layer 20 is formed with respect to the metal foil 50 as “upward”, and the semiconductor layer 20 with respect to the metal foil 50 as a reference. The side where no is formed is defined as “downward”.
- FIG. 1 shows a flexible semiconductor device 100A in which a source electrode 50s, a drain electrode 50d, and a gate electrode 50g are formed on the same plane.
- FIG. 2 shows how the gate electrode 50g has a source electrode 50s and a drain electrode 50d.
- a flexible semiconductor device 100B formed on non-coplanar surfaces is shown.
- the flexible semiconductor devices 100A and 100B obtained by the manufacturing method of the present invention include a semiconductor layer 20 constituting a TFT, an insulating film (protective layer) 10, A source electrode 50s, a drain electrode 50d, source and drain extraction electrode patterns 30s and 30d, and a gate electrode 50g are included. These various elements are laminated with each other, and an insulating film, a semiconductor layer, and extraction electrode patterns (10, 20, 30s, 30d) are sealed with a sealing resin layer 40.
- flexible semiconductor devices 100A and 100B shown in FIG. 1 and FIG. 2 each include source electrode 50s formed by etching insulating film 10 and metal foil 50 located on the lower surface of insulating film 10. And a drain electrode 50d, a semiconductor layer 20 formed on a part of the upper surface of the insulating film 10, and extraction electrode patterns 30s and 30d for the source electrode 50s and the drain electrode 50d, respectively.
- the sealing resin layer 40 is provided so as to enclose the source / drain extraction electrode patterns 30 s and 30 d, the semiconductor layer 20, and the insulating film 10.
- the gate electrode 50g is formed on the same surface as the surface S1 on which the source electrode 50s and the drain electrode 50d are formed, among the surfaces of the sealing resin layer 40.
- the gate electrode 50g is formed on the surface S2 opposite to the surface S1 on which the source electrode 50s and the drain electrode 50d are formed, among the surfaces of the sealing resin layer 40. Is formed.
- the insulating film 10 functions as a protective layer that protects the semiconductor layer 20.
- a resin-based or inorganic insulating-based film having insulating characteristics is used as the insulating film 10.
- An example of the inorganic insulator system may be tantalum oxide, and an example of the resin system may be polyphenylene ether resin.
- the semiconductor layer 20 is provided on the insulating film 10, as shown in the drawing (see FIG. 1B or FIG. 2B), the semiconductor layer 20 is a part of the upper surface of the insulating film 10 (see FIG. In the vicinity of the center) and is arranged so as to cover the extending portions 32s, 32d of the extraction electrode patterns 30s, 30d.
- the lower surface of the peripheral portion of the semiconductor layer 20 provided on the insulating film 10 is partially in contact with the upper surfaces of the peripheral portions of the extraction electrode patterns 30s and 30d for the source electrode and the drain electrode.
- the semiconductor layer 20 include a semiconductor layer made of silicon (eg, amorphous silicon) or an oxide semiconductor layer (eg, a semiconductor layer made of zinc oxide).
- the extraction electrode patterns 30 s and 30 d are in contact with the semiconductor layer 20. That is, a part 32 s of the extraction electrode pattern 30 s and a part 32 d of the extraction electrode pattern 30 d extend to the upper surface of the insulating film 10 and are in contact with the semiconductor layer 20.
- the flexible semiconductor devices 100A and 100B can be operated without the extending portions 32s and 32d. However, by providing the extending portions 32s and 32d, the channel length (here, the distance between the extraction electrode 30s and the extraction electrode 30d) can be shortened, and as a result, the speed can be increased due to the shortening of the channel length. It becomes possible to plan.
- the material of the extraction electrode pattern 30s, 30d may be the like of various metal materials or conductive oxide such as RuO 2.
- the sealing resin layer 40 is provided so as to cover the semiconductor layer 20, the insulating film 10, and the extraction electrode patterns 30 s and 30 d, but has flexibility and is used for “sealing” as the name suggests. To get.
- a resin material having flexibility after curing is preferable, and examples thereof include a polyphenylene ether resin and a polyethylene naphthalate resin.
- the source electrode 50S and the drain electrode 50d are formed below the insulating film 10.
- the source electrode 50S and the drain electrode 50d are formed on the lower surface S1 of the sealing resin layer 40 formed by sealing the insulating film 10, the semiconductor layer 20, and the extraction electrode patterns 30s and 30d.
- the source electrode 50S and the drain electrode 50d are formed by etching a metal foil that functions as a support for supporting each layer (10, 20, 30s, 30d, 40) constituting the TFT in the manufacturing process. It is.
- the electrode material is preferably a metal material having good conductivity, and examples thereof include copper (Cu).
- the gate electrode 50g of the flexible semiconductor device 100A shown in FIG. 1 is formed on the same surface as the surface S1 on which the source electrode 50s and the drain electrode 50d are formed.
- the gate electrode 50g can be formed by etching the same metal foil as that used for forming the source electrode 50S and the drain electrode 50.
- the source electrode 50s and the drain electrode 50d are formed on non-coplanar surfaces.
- the gate electrode 50g is located above the semiconductor layer 20 with the sealing resin layer 40 interposed therebetween. That is, the gate electrode 50g in FIG.
- the gate electrode 50g shown in FIG. 2 can be formed by etching a further metal foil provided on the upper surface of the sealing resin layer 40.
- the material of the gate electrode 50g is preferably a metal material having good conductivity, for example, copper (Cu).
- the electrodes constituting the TFT element are formed by etching a metal foil. It may have a taper shape in the thickness direction.
- the taper angle ⁇ can be about 1 ° to 60 °, for example, about 5 ° to 30 °. If the electrodes constituting the TFT element have a tapered shape in this way, the pattern step coverage when the electrodes and wiring patterns are later sealed and protected with an insulating film (step coverage) becomes good, and the reliability is high. Sex can be obtained.
- the electrodes constituting the TFT element are formed by etching the metal foil.
- the thickness is larger than the electrode thickness (about 0.1 ⁇ m) obtained by a conventional electrode forming method (for example, vapor deposition or sputtering).
- the electrode thickness is 4 ⁇ m to about 20 ⁇ m. ing.
- step (Embodiment 1) As the first embodiment, a method for manufacturing the flexible semiconductor device 100A will be described with reference to FIGS. 4 (a) to 4 (e).
- step (i) is first carried out. That is, the insulating film 10 is formed on the upper surface 54 of the metal foil 50 as shown in FIG.
- the metal foil 50 used functions as a support for the insulating film, the extraction electrode pattern, the semiconductor layer, and / or the sealing resin layer in the manufacturing process. It also functions as an electrode constituent material.
- the metal constituting the metal foil 50 is preferably a metal having conductivity and a relatively high melting point, such as copper (Cu, melting point: 1083 ° C.), nickel (Ni, melting point: 1453 ° C.), Examples include aluminum (Al, melting point: 660 ° C.) and stainless steel (SUS).
- the thickness of the metal foil 50 is preferably in the range of about 4 ⁇ m to about 20 ⁇ m, more preferably in the range of about 8 ⁇ m to about 16 ⁇ m, for example about 12 ⁇ m.
- the insulating film 10 formed on the metal foil 50 is, for example, an inorganic insulating film 10.
- the inorganic insulating insulating film 10 include, for example, tantalum oxide (Ta 2 O 5 or the like), aluminum oxide (Al 2 O 3 or the like), silicon oxide (SiO 2 or the like), zeolite oxide (ZrO). 2 ), titanium oxide (TiO 2 etc.), yttrium oxide (Y 2 O 3 etc.), lanthanum oxide (La 2 O 3 etc.), hafnium oxide (HfO 2 etc.), Examples thereof include films made of such metal nitrides.
- a film made of a dielectric material such as barium titanate (BaTiO 3 ), strontium titanate (SrTiO 3 ), calcium titanate (CaTiO 3 ), or the like may be used.
- the insulating film 10 may be a resin-based insulating film.
- the resin-based insulating film 10 include films made of epoxy resin, polyimide (PI) resin, polyphenylene ether (PPE) resin, polyphenylene oxide resin (PPO), polyvinyl pyrrolidone (PVP) resin, and the like.
- the inorganic insulating system has a higher dielectric constant than the resin-based insulating film, and is therefore preferable as a material for the gate insulating film of the flexible semiconductor device.
- the formation of the insulating film 10 on the metal foil 50 is not particularly limited.
- the metal foil 50 for example, copper foil
- the insulating film 10 can be formed by a high temperature process.
- an insulating film 10 made of a metal oxide can be formed by applying a precursor such as an organic metal to a surface on which a metal foil (copper foil) 50 is to be formed, and baking it at 800 ° C.
- the inorganic insulator can be formed on the formation surface of the metal foil 50 by a thin film forming method such as a sputtering method using a mask.
- the preferred thickness of the insulating film 10 may vary depending on the required TFT characteristics, but is about 2 ⁇ m or less, more preferably in the range of about 0.1 ⁇ m to about 2 ⁇ m, and still more preferably about 0.2 ⁇ m to The range is about 1 ⁇ m.
- tantalum oxide (Ta 2 O 5 ) having a thickness of 0.3 ⁇ m can be formed on the formation surface of the metal foil 50 by using a sputtering method.
- step (ii) is performed. That is, as illustrated in FIG. 4B, the source extraction electrode pattern 30 s and the drain extraction electrode pattern 30 d are formed on the upper surface 54 of the metal foil 50.
- Examples of the material of the extraction electrode patterns 30s and 30d include gold (Au), silver (Ag), copper (Cu), nickel (Ni), chromium (Cr), cobalt (Co), magnesium (Mg), and calcium ( Metal materials such as Ca), platinum (Pt), molybdenum (Mo), iron (Fe), zinc (Zn), titanium (Ti), tungsten (W), tin oxide (SnO 2 ), indium tin oxide (ITO) ), Fluorine-containing tin oxide (FTO), ruthenium oxide (RuO 2 ), iridium oxide (IrO 2 ), and conductive oxides such as platinum oxide (PtO 2 ).
- the method of forming the extraction electrode patterns 30s and 30d is not particularly limited.
- the metal foil 50 for example, copper foil
- the extraction electrode patterns 30s and 30d can also be formed by a high temperature process.
- it can be easily performed by vacuum deposition or sputtering.
- Other methods for example, a method of printing and curing an organic metal paste, a method of printing and baking nano metal particle ink by an ink jet method, etc. may be used.
- the formed extraction electrode patterns 30 s and 30 d are preferably laminated on the upper surface 54 of the metal foil 50 so as to partially overlap the insulating film 10 as shown in FIG. That is, it is preferable to form the extraction electrode patterns 30 s and 30 d on the metal foil 50 so that a part thereof extends onto the metal foil 50.
- the thickness of the extraction electrode patterns 30s and 30d to be formed is preferably in the range of about 50 nm to about 150 nm, more preferably in the range of about 80 nm to about 120 nm.
- a RuO 2 layer having a thickness of 100 nm may be laminated so as to cover the insulating film 10 by sputtering.
- step (iii) is performed. That is, the semiconductor layer 20 is formed on the insulating film 10 as shown in FIG. The semiconductor layer 20 is formed so that the semiconductor layer 20 is in contact with the extraction electrode patterns 30s and 30d.
- Various semiconductors can be used as the semiconductor constituting the semiconductor layer 20.
- a semiconductor such as silicon (for example, Si) or germanium (Ge) may be used, or an oxide semiconductor may be used.
- the oxide semiconductor include simple oxides such as zinc oxide (ZnO), tin oxide (SnO 2 ), indium oxide (In 2 O 3 ), and titanium oxide (TiO 2 ), InGaZnO, InSnO, InZnO, and ZnMgO.
- a compound semiconductor for example, GaN, SiC, ZnSe, CdS, GaAs, etc.
- an organic semiconductor for example, pentacene, poly-3-hexylthiophene, porphyrin derivative, copper phthalocyanine, C60, etc.
- the semiconductor layer 20 can be formed, for example, by depositing a semiconductor material at a position where the insulating film 10 is formed.
- a vacuum evaporation method, a sputtering method, a plasma CVD method, or the like can be used as appropriate.
- a silicon film is deposited on the formation position of the insulating film 10 provided on the metal foil 50 heated to 350 ° C. using a plasma CVD method, and the deposited silicon film is placed in an inert atmosphere (typically In a non-oxidizing atmosphere) By performing a thermal annealing process at 600 ° C., polysilicon can be formed.
- the semiconductor layer 20 can be formed using a high-temperature process.
- a resin (plastic) substrate when the semiconductor layer is directly formed on the resin substrate, the heat resistance of the resin substrate is low, so that the process temperature must be limited to be low.
- the process temperature (high temperature) exceeding the heat resistance temperature of the sealing resin layer 40 is used even though the sealing resin layer 40 having low heat resistance is used as the base material.
- the semiconductor layer 20 can be formed by the process.
- a high temperature process exceeding 180 ° C. (more preferably a high temperature process of 400 ° C. to 1000 ° C.) is actively applied to the manufacturing process of the semiconductor layer 20. Can be adopted.
- the semiconductor layer formation step can be performed by a high-temperature process of 180 ° C. or higher, more preferably about 400 ° C. to 1000 ° C. Further, due to the use of such metal foil, the obtained semiconductor layer can be positively subjected to heat treatment.
- the method of the heat treatment is not particularly limited, and may be, for example, a thermal annealing treatment (atmosphere heating), or a laser annealing treatment, and more specifically, a combination thereof.
- a thermal annealing treatment atmosphere heating
- a laser annealing treatment and more specifically, a combination thereof.
- a semiconductor layer made of amorphous silicon is formed at a position where the insulating film 10 is formed, it may be annealed with a laser.
- the crystallization of the semiconductor proceeds and the characteristics of the semiconductor (for example, carrier mobility) can be improved.
- annealing substantially means a heat treatment for the purpose of improving mobility and stabilizing characteristics.
- an organic silicon compound for example, cyclopentasilane
- an organic metal mixture at a position where the insulating film 10 is formed and heat-treat (for example, 600 ° C. or higher) to sinter the metal and form an oxide semiconductor.
- heat-treat for example, 600 ° C. or higher
- the semiconductor layer 20 is preferably formed without protruding from the upper surface of the insulating film 10.
- the sealing resin layer 40 is used as a constituent element of the TFT, the semiconductor layer 20 may be deteriorated due to the presence of water vapor or oxygen contained in the sealing resin layer 40. Therefore, by forming the semiconductor layer 20 without protruding from the upper surface of the insulating film 10, the insulating film 10 can suitably function as a protective layer that protects the semiconductor layer 20.
- the thickness of the formed semiconductor layer 20 is preferably in the range of about 10 nm to about 150 nm, more preferably in the range of about 20 nm to about 80 nm.
- step (iv) is performed. That is, as shown in FIG. 4D, the sealing resin layer 40 is formed on the upper surface 54 of the metal foil 50 so as to cover the semiconductor layer 20 and the extraction electrode patterns 30s and 30d.
- the resin material of the sealing resin layer 40 a material having flexibility after curing is preferable.
- resin materials include epoxy resins, polyimide (PI) resins, acrylic resins, polyethylene terephthalate (PET) resins, polyethylene naphthalate (PEN) resins, polyphenylene sulfide (PPS) resins, and polyphenylene ether (PPE) resins. Or a composite thereof. These resin materials are excellent in properties such as dimensional stability, and are preferable for the production method of the present invention.
- the method for forming the sealing resin layer 40 is not particularly limited, and any method can be used as long as the sealing resin layer can be formed on the upper surface of the metal foil so as to cover the semiconductor layer and the extraction electrode pattern. It may be used.
- the sealing resin layer 40 can be formed by applying and drying an uncured liquid resin (for example, a coating agent in which a resin material is mixed in a liquid medium) on the upper surface of the metal foil 50 by spin coating or the like.
- the semiconductor layer 20 can be suitably sealed.
- the sealing resin layer 40 may be formed by a method in which an uncured resin previously formed into a film shape is bonded to the upper surface 54 of the metal foil 50 and cured. Furthermore, a method may be employed in which an adhesive material is applied to the surface of a resin previously formed into a film shape, and the surface to which the adhesive material is applied is bonded to the upper surface 54 of the metal foil 50. As a method of bonding the sealing resin layer 40 and the metal foil 50, a method of applying pressure by roll lamination, vacuum lamination, pressing, or the like may be appropriately employed.
- the semiconductor layer 20 and the extraction electrode patterns 30 s and 30 d are embedded in the lower surface of the sealing resin layer 40, and the semiconductor layer 20 can be sealed with the sealing resin layer 40.
- an adhesive epoxy resin may be applied to the lower surface of a polyethylene naphthalate (PEN) resin film, and the surface coated with the epoxy resin may be bonded to the upper surface of the metal foil 50.
- PEN polyethylene naphthalate
- the thickness of the sealing resin layer 40 formed in step (iv) is preferably in the range of about 1 ⁇ m to about 7 ⁇ m, more preferably in the range of about 2 ⁇ m to about 5 ⁇ m. Since the sealing resin layer 40 can also function as a gate insulating film, the thickness of the sealing resin layer 40 is preferably thin from the viewpoint of lowering the gate voltage, and in that respect, 5 ⁇ m or less is preferable. You may adjust suitably according to the TFT characteristic etc. which are required.
- Step (v) is performed subsequent to step (iv). That is, as shown in FIG. 4E, the metal foil 50 is etched to form an electrode. Specifically, the source electrode 50 s and the drain electrode 50 d are formed by etching the metal foil 50. In particular, in the illustrated embodiment, the gate electrode 50 g is also formed by etching the metal foil 50.
- the etching method is not particularly limited, and a conventionally known method (typically etching using a photolithography process) may be used.
- the source electrode 50s is formed to be connected to the source extraction electrode pattern 30s by patterning the metal foil 50, and the drain electrode 50d is connected to the drain extraction electrode pattern 30d. Forming.
- the flexible semiconductor device 100A including the semiconductor layer 20, the insulating film 10, the gate electrode 50g, the source electrode 50s, and the drain electrode 50d is constructed as a TFT element. Can do.
- the insulating film 10 and the semiconductor layer 20 are formed on the metal foil 50 as described above.
- the sealing resin layer 40 is formed on the metal foil 50 so as to cover the semiconductor layer 20, and then the metal foil 50 is etched to form the source electrode 50s, the drain electrode 50d, and the gate electrode 50g. . Therefore, the metal foil 50 that is the support can be used as an electrode of the TFT (source, drain, and gate electrodes), and there is no need to finally peel off the metal foil 50 that is the support. Therefore, the TFT element can be manufactured by a simple process, and the productivity of the flexible semiconductor device is excellent.
- a support substrate for example, a glass substrate. Therefore, for example, it is necessary to perform a process for reducing the adhesion between the support substrate and the TFT element. Alternatively, it is necessary to form a peeling layer between the support substrate and the TFT element, and to perform a process of physically or chemically removing the peeling layer. In other words, the TFT manufacturing method using a typical transfer method leaves a problem in terms of productivity. On the other hand, in the manufacturing method of the present invention, it is not necessary to finally peel off the metal foil 50 that is the support, so that the complexity of the process is reduced.
- the sealing resin layer 40 is formed on the metal foil 50 after the insulating film 10 and the semiconductor layer 20 are formed on the metal foil 50, the insulating film 10 and The production of the semiconductor layer 20 can be performed by a high temperature process, and the performance of the obtained TFT is improved. That is, in a TFT manufacturing method that is directly formed on a resin substrate without using a transfer method, the resin substrate has low heat resistance, so the process temperature needs to be limited low, and the TFT performance tends to be inferior.
- the encapsulating resin layer having a low heat resistance for example, a polyethylene naphthalate (PEN) resin film having a heat resistant temperature of 180 ° C.
- PEN polyethylene naphthalate
- a high-temperature process at 400 ° C. or higher for example, heat treatment such as annealing
- TFT characteristics for example, carrier mobility of a semiconductor
- Embodiment 2 described below is a method for manufacturing the flexible semiconductor device 100B described above. That is, the manufacturing method of the second embodiment is a manufacturing method of a flexible semiconductor device in which the gate electrode 50g is “non-coplanar” with respect to the source electrode 50s and the drain electrode 50d as shown in FIG.
- step (i) the insulating film 10 is formed on the upper surface 54 of the metal foil 50.
- the metal foil 50 used functions as a support for the insulating film, the extraction electrode pattern, the semiconductor layer, and / or the sealing resin layer in the manufacturing process. It also functions as an electrode constituent material.
- step (ii) a source extraction electrode pattern 30 s and a drain extraction electrode pattern 30 d are formed on the upper surface 54 of the metal foil 50.
- step (iii) the semiconductor layer 20 is formed on the insulating film 10 so as to be in contact with the extraction electrode patterns 30s and 30d.
- a sealing resin layer 40 is formed on the metal foil 50 so as to cover the semiconductor layer 20 and the extraction electrode patterns 30s and 30d.
- an adhesive epoxy resin is applied to the lower surface of a resin film (for example, a polyethylene naphthalate resin film having a thickness of about 3 ⁇ m), and the surface coated with the epoxy resin is bonded to the upper surface of the metal foil 50.
- the sealing resin layer 40 is formed.
- a further metal foil 52 is formed on the sealing resin layer 40 (see FIGS. 6A and 6B).
- a further metal foil 52 is separately prepared and bonded to the upper surface of the sealing resin layer 40.
- the metal constituting the metal foil 52 is preferably a metal having conductivity and a relatively high melting point, such as copper (Cu, melting point: 1083 ° C.), nickel (Ni, melting point: 1453 ° C.), aluminum (Al, Al, Melting point: 660 ° C.) and stainless steel (SUS) can be used.
- the thickness of the metal foil 52 is preferably in the range of about 4 ⁇ m to about 20 ⁇ m, more preferably in the range of about 8 ⁇ m to about 16 ⁇ m, for example, about 12 ⁇ m.
- the metal foil 52 on the sealing resin layer 40 is performed by applying an adhesive epoxy resin on the upper surface of the sealing resin layer 40 and bonding the surface on which the epoxy resin is applied to the lower surface of the further metal foil 52. It's okay. By doing so, the sealing resin layer 40 and the further metal foil 52 are suitably integrated.
- the lamination of the metal foil 50 and the further lamination of the metal foil 52 may be executed in the same process or may be executed in separate processes.
- the metal foil 50 as the support is then etched as shown in FIG. 50d is formed, and the metal foil 52 is etched to form the gate electrode 50g.
- a flexible semiconductor device 100B including the semiconductor layer 20, the insulating film 10, the gate electrode 50g, the source electrode 50s, and the drain electrode 50d can be constructed as TFT elements.
- the semiconductor layer 20 of the sealing resin layer 40 A portion sandwiched between the gate electrode 50 g functions as the gate insulating film 42.
- the semiconductor layer 20 is formed from above the extraction electrode patterns 30 s and 30 d, and a part of the periphery of the semiconductor layer 20 is an extension portion 32 s of the extraction electrode patterns 30 s and 30 d, although it covers 32d, the form / formation order may be reversed.
- the extraction electrode patterns 30 s and 30 d may be formed from above the semiconductor layer 20. More specifically, in the flexible semiconductor device 100C shown in FIGS. 7A and 7B, the extending portions 32s and 32d of the extraction electrode patterns 30s and 30d are arranged so as to cover a part of the semiconductor layer 20. ing.
- the flexible semiconductor device 100C shown in FIGS. 7A and 7B is a semiconductor device in which the source electrode 50s, the drain electrode 50d, and the gate electrode 50g are formed on the same plane.
- FIGS. 8 (a) to 8 (e) An example of the manufacturing process of the flexible semiconductor device 100C will be described with reference to FIGS. 8 (a) to 8 (e). Note that the description of the same points as the manufacturing method of the flexible semiconductor devices 100A and 100B described above is omitted.
- the gate insulating film 10 is formed on the upper surface 54 of the metal foil 50, and then, as shown in FIG. 8B, the semiconductor layer 20 is formed on the upper surface of the gate insulating film 10.
- the method for forming the semiconductor layer 20 is not particularly limited, and may be formed, for example, in the same manner as in Embodiment 1 described above.
- Electrode patterns 30s and 30d are formed. As illustrated, the source extraction electrode pattern 30 s is formed so as to cover the left end side portion of the semiconductor layer 20 and the left end side portion of the gate insulating film 10. Similarly, the drain extraction electrode pattern 30 d is formed so as to cover the right end side portion of the semiconductor layer 20 and the right end side portion of the gate insulating film 10.
- the sealing resin layer 40 is formed on the upper surface 54 of the metal foil 50 so as to cover the semiconductor layer 20 and the extraction electrode patterns 30s and 30d.
- the metal foil 50 is etched to form a gate electrode 50g, a source electrode 50s, and a drain electrode 50d. In this way, a flexible semiconductor device 100C as shown in FIGS. 7A and 7B can be obtained easily and stably.
- extraction electrode patterns 30 s and 30 d are formed from above the semiconductor layer 20 in the flexible semiconductor device 100 ⁇ / b> D shown in FIGS. 9A and 9B. That is, the extending portions 32 s and 32 d of the extraction electrode patterns 30 s and 30 d are arranged so as to cover a part of the semiconductor layer 20.
- the difference from the flexible semiconductor device 100C of the third embodiment is that in the flexible semiconductor device 100D shown in FIGS. 9A and 9B, the gate electrode 50g is “non-coplanar” with respect to the source electrode 50s and the drain electrode 50d. It is formed.
- FIGS. 10 (a) to 10 (c) An example of a manufacturing process of the flexible semiconductor device 100D will be described with reference to FIGS. 10 (a) to 10 (c) and FIGS. 11 (a) to 11 (c).
- the semiconductor layer 20 is formed on the insulating film 10 as shown in FIG. 10B.
- at least two extraction electrode patterns 30 s and 30 d are formed on the metal foil 50 so as to be in contact with the semiconductor layer 20.
- a source extraction electrode pattern 30 s and a drain extraction electrode pattern 30 d are formed so as to cover a part of the peripheral edge of the semiconductor layer 20 and a part of the peripheral edge of the insulating film 10.
- a sealing resin layer 40 is formed on the metal foil 50 so as to cover the insulating film 10, the semiconductor layer 20, and the extraction electrode patterns 30s and 30d.
- the source electrode 50s and the drain electrode 50d are formed by etching the metal foil 50 as shown in FIG.
- FIG. 11C the surface of the sealing resin layer 40 opposite to the surface (the lower surface in the figure) on which the source electrode 50s and the drain electrode 50d are formed (the upper surface in the figure).
- the step of forming the gate electrode 50g is performed.
- the gate electrode 50 g is formed directly on the sealing resin layer 40.
- the method of directly forming the gate electrode 50g on the sealing resin layer 40 is not particularly limited, and can be performed by, for example, a vacuum evaporation method using a mask or a sputtering method. Alternatively, a method of printing and baking an organic metal by an ink jet method may be used.
- the flexible semiconductor device 100D can be constructed through the above steps.
- the insulating film constituting the gate insulating film 10 is provided only in the lower surface region of the semiconductor layer 20, but the invention is not limited to this.
- an insulating film that is, the insulating film 12
- the insulating film 12 is disposed so as to cover the entire lower surface of the sealing resin layer 40 (except for the positions where the extraction electrode patterns 30s and 30d are formed).
- a flexible semiconductor device 100E shown in FIG. 12 is a semiconductor device in which the source electrode 50s, the drain electrode 50d, and the gate electrode 50g are formed on the same plane.
- a metal foil 50 whose upper surface is previously coated with an insulating film 12 is prepared.
- the metal foil 50 may be a stainless steel (SUS) foil, for example.
- the insulating film 12 may be formed in the same manner as in the first embodiment.
- the semiconductor layer 20 is formed on part of the upper surface of the insulating film 12.
- the semiconductor layer 20 may be formed in the same manner as in the first embodiment.
- the opening parts 15 and 17 which expose the metal foil 50 located on the lower surface are formed.
- the openings 15 and 17 are through-holes penetrating the front and back surfaces of the entire insulating film 12, and are portions that become contacts of extraction electrode patterns 30s and 30d described later.
- the shape of the openings 15 and 17 is not particularly limited, and may be, for example, a circular shape.
- the partial removal of the insulating film 12 can be performed using, for example, laser irradiation, etching, a lift-off method, or the like.
- extraction electrode patterns 30 s and 30 d that are in contact with the semiconductor layer 20 are formed on the upper surface of the metal foil 50 where the openings 15 and 17 are exposed.
- the extraction electrode pattern 30 s for the source electrode 50 s is formed on the upper surface of the metal foil 50 exposed at the left opening 15, and the drain is formed on the upper surface of the metal foil 50 exposed at the right opening 17.
- An extraction electrode pattern 30d for the electrode 50d is formed.
- the extraction electrode patterns 30s and 30d can be formed in the same manner as in the first embodiment.
- a sealing resin layer 40 is formed on the upper surface of the metal foil 50 so as to cover the semiconductor layer 20 and the extraction electrode patterns 30s and 30d. Then, as shown in FIG. 13E, the metal foil 50 is etched to form a gate electrode 50g, a source electrode 50s, and a drain electrode 50d. In this way, a flexible semiconductor device 100E as shown in FIG. 12 can be obtained easily and stably.
- the insulating film is formed in a region other than the lower surface of the semiconductor layer 20.
- the gate electrode 50g is formed in “non-coplanar” with respect to the source electrode 50s and the drain electrode 50d. .
- FIGS. 15A to 15E can be manufactured through the manufacturing steps shown in FIGS. 15A to 15E, for example.
- FIG. 15A a metal foil 50 whose upper surface is previously coated with an insulating film 12 is prepared.
- the semiconductor layer 20 is formed on part of the upper surface of the insulating film 12.
- FIG. 15B by removing a part of the insulating film 12, a part of the metal foil 50 located on the lower surface of the insulating film 12 is exposed to form openings 15 and 17. .
- FIG. 15C extraction electrode patterns 30 s and 30 d that are in contact with the semiconductor layer 20 are formed on the upper surface of the metal foil 50 exposed at the openings 15 and 17.
- a sealing resin layer 40 is formed on the upper surface of the metal foil 50 so as to cover the semiconductor layer 20 and the extraction electrode patterns 30s and 30d.
- the metal foil 50 is etched to form the source electrode 50s and the drain electrode 50d.
- the gate electrode 50g is formed on the surface of the sealing resin layer 40 opposite to the surface on which the source electrode 50s and the drain electrode 50d are formed. The formation of the gate electrode 50g may be performed in the same manner as in the second and fourth embodiments. In this way, a flexible semiconductor device 100F as shown in FIG. 14 can be obtained easily and stably.
- FIG. 16A is a top view of the flexible semiconductor device 100G
- FIG. 16B is a cross-sectional view showing a IXb-IXb cross section of FIG.
- a flexible semiconductor device 100G mounted on an image display device includes at least two TFT elements each including a semiconductor layer, a gate insulating film, a gate electrode, a source electrode, and a drain electrode. Have.
- the number of TFTs per pixel is two, and the flexible semiconductor device includes a first TFT element 100Ga and a second TFT element 100Gb.
- the gate electrode 50Ag, the source electrode 50As, and the drain electrode 50Ad that constitute the first TFT element 100Ga, and the gate electrode 50Bg, the source electrode 50Bs, and the drain electrode 50Bd that constitute the second TFT element 100Gb are: It is formed on the same surface (lower surface in the figure) of the sealing resin layer 40. That is, the first TFT element 100Ga and the second TFT element 100Gb are arranged side by side with respect to the same surface of the sealing resin layer 40. The first TFT element 100Ga and the second TFT element 100Gb are electrically connected via a wiring 85.
- the first TFT element 100Ga is a switching transistor
- the second TFT element 100Gb is a driving transistor
- the drain electrode 50Ad of the first TFT element (for switching) 100Ga and the gate electrode 50Bg of the second TFT element (for driving) 100Gb are preferably electrically connected via the wiring 85.
- the wiring 85 can be formed by etching the metal foil 50 in the same manner as the gate, source and drain electrodes constituting each element.
- the illustrated flexible semiconductor device 100G includes a capacitor 80.
- the capacitor 80 holds a capacity for driving the driving TFT element 100Gb.
- the capacitor 80 includes a dielectric layer 82, an upper electrode layer 84, and a lower electrode layer 86.
- the capacitor 80 of the flexible semiconductor device 100G will be described in detail.
- the dielectric layer 82 of the capacitor 80 is made of the same material as the gate insulating films 10A and 10B constituting each element and is arranged in parallel with them. That is, the lower surface of the dielectric layer 82 and the lower surfaces of the gate insulating films 10A and 10B are located on the same plane.
- the upper electrode layer 84 of the capacitor 80 is made of the same material as the extraction electrode patterns 30As, 30Ad, 30Bs, 30Bd constituting each element, and is arranged in parallel therewith.
- the lower electrode layer 86 of the capacitor 80 is made of the same material as the gate, source and drain electrodes 50Ag, 50As, 50Ad, 50Bg, 50Bs, and 50Bd constituting each element, and is arranged in parallel therewith. That is, the lower electrode layer 86 of the capacitor 80 can be formed by etching the metal foil 50 in the same manner as the electrodes constituting each element.
- the lower electrode layer 86 of the capacitor 80 is connected to the drain electrode 50Ad for switching and the gate electrode 50Bg for driving.
- the upper electrode layer 84 of the capacitor 80 is connected to the driving source electrode 50Bs via the wiring 88.
- charge is held for a period selected by the switching TFT element 100Ga, and a voltage generated by the charge is applied to the gate of the driving TFT element 100Gb. Then, a drain current corresponding to the voltage flows through the organic EL element, thereby causing the pixel to emit light.
- a TFT element for driving a display which is an important application of a flexible semiconductor device, requires a capacitor for holding a capacity in order to drive the element.
- the capacitor 80 can be directly formed on the sealing resin layer 40, and a separate capacitor need not be disposed outside the flexible semiconductor device. Therefore, according to the present invention, it is possible to realize a small image display apparatus that can be mounted at high density.
- the dielectric layer 82 of the capacitor 80 can be made of the same material as the gate insulating films 10A and 10B. Further, the upper electrode layer 84 of the capacitor 80 can be taken out and made of the same material as the electrode patterns 30As, 30Ad, 30Bs, 30Bd. Furthermore, the lower electrode layer 86 of the capacitor 80 can be made of the same material as the gate, source and drain electrodes 50Ag, 50As, 50Ad, 50Bg, 50Bs, and 50Bd. Therefore, the capacitor 80, the first TFT element 100Ga, and the second TFT element 100Gb can be manufactured in the same process. As a result, it can be said that the flexible semiconductor device 100G can be produced efficiently.
- the dielectric layer 82 of the capacitor 80 may be formed on the metal foil 50 together with the gate insulating film 10 in the step of forming the gate insulating film 10 shown in FIG. .
- the upper electrode layer 84 of the capacitor 80 may be formed on the dielectric layer 82 together with the extraction electrode patterns 30s and 30d.
- the lower electrode layer 86 of the capacitor may be formed together with the gate electrode, the source electrode, and the drain electrode by etching the metal foil 50.
- a flexible semiconductor device 100H as shown in FIG. 17 may be used as an aspect of the flexible semiconductor device that can be preferably mounted on the image display device.
- An embodiment of the flexible semiconductor device 100H will be described with reference to FIGS. 17 (a) to (c).
- 17A is a top view of the flexible semiconductor device 100H
- FIG. 17B is a cross-sectional view showing the XVb-XVb cross section of FIG. 17A
- FIG. 17C is FIG. 17A. It is sectional drawing which shows the XVc-XVc cross section.
- a flexible semiconductor device mounted on an image display device (here, an organic EL display) has at least two TFT elements each including a semiconductor layer, a gate insulating film, a gate electrode, a source electrode, and a drain electrode. is doing.
- the number of TFTs per pixel is two, and the illustrated flexible semiconductor device 100H includes a first TFT element 100Ha and a second TFT element 100Hb.
- the gate electrode 50Ag constituting the first TFT element 100Ha and the gate electrode 50Bg constituting the second TFT element 100Hb are formed on the same surface of the sealing resin layer 40 (upper surface in the figure).
- the source electrode 50As and the drain electrode 50Ad constituting the first TFT element 100Ha and the source electrode 50Bs and the drain electrode 50Bd constituting the second TFT element 100Hb are formed on the same surface of the sealing resin layer 40 (see FIG. It is the lower surface in the figure.
- the first TFT element 100Ha and the second TFT element 100Hb are electrically connected via an interlayer connection member 60 that conducts the front and back surfaces (upper surface and lower surface in the drawing) of the sealing resin layer 40. .
- the first TFT element 100Ha is a switching transistor
- the second TFT element 100Hb is a driving transistor.
- the drain electrode 50Ad of the first TFT element (for switching) 100Ha and the gate electrode 50Bg of the second TFT element (for driving) 100Hb are connected to the interlayer connection member 60. It is preferable to make an electrical connection via.
- the flexible semiconductor device 100H includes a capacitor 80 as shown in FIG.
- the capacitor 80 holds a capacity for driving the driving TFT element 100Hb.
- the capacitor 80 includes a dielectric layer 82, an upper electrode layer 84, and a lower electrode layer 86. More specifically, the upper electrode layer 84 of the capacitor 80 is made of the same material as the gate electrodes 50Ag and 50Bg constituting each element, and is arranged in parallel with them.
- the lower electrode layer 86 of the capacitor 80 is made of the same material as the source and drain electrodes 50As, 50Ad, 50Bs, and 50Bd constituting each element, and is arranged in parallel therewith.
- the dielectric layer 82 of the capacitor 80 is configured from a portion of the sealing resin layer 40 sandwiched between the upper electrode layer 84 and the lower electrode layer 86.
- the capacitor 80, the first TFT element 100Ha, and the second TFT element 100Hb may be manufactured in the same process. Further, in the etching process of the metal foil 50 as shown in FIGS. 6B and 6C, the lower electrode layer 86 of the capacitor 80 is formed when the source electrode and the drain electrode are formed, and the further metal foil 52 is formed. In the etching step, the upper electrode layer 84 of the capacitor 80 may be formed when the gate electrode is formed.
- a thickness adjusting electrode 85 that adjusts the thickness of the dielectric layer 82 of the capacitor 80 may be embedded in the sealing resin layer 40.
- the thickness adjusting electrode 85 is embedded on the lower surface side of the sealing resin layer 40 so as to be positioned on the upper surface of the lower electrode layer 86.
- the thickness adjusting electrode 85 can be made of the same material as the extraction electrode patterns 30As, 30Ad, 30Bs, and 30Bd of each element, for example, and can be manufactured in the same process as the formation of the extraction electrode pattern.
- FIG. 18 shows an equivalent circuit 90 in the flexible semiconductor devices 100G and H of the seventh and eighth embodiments.
- the wiring 92 shown in FIG. 18 is a data line, and the wiring 94 is a selection line.
- Flexible semiconductor devices 100G and 100H are formed for each pixel of each image display device. Depending on the configuration of the display, not only two TFT elements may be provided for each pixel, but more than that may be provided, so that the flexible semiconductor devices 100G and 100H can be modified accordingly.
- FIG. 19A is a top view of the flexible semiconductor device 100I
- FIG. 19B is a cross-sectional view showing a section XVIIb-XVIIb in FIG.
- the first TFT element and the second TFT element are not arranged side by side on the same surface of the sealing resin layer. Absent.
- the sealing resin layer is disposed so as to be opposed to both surfaces (upper surface and lower surface in the figure).
- the gate electrode 50Ag constituting the first TFT element 100Ia and the source electrode 50Bs and the drain electrode 50Bd constituting the second TFT element 100Ib are formed of the sealing resin layer 40. It is formed on one surface (the upper surface in the figure). Further, the source electrode 50As and the drain electrode 50Ad constituting the first TFT element 100Ia and the gate electrode 50Bg constituting the second TFT element 100Ib are on the other surface (the lower surface in the figure) of the sealing resin layer 40. Is formed. The first TFT element 100Ia and the second TFT element 100Ib are electrically connected via a wiring.
- the first TFT element 100Ia is a switching transistor
- the second TFT element 100Ib is a driving transistor
- the gate electrode 50Bg constituting the second TFT element (for driving) 100Ib and the drain electrode 50Ad constituting the first TFT element 100Ia are electrically connected via the wiring 87.
- the wiring 87 can be formed by etching the metal foil 50 as in the gate, source, and drain electrodes 50As, 50Ad, and 50Bg.
- the first TFT element 100Ia and the second TFT element 100Ib are arranged so as to face each other with the sealing resin layer 40 interposed therebetween. Therefore, the floor area of the flexible semiconductor device 100I can be reduced as compared with the flexible semiconductor device 100G (see FIG. 16) in which the elements 100Ha and 100Hb are arranged side by side on the same surface of the sealing resin layer. Moreover, the wiring length connected to each element 100Ia and 100Ib can be shortened by this, and wiring resistance can be reduced. As a result, it is possible to reduce the wiring delay that delays the rise and fall of the signal. In particular, when the screen size of the image display device is increased, the wiring delay tends to increase. Therefore, the effect of adopting the configuration of the flexible semiconductor device 100I of the ninth embodiment can be exhibited particularly well.
- the flexible semiconductor device 100I may include a capacitor 80.
- the capacitor 80 includes a dielectric layer 82, an upper electrode layer 84, and a lower electrode layer 86.
- the thickness adjusting electrode 85 is formed on the upper electrode layer 84 of the capacitor 80. As shown in the figure, the thickness of the dielectric layer 82 can be reduced by embedding the thickness adjusting electrode 85 on the upper surface side of the sealing resin layer 40.
- 20A to 20C are process cross-sectional views of the flexible semiconductor device 100I in the XVIIb-XVIIb cross section of FIG. 19A.
- a first metal foil 50A, a second metal foil 50B, and one sealing resin film 40 are prepared.
- the first metal foil 50A is a metal foil at the stage before various electrodes are formed, and has a semiconductor layer forming surface (upper surface in the figure) 54A on which the semiconductor layer 20A is formed via the insulating film 10A. is doing.
- the second metal foil 50B is a metal foil at a stage before various electrodes are formed, and has a semiconductor layer forming surface (lower surface in the figure) 54B on which the semiconductor layer 20B is formed via the insulating film 10B. ing.
- the metal foils 50A and 50B having the semiconductor layer forming surfaces 54A and 54B can be manufactured through the steps shown in FIGS. 5A to 5C, for example.
- an embedding process is performed. Specifically, the semiconductor layer forming surface (upper surface in the drawing) 54A of the first metal foil 50A is superposed on one surface (lower surface in the drawing) 44 of the sealing resin film 40. By doing so, the semiconductor layer 20A and the insulating film 10A formed on the semiconductor layer forming surface 54A can be embedded in the sealing resin 40 from one surface (lower surface in the drawing) 44. Further, the semiconductor layer forming surface (lower surface in the drawing) 54B of the second metal foil 50B is overlapped with the other surface (upper surface in the drawing) 46 of the sealing resin film 40. By doing so, the semiconductor layer 20B and the insulating film 10B formed on the semiconductor layer forming surface 54B can be embedded in the sealing resin 40 from the other surface (upper surface in the drawing) 46.
- the first metal foil 50A, the sealing resin film 40, and the second metal foil 50B may be overlapped in the same process. That is, the first metal foil 50A, the sealing resin film 40, and the second metal foil 50B are aligned and overlapped so that the semiconductor layers 20A and 20B are sealed, as shown in FIG. It may be bonded and integrated.
- the integration method include a method in which the metal foils 50A and 50B are heated at a predetermined temperature and pressed by a roll laminating method, a vacuum laminating method, a hot press or the like.
- the first metal foil 50A is then etched as shown in FIG. Thereby, the source electrode 50As and the drain electrode 50Ad constituting the first TFT element 100Ia and the gate electrode 50Bg constituting the second TFT element 100Ib are formed. Further, by etching the second metal foil 50B, the gate electrode 50Ag constituting the first TFT element 100Ia, and the source electrode 50Bs and the drain electrode 50Bd constituting the second TFT element 100Ib are formed.
- the etching of the first metal foil 50A and the etching of the second metal foil 50B can be performed in the same process. However, the etching of the first metal foil 50A and the etching of the second metal foil 50B are not limited to being performed in the same process, and may be performed in separate processes.
- a flexible semiconductor device 100I as shown in FIGS. 19A and 19B can be obtained.
- FIGS. 21A is a top view of the flexible semiconductor device 100J
- FIG. 21B is a cross-sectional view showing the Xb-Xb cross section of FIG. 21A
- FIG. 21C is a cross-sectional view showing the Xc-Xc cross section of FIG. .
- the first TFT element and the second TFT element are arranged on the same surface of the sealing resin layer as in the ninth embodiment. Are arranged opposite to each other on both surfaces (upper surface and lower surface in the figure) of the sealing resin layer.
- the gate electrode 50Ag, the source electrode 50As, and the drain electrode 50Ad constituting the first TFT element 100Ja are formed on one surface (here, the lower surface) 44 of the sealing resin layer 40.
- the gate electrode 50Bg, the source electrode 50Bs, and the drain electrode 50Bd constituting the second TFT element 100Jb are formed on the other surface (here, the upper surface) 46 of the sealing resin layer 40.
- the first TFT element 100Ja and the second TFT element 100Jb may be electrically connected via an interlayer connection member that conducts the front and back of the sealing resin layer 40.
- This interlayer connection member may be made of, for example, a conductive paste filled in a through-hole penetrating the front and back surfaces (upper surface and lower surface) of the sealing resin layer 40.
- the first TFT element 100Ja is a switching transistor
- the second TFT element 100Jb is a driving transistor.
- the drain electrode 50Ad of the first TFT element (for switching) 100Ja and the gate electrode 50Bg of the second TFT element (for driving) 100Jb may be electrically connected via the interlayer connection member 60. .
- one TFT element 100Ja is disposed on the lower surface 44 of the sealing resin layer 40, and the other TFT element 100Jb is disposed on the upper surface 46 of the sealing resin layer 40.
- the floor area of the flexible semiconductor device 100J can be reduced compared to the flexible semiconductor device 100G (see FIG. 16) in which the elements 100Ga and 100Gb are arranged in parallel on the same surface of the sealing resin layer.
- the capacitor 80 is also formed in the flexible semiconductor device 100J. As illustrated, the capacitor 80 includes a dielectric layer 82, an upper electrode layer 84, and a lower electrode layer 86. In the illustrated embodiment, the lower electrode layer 86 of the capacitor 80 is electrically connected to the drain electrode 50Ad of the switching TFT element 100Ja. The upper electrode layer 84 of the capacitor 80 is electrically connected to the source electrode 50Bs of the driving TFT element 100Jb via the interlayer connection member 62.
- the sealing resin layer 40 a composite sealing material composed of a film-like core material 42 and resin layers 40A and 40B laminated on both surfaces of the core material 42 is used. ing.
- the core material 42 may be composed of a resin film having excellent dimensional stability. Examples of the resin material of the core material 42 include epoxy resin, polyimide (PI) resin, acrylic resin, polyethylene terephthalate (PET) resin, polyethylene naphthalate (PEN) resin, polyphenylene sulfide (PPS) resin, polyphenylene ether (PPE) resin, and the like. Can be mentioned.
- the resin material which has the characteristic which can embed semiconductor layer 20A, 20B, and has flexibility after hardening is preferable.
- the resin material which has the characteristic which can embed semiconductor layer 20A, 20B, and has flexibility after hardening is preferable.
- an uncured epoxy resin or PPE resin coated on both surfaces of the core material 42 can be used.
- the handling property and dimensional stability of the sealing resin layer 40 can be improved by sandwiching the core material 42 between the resin layers (embedded layers) 40A and 40B. Therefore, it contributes to the provision of the flexible semiconductor device 100J having excellent productivity.
- 23A to 23C are process cross-sectional views of the flexible semiconductor device 100J along the Xc-Xc cross section of FIG. 21A.
- a resin layer 40A is laminated on the lower surface of the film-like core material 42, and a resin layer 40B is laminated on the upper surface of the core material 42, respectively.
- the stop resin layer 40 is produced.
- through holes 65 and 67 are formed at predetermined positions of the produced sealing resin film 40.
- the through holes 65 and 67 can be easily formed by, for example, punching processing or laser irradiation.
- the through holes 65 and 67 are filled with a conductive paste (for example, a conductive paste made of silver powder and epoxy resin) and sealed.
- a conductive paste for example, a conductive paste made of silver powder and epoxy resin
- Interlayer connection members 60 and 62 are formed to conduct the front and back of the stop resin 40.
- the sealing resin film 40 provided with the interlayer connection members 60 and 62 is obtained.
- a first metal foil 50A having a semiconductor layer forming surface (upper surface in the figure) 54A on which the semiconductor layer 20A is formed is prepared.
- a second metal foil 50B having a semiconductor layer forming surface (lower surface in the figure) 54B on which the semiconductor layer 20B is formed is also prepared.
- the first metal foil and the second metal foil 50A, 50B can be easily manufactured through the steps as shown in FIGS. 4A to 4C, for example.
- the semiconductor layer forming surface 54A of the first metal foil 50A is overlapped with one surface 44 of the sealing resin film 40, and the first TFT element 100Ja.
- the semiconductor layer 20 ⁇ / b> A constituting the structure is embedded in the sealing resin 40 from one surface 44.
- the semiconductor layer forming surface 54A of the first metal foil 50A and the interlayer connection members 60 and 62 are positioned and pressed together so as to be connected.
- the semiconductor layer 20B constituting the second TFT element 100Jb is sealed from the other surface 46 by superimposing the semiconductor layer forming surface 54B of the second metal foil 50B on the other surface 46 of the sealing resin film 40. Embed in the stop resin 40. At this time, the semiconductor layer forming surface 54 ⁇ / b> B of the second metal foil 50 ⁇ / b> B and the interlayer connection agents 60 and 62 are positioned and pressed together so as to be connected.
- the first metal foil 50A is then etched as shown in FIGS. 23 (b) and (c). Then, the gate electrode 50Ag, the source electrode 50As, and the drain electrode 50Ad constituting the first TFT element 100Ja are formed. In this way, the first TFT element 100Ja can be constructed. Further, by etching the second metal foil 50B, the gate electrode 50Bg, the source electrode 50Bs, and the drain electrode 50Bd constituting the second TFT element 100Jb are formed.
- the sealing resin layer 40 of the flexible semiconductor device 100K illustrated in FIG. 24 has a stacked structure in which a first sealing resin layer 40A and a second sealing resin layer 40B are stacked.
- the first sealing resin 40 ⁇ / b> A constitutes the lower layer of the sealing resin layer 40
- the second sealing resin 40 ⁇ / b> B constitutes the upper layer of the sealing resin layer 40.
- the source and drain electrodes 50As, 50Ad, 50Bs, 50Bd constituting each element are formed on the outer surface (lower surface in the drawing) 41A in the stacking direction (or the thickness direction of the stacked structure) 70 of the first sealing resin layer 40A.
- the gate electrodes 50Ag and 50Bg constituting each element are formed on the inner surface (lower surface in the drawing) 41B in the stacking direction 70 of the second sealing resin layer 40B.
- the first sealing resin layer 40A and the second sealing resin layer 40B may be made of the same resin material or different resin materials, but may be made of the same material. It is preferable to do. This is because there is no difference in physical property values such as thermal expansion coefficient between resins, so that the reliability of the semiconductor device is improved.
- the boundary surfaces 41B and 43A shown in FIG. 24 substantially do not exist.
- a method for manufacturing the flexible semiconductor device 100K will be described with reference to FIGS.
- a flexible substrate 40B having a sealing resin film 40A and a wiring layer forming surface 41B on which gate electrodes 50Ag and 50Bg constituting each element are formed is prepared. Also, a first metal foil 50 having a semiconductor layer forming surface 54 on which the semiconductor layers 20A and 20B constituting each element are formed is prepared.
- the sealing resin film 40A is a resin film for constituting the first sealing resin layer 40A of the sealing resin layer 40, and an interlayer connection member 60 is formed at a predetermined position thereof.
- the flexible substrate 40B is a resin film for constituting the second sealing resin layer 40B of the sealing resin layer 40, and a wiring layer including gate electrodes 50Ag and 50Bg constituting each element is formed on the surface thereof. Has been.
- the metal foil 50 is a pre-stage metal foil in which the source and drain electrodes 50As, 50Ad, 50Bs, and 50Bd are formed by etching.
- Semiconductor layers 20A and 20B are formed on the surface of the metal foil 50 via insulating films 10A and 10B.
- the semiconductor layer forming surface 54 of the metal foil 50 is overlaid on one surface 41A of the sealing resin film 40A, thereby forming the semiconductor layers 20A and 20B constituting each element. Embedded in the sealing resin film 40A from one surface 41A. At this time, the metal foil 50 and the interlayer connection member 60 are positioned and pressed together so as to be connected.
- the wiring layer forming surface 41B of the flexible substrate 40B is placed on the surface 43A on the opposite side of the sealing resin film 40A from the surface 41A on which the metal foil 50 is pressed (that is, the surface on which the source and drain electrodes are formed). Overlapping. By doing so, the wiring layer including the gate electrodes 50Ag and 50Bg can be embedded in the surface 43A of the sealing resin film 40A. At this time, a part of the wiring layer on the wiring layer forming surface 41 ⁇ / b> B and the interlayer connection member 60 are aligned and pressed together so as to be connected.
- the sealing resin film 40A, the flexible substrate 40B, and the first metal foil 50 are integrated.
- the first metal foil 50 is etched to form the source and drain electrodes 50As, 50Ad, 50Bs, and 50Bd constituting each element.
- the first TFT element 100Ka and the second TFT element 100Kb can be constructed, and a flexible semiconductor device 100K as shown in FIG. 24 can be obtained.
- Embodiment 12 Next, the flexible semiconductor device 100L illustrated in FIG. 26 will be described.
- the gate electrode 50Ag, the source electrode 50As, and the drain electrode 50Ad constituting the first TFT element 100La are provided on any one surface of the sealing resin layer 40.
- the gate electrode 50Bg, the source electrode 50Bs, and the drain electrode 50Bd constituting the second TFT element 100Lb are provided inside the sealing resin layer 40.
- the gate electrode 50Ag, the source electrode 50As, and the drain electrode 50Ad constituting the first TFT element 100La are arranged on the outer side in the stacking direction (or the thickness direction of the stacked structure) 70 of the first sealing resin layer 40A.
- a surface (lower surface in the figure) 41A is formed.
- the gate electrode 50Bg, the source electrode 50Bs, and the drain electrode 50Bd constituting the second TFT element 100Lb are on the inner surface (lower surface in the drawing) 41B in the stacking direction 70 of the second sealing resin layer 40B. Is formed.
- the first TFT element 100La is a switching transistor
- the second TFT element 100Lb is a driving transistor.
- the sealing resin layer has a layered structure formed by laminating a plurality of resin layers, and the TFT element is formed in each layer, whereby the mounting density of the TFT elements can be further increased. . Therefore, the length of the wiring connected to each element 100La, 100Lb can be further shortened, and as a result, the wiring delay can be effectively reduced.
- the flexible semiconductor device 100L shown in the figure also includes a capacitor 80.
- the lower electrode layer 86 of the capacitor 80 is electrically connected to the drain electrode 50Ad of the first TFT element (for switch) 100La.
- the upper electrode layer 84 of the capacitor 80 is electrically connected to the source electrode 50Bs of the second TFT element (for driving) 100Lb via the interlayer connection member 62.
- the first sealing resin film 40A is prepared, and the electrode on which the gate electrode 50Bg, the source electrode 50Bs, and the drain electrode 50Bd constituting the second TFT element 100Lb are formed.
- a second sealing resin film 40B having a formation surface 41B is prepared.
- a metal foil 50A including a semiconductor layer forming surface 54A on which the semiconductor layer 20A constituting the first TFT element 100La is formed is also prepared.
- the first sealing resin film 40A is a resin film for constituting the first sealing resin layer 40A of the sealing resin 40, and interlayer connection members 60 and 62 are formed at predetermined positions thereof. ing.
- a resin film 40A can be produced, for example, through the steps shown in FIGS. 22 (a) and (b).
- the second sealing resin film 40B is a resin film for constituting the second sealing resin 40B of the sealing resin layer 40.
- a gate electrode 50Bg, a source electrode 50Bs, and a drain electrode 50Bd constituting the second TFT element 100Lb are formed on the surface.
- a gate insulating film 10B and a semiconductor layer 20B constituting the second TFT element 100Lb are embedded in the second sealing resin film 40B.
- Such a resin film 40B can be manufactured through the steps shown in FIGS. 4A to 4E, for example.
- the metal foil 50A is a pre-stage metal foil in which the gate electrode 50Ag, the source electrode 50As, and the drain electrode 50Ad are formed by etching.
- a semiconductor layer 20A is formed on the surface of the metal foil 50A via a gate insulating film 10A.
- Such a metal foil 50A can be manufactured through the steps shown in FIGS. 4A to 4C, for example.
- the semiconductor layer forming surface 54A of the metal foil 50A is superimposed on one surface 41A of the first sealing resin film 40A.
- the semiconductor layer 20A constituting the first TFT element 100La is embedded in the first sealing resin film 40A from the one surface 41A.
- the wiring 88 formed on the semiconductor layer forming surface 54A and the interlayer connection member 60, and the upper electrode layer 84 of the capacitor 80 and the interlayer connection member 62 are aligned and pressed together.
- the electrode forming surface 41B of the second sealing resin film 40B is overlaid on the other surface 43A of the first sealing resin film 40A.
- the gate electrode 50Bg, the source electrode 50Bs, and the drain electrode 50Bd constituting the second TFT element 100Lb are embedded in the first sealing resin film 40A from the other surface 43A.
- the gate electrode 50Bg formed on the electrode formation surface 41B and the interlayer connection member 60, and the source electrode 50Bs and the interlayer connection member 62 are aligned and pressed together.
- the metal foil 50A is then etched as shown in FIGS. 27 (b) and (c).
- the gate electrode 50Ag, the source electrode 50As, and the drain electrode 50Ad constituting the first TFT element 100La are formed.
- FIG. 28 is an external perspective view showing the overall appearance of the image display apparatus 1000.
- the image display device 1000 is, for example, an organic EL display. As shown in FIG. 28, the image display apparatus 1000 includes a TFT portion 1100, driver portions (1200, 1300), and an EL portion 1400. Each pixel of the TFT portion 1100 includes various flexible semiconductor devices 600 of the present invention.
- the flexible semiconductor device 600 is disposed on a reinforcing film (for example, a resin film such as PET or PEN).
- the flexible semiconductor device 600 is formed under the organic EL element included in the EL portion 1400, and the drain electrode of the driving TFT element of the flexible semiconductor device 600 is connected to the organic EL element.
- a transparent electrode is formed on the organic EL element.
- a protective film for example, a resin film such as PET or PEN is formed thereon.
- the shape of the portion where the source extraction electrode 30s and the drain extraction electrode 30d face each other is a comb-teeth shape. Good.
- the channel width can be increased while maintaining a predetermined dimension by making the shape of the portion where the source extraction electrode 30s and the drain extraction electrode 30d face each other into a comb shape.
- the length of the comb shape (the length of the portion where the source extraction electrode 30s and the drain extraction electrode 30d face each other) can be appropriately determined according to the required TFT performance. For example, when a TFT array for an organic EL display is formed, the comb-shaped length of the driving TFT element may be longer than the comb-shaped length of the switching TFT element.
- Modification 2 As shown by the flexible semiconductor devices 100N and 100N ′ in FIGS. 30A and 30B, two source extraction electrodes 30s extending straight from the source electrode 50s and three extending straight from the drain electrode 50d
- the drain electrode 30d may be alternately arranged in parallel. Even in such a shape, the extraction electrodes 30 s and 30 d constitute a “comb shape”, and the channel width can be increased.
- a protective layer (further protective layer) 16 may be formed on the semiconductor layer 20 as shown in the flexible semiconductor device 100O of FIG.
- the insulating material constituting the protective layer 16 may be the same material as the insulating material of the insulating film 10 that protects the lower surface of the semiconductor layer 20, or may be a different material.
- the semiconductor layer 20 can be further isolated from the sealing resin layer 40 by adopting a mode in which both sides of the semiconductor layer 20 are covered with the two protective layers (the insulating film 10 and the protective layer 16).
- an inexpensive sealing resin having a high impurity ion content can be used as the base material, and the manufacturing cost can be reduced.
- the protective layer (further protective layer) 16 formed on the semiconductor layer 20 also functions as a gate insulating film.
- a preferable insulating material that serves as both a protective layer and a gate insulating film for example, tantalum oxide (Ta 2 O 5 etc.), aluminum oxide (Al 2 O 3 etc.), silicon oxide (SiO 2 etc.) Zeolite oxide (such as ZrO 2 ), titanium oxide (such as TiO 2 ), yttrium oxide (such as Y 2 O 3 ), lanthanum oxide (such as La 2 O 3 ), hafnium oxide (such as HfO 2 ), etc. And metal nitrides thereof. Since these inorganic materials have a higher dielectric constant than resin-based insulating materials, they can be said to be particularly preferable as materials for gate insulating films in flexible semiconductor devices.
- a double gate structure may be adopted. That is, in addition to the gate electrode 50 g on the semiconductor layer 20, a further gate electrode 54 g may be formed below the semiconductor layer 20 via the insulating film 10. The further gate electrode 54g can be formed by etching the metal foil 50, similarly to the source electrode 50s and the drain electrode 50d.
- a double gate structure is adopted, more current can be passed between the source and drain than in the case of a single gate electrode. Further, even when the same amount of current flows as in the case of one gate electrode, the amount of current flowing per gate can be reduced, and as a result, the gate voltage can be lowered.
- the threshold voltage of the semiconductor element can be changed, so that variations in the semiconductor element can be reduced.
- one of the gate electrodes for modulation there is an advantage that different output sizes and frequency outputs can be obtained.
- a structure without the source electrode 50s and the drain electrode 50d is also conceivable. That is, by removing the metal foil 50 (the source electrode 50s and the drain electrode 50d) at the time of manufacture, the source extraction electrode pattern 30s and the drain extraction electrode pattern 30d are removed from the surface (the lower surface in the drawing) of the sealing resin layer 40. It may be exposed. When such a structure is employed, the thickness of the entire device can be reduced by the thickness of the source electrode 50s and the drain electrode 50d. The removal of the metal foil 50 (source electrode 50s and drain electrode 50d) may be performed by an etching process.
- the flexible semiconductor device 100Q may be further modified as shown in FIG.
- the source electrode 50s and the drain electrode 50d are formed on the surface opposite to the exposed surface of the extraction electrode patterns 30s, 30d (the lower surface of the sealing resin layer 40 in the figure). . That is, the source electrode 50s and the drain electrode 50d are formed on the same surface as the gate electrode 50g.
- the source electrode 50 s and the extraction electrode pattern 30 s are electrically connected via the interlayer connection member 64 that conducts the front and back of the sealing resin layer 40.
- the drain electrode 50d and the extraction electrode pattern 30d are electrically connected via the interlayer connection member 66.
- a wiring layer may be formed not only on the lower surface 41B of the flexible substrate 40B but also on the upper surface 43B.
- the wiring layers on the upper surface 43A and the lower surface 41B may be electrically connected via the interlayer connection member 62 that conducts both surfaces of the flexible substrate 40B.
- the present invention described above includes the following aspects: 1st aspect : It is a flexible semiconductor device which has flexibility , Comprising : An insulating film; A source electrode and a drain electrode formed by etching a metal foil located on the lower surface of the insulating film; A semiconductor layer formed on a part of the upper surface of the insulating film; An extraction electrode pattern for electrically connecting each of the source electrode and the drain electrode and the semiconductor layer; A sealing resin layer for sealing the extraction electrode pattern and the semiconductor layer; A flexible semiconductor device comprising: a gate electrode formed on a surface of the sealing resin layer opposite to a surface on which the source electrode and the drain electrode are formed.
- Second aspect In the first aspect, a portion of the surface of the sealing resin layer sandwiched between the semiconductor layer and the gate electrode functions as a gate insulating film.
- Third aspect The flexible semiconductor device according to the first or second aspect, wherein a protective layer made of an insulating material covering the semiconductor layer is formed on the semiconductor layer.
- Fourth aspect A flexible semiconductor device according to any one of the first to third aspects, further comprising a capacitor, wherein the electrode layer of the capacitor is formed by etching the metal foil. .
- Fifth aspect In any one of the first to fourth aspects, at least two TFT elements each including the semiconductor layer, the insulating film, the gate electrode, the source electrode, and the drain electrode are provided. And a flexible semiconductor device.
- a source electrode and a drain electrode constituting the first TFT element, and a source electrode and a drain electrode constituting the second TFT element are the other side of the sealing resin layer.
- the first TFT element and the second TFT element are electrically connected via an interlayer connection member that conducts the front surface and the back surface of the sealing resin layer.
- a flexible semiconductor device characterized in that it is connected to Eighth aspect :
- the gate electrode constituting the first TFT element and the source electrode and the drain electrode constituting the second TFT element are sealed.
- a source electrode and a drain electrode forming the first TFT element and a gate electrode forming the second TFT element are formed on one surface of the resin layer, and the other surface of the sealing resin layer.
- the first TFT element and the second TFT element are electrically connected via a wiring formed by etching the metal foil.
- Tenth aspect A method of manufacturing a flexible semiconductor device having flexibility, Preparing a metal foil; Forming an insulating film on the metal foil; Forming an extraction electrode pattern on the metal foil; Forming a semiconductor layer on the insulating film so as to be in contact with the extraction electrode pattern; Forming a sealing resin layer on the metal foil so as to cover the semiconductor layer and the extraction electrode pattern; Forming a source electrode and a drain electrode by etching the metal foil; Forming a gate electrode on a surface of the sealing resin layer opposite to a surface on which the source electrode and the drain electrode are formed.
- Eleventh aspect a method of manufacturing a flexible semiconductor device having flexibility, Preparing a metal foil; Forming an insulating film on the metal foil; Forming a semiconductor layer on the insulating film; Forming an extraction electrode pattern on the metal foil so as to be in contact with the semiconductor layer; Forming a sealing resin layer on the metal foil so as to cover the semiconductor layer and the extraction electrode pattern; Forming a source electrode and a drain electrode by etching the metal foil; Forming a gate electrode on a surface of the sealing resin layer opposite to a surface on which the source electrode and the drain electrode are formed.
- Twelfth aspect A method of manufacturing a flexible semiconductor device having flexibility, Preparing a metal foil having one surface coated with an insulating film; Forming a semiconductor layer on the insulating film; Removing a portion of the insulating film to form an opening exposing the metal foil located under the insulating film; Forming an extraction electrode pattern in contact with the semiconductor layer on the metal foil exposed in the opening; Forming a sealing resin layer on the metal foil so as to cover the extraction electrode pattern and the semiconductor layer; Forming a source electrode and a drain electrode by etching the metal foil; Forming a gate electrode on a surface of the sealing resin layer opposite to a surface on which the source electrode and the drain electrode are formed.
- the formation of the gate electrode comprises: Forming a further metal foil on the surface of the sealing resin layer opposite to the surface on which the source and drain electrodes are formed; Forming a gate electrode by etching the further metal foil.
- a method for manufacturing a flexible semiconductor device comprising: Fourteenth aspect : In any one of the tenth to twelfth aspects, the formation of the gate electrode comprises: Preparing a flexible substrate having a wiring layer forming surface on which a wiring layer including the gate electrode is formed; Sealing resin from the opposite surface by overlapping the wiring layer forming surface of the flexible substrate on the surface of the sealing resin layer opposite to the surface on which the source electrode and drain electrode are formed.
- the flexible structure according to any one of the tenth to fourteenth aspects further comprising a step of exposing the extraction electrode pattern from the surface of the sealing resin layer by removing the metal foil.
- a method for manufacturing a semiconductor device further includes a step of forming a protective layer made of an insulating material so as to cover the semiconductor layer.
- a method for manufacturing a semiconductor device includes: Depositing a semiconductor material on the insulating film; And a step of performing a heat treatment on the deposited semiconductor material.
- the heat treatment includes at least one of a thermal annealing step and a laser annealing step, and the deposited semiconductor material is crystallized by the heat treatment.
- a method for manufacturing a flexible semiconductor device Nineteenth aspect: The flexible semiconductor device according to any one of the tenth to eighteenth aspects, wherein the semiconductor layer forming step is performed in a high-temperature process including a step of a process temperature of 400 ° C. or higher. Production method.
- Twenty aspect In any one of the tenth to nineteenth aspects, in the step of etching the metal foil, the metal foil is etched to form the source electrode and the drain electrode and to form an electrode layer of the capacitor. Forming a flexible semiconductor device.
- Twenty-first aspect In the thirteenth aspect, in the step of etching the further metal foil, an electrode layer of a capacitor is formed together with the gate electrode by etching the further metal foil.
- Twenty-second aspect A method for manufacturing a flexible semiconductor device having a first TFT element and a second TFT element, A first metal foil having a semiconductor layer forming surface on which a semiconductor layer constituting the first TFT element is formed; and a semiconductor layer forming surface on which a semiconductor layer constituting the second TFT element is formed.
- Preparing a second metal foil and one sealing resin film By superimposing the semiconductor layer forming surface of the first metal foil on one surface of the sealing resin film, the semiconductor layer constituting the first TFT element is placed on one surface of the sealing resin film. Laminating process of embedding, By superimposing the semiconductor layer forming surface of the second metal foil on the other surface of the encapsulating resin film, the semiconductor layer constituting the second TFT element is made to the other surface of the encapsulating resin film.
- An embedding layering process An etching step of forming a source electrode and a drain electrode constituting the first TFT element and a gate electrode constituting the second TFT element by etching the first metal foil;
- a flexible semiconductor comprising: an etching step of forming a gate electrode constituting the first TFT element and a source electrode and a drain electrode constituting the second TFT element by etching the second metal foil Device manufacturing method.
- Twenty-third aspect The flexible semiconductor according to the twenty-second aspect, wherein the sealing resin film is formed with an interlayer connection member that conducts the first metal foil and the second metal foil. Device manufacturing method.
- Twenty-fourth aspect The method for manufacturing a flexible semiconductor device according to the twenty-second or twenty-third aspect, wherein the etching of the first metal foil and the etching of the second metal foil are performed in the same step.
- Twenty-fifth aspect The flexible semiconductor device according to any one of the twenty-second to twenty-fourth aspects, wherein the lamination of the first metal foil and the lamination of the second metal foil are performed in the same step. Production method.
- Twenty-sixth aspect a flexible semiconductor device having flexibility, A gate insulating film; A source electrode and a drain electrode formed by etching a metal foil located on the lower surface of the gate insulating film; A semiconductor layer formed on an upper surface of the gate insulating film; An extraction electrode pattern for electrically connecting each of the source electrode and the drain electrode and the semiconductor layer; A sealing resin layer for sealing the extraction electrode pattern and the semiconductor layer; A flexible semiconductor device comprising: a gate electrode formed on a lower surface of the gate insulating film and formed by etching the metal foil.
- Twenty-seventh aspect The flexible semiconductor device according to the twenty-sixth aspect, wherein the lower surface of the gate electrode and the lower surfaces of the source electrode and the drain electrode are respectively located on the same plane.
- a capacitor is further provided, and the lower surface of the dielectric layer of the capacitor and the lower surface of the gate insulating film are located on the same plane.
- a flexible semiconductor device The flexible semiconductor device according to the twenty-eighth aspect, wherein the lower electrode layer of the capacitor is formed by etching the metal foil.
- the flexible semiconductor device includes the semiconductor layer, the gate insulating film, the gate electrode, the source electrode, and the drain electrode. A flexible semiconductor device having at least two TFT elements.
- a gate electrode, a source electrode and a drain electrode constituting the first TFT element, and a gate electrode constituting the second TFT element A flexible semiconductor device, wherein a source electrode and a drain electrode are formed on the same surface of the sealing resin layer.
- the first TFT element and the second TFT element are electrically connected via a wiring formed by etching the metal foil.
- a flexible semiconductor device In the thirty-third aspect, a gate electrode, a source electrode, and a drain electrode constituting the first TFT element among the at least two TFT elements are formed on one surface of the sealing resin layer.
- a gate electrode, a source electrode, and a drain electrode constituting the second TFT element are formed on the other surface of the sealing resin layer.
- the first TFT element and the second TFT element are electrically connected via an interlayer connection member that conducts the front and back of the sealing resin layer.
- a flexible semiconductor device is composed of a film-shaped core material and resin layers laminated on both surfaces of the core material, respectively. Flexible semiconductor device.
- the gate electrode, the source electrode, and the drain electrode constituting the first TFT element are any one of the surfaces of the sealing resin layer.
- the sealing resin layer has a laminated structure in which a first sealing resin layer and a second sealing resin layer are laminated.
- the gate electrode, the source electrode, and the drain electrode constituting the first TFT element are formed on an outer surface in the stacking direction of the first sealing resin layer, and constitute the second TFT element.
- the gate electrode, the source electrode, and the drain electrode are disposed on the inner surface in the stacking direction of the second sealing resin layer (that is, with respect to the interface between the first sealing resin layer and the second sealing resin layer).
- the flexible semiconductor device is formed so as to be flush with each other.
- a flexible semiconductor device characterized in that it is connected to Thirty-ninth aspect : a method of manufacturing a flexible semiconductor device having flexibility, Preparing a metal foil (a); Forming a gate insulating film on the metal foil (b); Forming a semiconductor layer on the gate insulating film (c); A step (d) of forming a sealing resin layer on the metal foil so as to cover the semiconductor layer; And (e) forming a gate electrode, a source electrode and a drain electrode by etching the metal foil.
- the step (c) includes a step of depositing a semiconductor material on the gate insulating film and a step of performing a heat treatment on the deposited semiconductor material.
- the heat treatment includes at least one of a thermal annealing step and a laser annealing step, and the deposited semiconductor material is crystallized by the heat treatment.
- the steps (b) to (c) are performed in a high-temperature process including a step at a process temperature of 400 ° C.
- Forty-third aspect In any one of the thirty-ninth to forty-second aspects, after the step (c), at least two extraction electrode patterns are formed on the metal foil so as to be in contact with the semiconductor layer.
- a method for manufacturing a flexible semiconductor device comprising: Forty-fourth aspect : In any one of the thirty-nine to forty-second aspects, after the step (b), the method includes the step of forming at least two extraction electrode patterns on the metal foil, the step (c) Then, the said semiconductor layer is formed so that it may contact with the formed said extraction electrode pattern, The manufacturing method of the flexible semiconductor device characterized by the above-mentioned. Forty-fifth aspect : In the forty-third or forty-fourth aspect, in the step (e), the source electrode and the drain electrode are formed so as to be connected to the formed at least two extraction electrode patterns, respectively. A method for manufacturing a flexible semiconductor device.
- a dielectric layer of a capacitor is formed on the metal foil together with the gate insulating film.
- a method for manufacturing a semiconductor device in any one of the thirty-nine to forty-fifth aspects, in the step (e), the metal foil is etched to form the gate electrode, the source electrode and the drain electrode, and to form a lower electrode of the capacitor.
- a method of manufacturing a flexible semiconductor device having flexibility Preparing a metal foil having one surface coated with an insulating film; Forming a semiconductor layer on the insulating film; Removing a portion of the insulating film to form an opening exposing the metal foil located under the insulating film; Forming an extraction electrode pattern in contact with the semiconductor layer on the metal foil exposed in the opening; Forming a sealing resin layer on the metal foil so as to cover the extraction electrode pattern and the semiconductor layer; Forming a gate electrode, a source electrode, and a drain electrode by etching the metal foil.
- the formation of the semiconductor layer includes a step of depositing a semiconductor material on an upper surface of the insulating film, and a step of performing a heat treatment on the deposited semiconductor material.
- the heat treatment includes at least one of a thermal annealing step and a laser annealing step, and the deposited semiconductor material is crystallized by the heat treatment.
- Fifty-first aspect The flexible semiconductor device according to any one of the forty-eighth to fifty aspects, wherein the semiconductor layer forming step is performed by a high-temperature process including a step of a process temperature of 400 ° C. or higher.
- Manufacturing method. 52nd aspect A method for manufacturing a flexible semiconductor device having a first TFT element and a second TFT element, A first metal foil having a semiconductor layer forming surface on which a semiconductor layer constituting the first TFT element is formed; and a semiconductor layer forming surface on which a semiconductor layer constituting the second TFT element is formed.
- Preparing a second metal foil and one sealing resin film By superimposing the semiconductor layer forming surface of the first metal foil on one surface of the sealing resin film, the semiconductor layer constituting the first TFT element is placed on one surface of the sealing resin film. Laminating process of embedding, By superimposing the semiconductor layer forming surface of the second metal foil on the other surface of the encapsulating resin film, the semiconductor layer constituting the second TFT element is made to the other surface of the encapsulating resin film.
- An embedding layering process An etching step of forming a gate electrode, a source electrode, and a drain electrode constituting the first TFT element by etching the first metal foil;
- a method of manufacturing a flexible semiconductor device comprising: an etching step of forming a gate electrode, a source electrode, and a drain electrode constituting the second TFT element by etching the second metal foil.
- the said sealing resin film is comprised from the film-form core material and the resin layer each laminated
- 54th aspect Production of a flexible semiconductor device according to the above 52nd or 53rd aspect, wherein the sealing resin film is formed with an interlayer connection member for conducting the front and back of the sealing resin film.
- Method. 55th aspect The flexible semiconductor device according to any one of the above 52nd to 54th aspects, wherein the etching of the first metal foil and the etching of the second metal foil are performed in the same step.
- Production method. 56th aspect The flexible semiconductor device according to any one of the above 52nd to 55th aspects, wherein the lamination of the first metal foil and the lamination of the second metal foil are performed in the same step. Production method.
- the first metal foil and the second metal foil having the semiconductor layer forming surface are the steps of (a) to (c) of the thirty-ninth aspect
- a 58th aspect a method of manufacturing a flexible semiconductor device having a first TFT element and a second TFT element, A first sealing resin film, a second sealing resin film having an electrode forming surface on which a gate electrode, a source electrode and a drain electrode constituting the second TFT element are formed; and the first TFT Preparing a metal foil having a semiconductor layer forming surface on which a semiconductor layer constituting the element is formed; By superimposing the semiconductor layer forming surface of the metal foil on one surface of the first sealing resin film, the semiconductor layer constituting the first TFT element is placed on one side of the first sealing resin film.
- a laminating process for embedding the surface of By overlapping the electrode forming surface of the second sealing resin film with the other surface of the first sealing resin film, the gate electrode, the source electrode, and the drain electrode constituting the second TFT element are formed.
- 59th aspect The flexible semiconductor device according to the 58th aspect, wherein an interlayer connection member is formed on the first sealing resin film to conduct the front and back of the resin film in the vertical direction. Production method.
- 60th aspect In the above 59th aspect, in the step of laminating the second sealing resin film, any one of the gate electrode, the source electrode and the drain electrode formed on the electrode forming surface, A flexible semiconductor device characterized by being stacked so as to be connected to the interlayer connection member.
- Sixty-first aspect The flexible semiconductor device according to any one of the above-described 58th to 60th aspects, wherein the lamination of the metal foil and the lamination of the second sealing resin film are performed in the same step. Manufacturing method.
- Sixty-second aspect In any one of the fifty-eighth to sixty-first aspects, the metal foil having the semiconductor layer forming surface is produced through the steps (a) to (c) of the thirty-ninth aspect.
- a method for manufacturing a flexible semiconductor device In any one of the above 58th to 62nd aspects, the second sealing resin film having the electrode forming surface is produced through the steps (a) to (e) of the 39th aspect. A method for manufacturing a flexible semiconductor device.
- the method for manufacturing a flexible semiconductor device of the present invention is excellent in productivity of the flexible semiconductor device.
- the obtained flexible semiconductor device can be used for various image display units, and can also be used for electronic paper, digital paper, and the like.
- it can be used in an image display unit of a digital still camera and a camcorder, an image display unit of electronic paper as shown in FIG.
- the flexible semiconductor device according to the present invention can be applied to various uses (for example, RF-ID, memory, MPU, solar cell, sensor, etc.) that are currently being studied for use in printed electronics.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Semiconductor Integrated Circuits (AREA)
- Electrodes Of Semiconductors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Electroluminescent Light Sources (AREA)
Abstract
Description
フレキシブル半導体装置を製造するための方法であって、
(i)金属箔の上面に絶縁膜を形成する工程、
(ii)金属箔の上面に取出し電極パターンを形成する工程、
(iii)取出し電極パターンと接するように、絶縁膜の上に半導体層を形成する工程、
(iv)半導体層および取出し電極パターンを覆うように、金属箔の上面に封止樹脂層を形成する工程、ならびに
(v)金属箔をエッチングすることによって電極を形成する工程
を含んで成り、
金属箔を、工程(i)~(iv)にて形成される絶縁膜、取出し電極パターン、半導体層および封止樹脂層のための支持体として用いると共に、工程(v)にて電極の構成材料として用いることを特徴とする製造方法が提供される。
(ii)’ 絶縁膜の上に半導体層を形成する工程、および
(iii)’ 半導体層と接触するように、金属箔の上面に取出し電極パターンを形成する工程
を順次実施してもよい。
(a)第1のTFT素子を構成する絶縁膜および半導体層が設けられているTFT素子形成面を備えた第1金属箔と、第2のTFT素子を構成する絶縁膜および半導体層が設けられているTFT素子形成面を備えた第2金属箔と、1つの封止樹脂フィルムとを用意する工程、
(b)第1金属箔のTFT素子形成面を、封止樹脂フィルムの一方の面に重ね合わせることにより、第1のTFT素子を構成する絶縁膜および半導体層を封止樹脂フィルムに対して一方の面から埋め込む工程と、
(c)第2金属箔のTFT素子形成面を封止樹脂フィルムの他方の面に重ね合わせることにより、第2のTFT素子を構成する絶縁膜および半導体層を封止樹脂フィルムに対して他方の面から埋め込む工程、ならびに
(d)第1金属箔および第2金属箔をエッチングすることにより、第1のTFT素子の電極および第2のTFT素子の電極を形成する工程
を含んで成り、
第1金属箔を工程(a)~(c)にて「第1のTFT素子を構成する絶縁膜および半導体層の支持体」として用いると共に、工程(d)にて第1のTFT素子の電極構成材料として用い、また、第2金属箔を工程(a)~(c)にて「第2のTFT素子を構成する絶縁膜および半導体層の支持体」として用いると共に、工程(d)にて第2のTFT素子の電極構成材料として用いることを特徴としている。
絶縁膜、
絶縁膜の上面に形成された半導体層、
絶縁膜の下面側に位置する電極、
電極と半導体層とを電気的に接続する取出し電極パターン、ならびに
取出し電極パターンおよび半導体層を封止する封止樹脂層
を有して成り、
電極が、絶縁膜、半導体層、取出し電極パターンおよび封止樹脂層の支持体として機能していた金属箔をエッチングすることによって形成されたものであることを特徴としている。
まず、図1および図2を参照して、本発明の製造方法で得られる典型的なフレキシブル半導体装置について説明する。図1は、ソース電極50sとドレイン電極50dとゲート電極50gとが同一平面上に形成されたフレキシブル半導体装置100Aを示しており、図2は、ゲート電極50gがソース電極50sとドレイン電極50dとは非同一平面に形成されたフレキシブル半導体装置100Bを示している。
次に、図面を参照して、本発明のフレキシブル半導体装置の製造方法について説明する。また、かかる製造方法の説明に付随させる形でフレキシブル半導体装置についても説明を行う。
実施形態1として、図4(a)~(e)を参照してフレキシブル半導体装置100Aの製造方法を説明する。本発明の製造方法を実施するに際しては、まず、工程(i)を実施する。つまり、図4(a)に示すように、金属箔50の上面54に絶縁膜10を形成する。用いられる金属箔50は、上述したように、製造過程において絶縁膜、取出し電極パターン、半導体層および/または封止樹脂層のための支持体として機能すると共に、最終的には、TFT素子の各種電極の構成材料としても機能するものである。かかる観点から、金属箔50を構成する金属は、導電性を有し且つ融点が比較的高い金属が好ましく、例えば、銅(Cu、融点:1083℃)、ニッケル(Ni、融点:1453℃)、アルミニウム(Al、融点:660℃)、ステンレス(SUS)を挙げることができる。金属箔50の厚さは、好ましくは約4μm~約20μmの範囲、より好ましくは約8μm~約16μmの範囲であり、例えば12μm程度である。
以下、本発明の製造方法の他の実施形態およびそれによって得られるフレキシブル半導体装置について説明する。なお、フレキシブル半導体装置100Aと同一の構成部材には同一の符号を付すと共に、フレキシブル半導体装置100Aの製造方法と重複する部分については説明を省略ないしは簡略化する。
図4および図5に例示した態様では、半導体層20を、取出し電極パターン30s、30dの上方から形成し、半導体層20の周縁部の一部が取出し電極パターン30s、30dの延在部32s、32dを覆うようになっているものの、その形態・形成順序は逆でもよい。例えば、図7(a)および(b)に示すように、取出し電極パターン30s、30dが半導体層20の上から形成されているものであってもよい。より具体的には、図7(a)および(b)に示すフレキシブル半導体装置100Cでは、その取出し電極パターン30s、30dの延在部32s、32dが半導体層20の一部を覆うように配置されている。換言すれば、絶縁膜10上に設けられた半導体層20は、その周縁部の上面が、ソース電極用およびドレイン電極用の取出し電極パターン30s,30dの周縁部の下面と部分的に接している。尚、図7(a)および(b)に示すフレキシブル半導体装置100Cは、ソース電極50sとドレイン電極50dとゲート電極50gとが同一平面上に形成されている半導体装置である。
実施形態3と同様に、図9(a)および(b)に示すレキシブル半導体装置100Dでは、取出し電極パターン30s、30dが半導体層20の上から形成されている。つまり、取出し電極パターン30s、30dの延在部32s、32dで半導体層20の一部を覆うように配置されている。実施形態3のフレキシブル半導体装置100Cと異なる点は、図9(a)および(b)に示すフレキシブル半導体装置100Dでは、ゲート電極50gがソース電極50sとドレイン電極50dに対して“非同一平面”に形成されていることである。
例えば図1および図7に示すフレキシブル半導体装置100Aおよび100Cでは、ゲート絶縁膜10を構成している絶縁膜は、半導体層20の下面領域だけに設けられているが、これに限定されない。例えば、図12に示すフレキシブル半導体装置100Eにおける場合のように、半導体層20の下面以外の領域にも絶縁膜(即ち、絶縁膜12)を設けてもよい。
実施形態5と同様に、図14に示すフレキシブル半導体装置100Fでも、絶縁膜を半導体層20の下面以外の領域に形成している。実施形態5のフレキシブル半導体装置100Eと異なる点は、図14に示すフレキシブル半導体装置100Fでは、ゲート電極50gがソース電極50sとドレイン電極50dに対して“非同一平面”に形成されていることである。
次に、図16(a)および(b)を参照しながら、画像表示装置に好ましく搭載され得るフレキシブル半導体装置100Gの態様の一例について説明する。図16(a)はフレキシブル半導体装置100Gの上面図であり、図16(b)は図16(a)のIXb-IXb断面を示す断面図である。
画像表示装置に好ましく搭載され得るフレキシブル半導体装置の態様としては、図17に示すようなフレキシブル半導体装置100Hであってもよい。図17(a)~(c)を参照しながら、フレキシブル半導体装置100Hの態様について説明する。図17(a)はフレキシブル半導体装置100Hの上面図であり、図17(b)は図17(a)のXVb-XVb断面を示す断面図であり、図17(c)は図17(a)のXVc-XVc断面を示す断面図である。
次に、図19(a)および(b)を参照しながら、画像表示装置に搭載するフレキシブル半導体装置の他の実施形態について説明する。図19(a)は、フレキシブル半導体装置100Iの上面図、(b)は(a)のXVIIb-XVIIb断面を示す断面図である。
次に、図21(a)~(c)を参照してフレキシブル半導体装置100Jを説明する。図21(a)は、フレキシブル半導体装置100Jの上面図、(b)は(a)のXb-Xb断面を示す断面図、(c)は(a)のXc-Xc断面を示す断面図である。
次に、図24に示すフレキシブル半導体装置100Kについて説明する。図24に示したフレキシブル半導体装置100Kの封止樹脂層40は、第1の封止樹脂層40Aと第2の封止樹脂層40Bとが積層されて成る積層構造を有している。図示する態様では、第1の封止樹脂40Aが封止樹脂層40の下層を構成し、第2の封止樹脂40Bが封止樹脂層40の上層を構成している。
次に、図26に示すフレキシブル半導体装置100Lについて説明する。
本発明の各種フレキシブル半導体装置が適用される画像表示装置を例を挙げて説明する。図28は、画像表示装置1000の全体の外観を示す外観斜視図である。
図29(a)および(b)のフレキシブル半導体装置100M,100M’で示されるように、ソース用取出し電極30sと、ドレイン用取出し電極30dとの対向する部位の形状が櫛歯形状となっていてよい。このように、ソース用取出し電極30sとドレイン用取出し電極30dとの対向する部位の形状を櫛歯形状とすることで、所定寸法を維持しつつチャネル幅を大きくすることができる。その結果、チャネル幅の増大による高速動作を得ることができる。なお、櫛歯形状の長さ(ソース用取出し電極30sとドレイン用取出し電極30dとの対向する部位の長さ)は、必要とされるTFT性能に応じて適宜決定され得る。例えば、有機ELディスプレイ用のTFTアレイを形成する場合では、駆動用TFT素子の櫛歯形状の長さをスイッチ用TFT素子の櫛歯形状の長さよりも長くしてもよい。
図30(a)および(b)のフレキシブル半導体装置100N,100N’で示されるように、ソース電極50sからストレートに延びた2つのソース用取出し電極30sと、ドレイン電極50dからストレートに延びた3つのドレイン用取出し電極30dとを、交互に並列に配置したような態様であってもよい。このような形状であっても、取出し電極30s、30dが“櫛歯形状”を構成しており、チャネル幅を大きくすることができる。
図31のフレキシブル半導体装置100Oに示すように、半導体層20の上に保護層(更なる保護層)16を形成してもよい。保護層16を構成する絶縁材料は、半導体層20の下面を保護する絶縁膜10の絶縁材料と同じ材料であってもよいし、あるいは異なる材料であってもよい。このように、半導体層20の両面を2つの保護層(絶縁膜10および保護層16)で覆う態様を採用することにより、封止樹脂層40から半導体層20をさらに隔離することができる。その結果、封止樹脂層40内からの水蒸気や酸素、残留イオン等に起因する半導体層20の劣化を防止することができる。これにより、例えば基材として不純物イオンの含有量が高い安価な封止樹脂を用いることができ、製造コストの低減を図ることができる。
図32のフレキシブル半導体装置100Pにおいて示されるように、ダブルゲート構造を採用してもよい。すなわち、半導体層20の上のゲート電極50gに加えて、半導体層20の下に絶縁膜10を介して更なるゲート電極54gを形成してもよい。更なるゲート電極54gは、ソース電極50sおよびドレイン電極50dと同様に、金属箔50のエッチングにより形成することができる。
図33のフレキシブル半導体装置100Qで示されるように、ソース電極50sおよびドレイン電極50dがない構造も考えられる。すなわち、製造時において金属箔50(ソース電極50sおよびドレイン電極50d)を除去することによって、ソース用取出し電極パターン30sおよびドレイン用取出し電極パターン30dを封止樹脂層40の表面(図では下面)から露出させてもよい。かかる構造を採用すると、ソース電極50sおよびドレイン電極50dの厚さ分だけ装置全体の厚みを薄くすることができる。なお、金属箔50の除去(ソース電極50sおよびドレイン電極50d)は、エッチング処理により行ってよい。
図35で示すフレキシブル半導体装置100Sの場合では、フレキシブル基板40Bの下面41Bだけでなく、その上面43Bにも配線層を形成してよい。この場合、上面43Aおよび下面41Bの各配線層は、フレキシブル基板40Bの両面を導通する層間接続部材62を介して電気的に接続すればよい。このような構成にすると、フレキシブル基板40Bの上面43Bの配線層を介して、再配線や電極の引き出しを行うことができ、利便性が高い。
第1の態様:可撓性を有するフレキシブル半導体装置であって、
絶縁膜と、
前記絶縁膜の下面に位置する金属箔をエッチングすることによって形成されたソース電極およびドレイン電極と、
前記絶縁膜の上面の一部に形成された半導体層と、
前記ソース電極および前記ドレイン電極のそれぞれと、前記半導体層とを電気的に接続する取出し電極パターンと、
前記取出し電極パターンおよび前記半導体層を封止する封止樹脂層と、
前記封止樹脂層の面のうち、前記ソース電極および前記ドレイン電極が形成された面とは反対側の面に形成されたゲート電極と
を備えた、フレキシブル半導体装置。
第2の態様:上記第1の態様において、前記封止樹脂層の面のうち、前記半導体層と前記ゲート電極との間で挟まれた部位がゲート絶縁膜として機能することを特徴とするフレキシブル半導体装置。
第3の態様:上記第1または第2の態様において、前記半導体層の上には、該半導体層を被覆する絶縁材料からなる保護層が形成されていることを特徴とするフレキシブル半導体装置。
第4の態様:上記第1~3の態様のいずれかにおいて、コンデンサを更に備えており、該コンデンサの電極層が前記金属箔をエッチングすることによって形成されていることを特徴とするフレキシブル半導体装置。
第5の態様:上記第1~4の態様のいずれかにおいて、前記半導体層と、前記絶縁膜と、前記ゲート電極と、前記ソース電極と、前記ドレイン電極とから構成されたTFT素子を少なくとも2つ有して成ることを特徴とするフレキシブル半導体装置。
第6の態様:上記第5の態様において、前記少なくとも2つのTFT素子のうち、第1のTFT素子を構成するソース電極およびドレイン電極と、第2のTFT素子を構成するソース電極およびドレイン電極とが前記封止樹脂層の一方の面に形成されていると共に、前記第1のTFT素子を構成するゲート電極と前記第2のTFT素子を構成するゲート電極とが前記封止樹脂層の他方の面に形成されていることを特徴とするフレキシブル半導体装置。
第7の態様:上記第6の態様において、前記第1のTFT素子と、前記第2のTFT素子とは、前記封止樹脂層の表面と裏面とを導通する層間接続部材を介して電気的に接続されていることを特徴とするフレキシブル半導体装置。
第8の態様:上記第5の態様において、前記少なくとも2つのTFT素子のうち、第1のTFT素子を構成するゲート電極と第2のTFT素子を構成するソース電極およびドレイン電極とが前記封止樹脂層の一方の面に形成されていると共に、前記第1のTFT素子を構成するソース電極およびドレイン電極と前記第2のTFT素子を構成するゲート電極とが前記封止樹脂層の他方の面に形成されていることを特徴とするフレキシブル半導体装置。
第9の態様:上記第8の態様において、前記第1のTFT素子と前記第2のTFT素子とが前記金属箔をエッチングすることによって形成された配線を介して電気的に接続されていることを特徴とするフレキシブル半導体装置。
第10の態様:可撓性を有するフレキシブル半導体装置の製造方法であって、
金属箔を用意する工程と、
前記金属箔の上に絶縁膜を形成する工程と、
前記金属箔の上に取出し電極パターンを形成する工程と、
前記取出し電極パターンと接触するように、前記絶縁膜の上に半導体層を形成する工程と、
前記半導体層および前記取出し電極パターンを覆うように、前記金属箔の上に封止樹脂層を形成する工程と、
前記金属箔をエッチングすることによって、ソース電極およびドレイン電極を形成する工程と、
前記封止樹脂層の面うち、前記ソース電極およびドレイン電極が形成された面とは反対側の面にゲート電極を形成する工程と
を含むフレキシブル半導体装置の製造方法。
第11の態様:可撓性を有するフレキシブル半導体装置の製造方法であって、
金属箔を用意する工程と、
前記金属箔の上に絶縁膜を形成する工程と、
前記絶縁膜の上に半導体層を形成する工程と、
前記半導体層と接触するように、前記金属箔の上に取出し電極パターンを形成する工程と、
前記半導体層および前記取出し電極パターンを覆うように、前記金属箔の上に封止樹脂層を形成する工程と、
前記金属箔をエッチングすることによって、ソース電極およびドレイン電極を形成する工程と、
前記封止樹脂層の面のうち、前記ソース電極およびドレイン電極が形成される面とは反対側の面にゲート電極を形成する工程と
を含む、フレキシブル半導体装置の製造方法。
第12の態様:可撓性を有するフレキシブル半導体装置の製造方法であって、
一方の面が絶縁膜で被覆された金属箔を用意する工程と、
前記絶縁膜の上に半導体層を形成する工程と、
前記絶縁膜の一部を除去することにより、該絶縁膜の下に位置する金属箔を露出する開口部を形成する工程と、
前記開口部に露出した前記金属箔の上に、前記半導体層と接触する取出し電極パターンを形成する工程と、
前記取出し電極パターンおよび前記半導体層を覆うように、前記金属箔の上に封止樹脂層を形成する工程と、
前記金属箔をエッチングすることによって、ソース電極およびドレイン電極を形成する工程と、
前記封止樹脂層の面のうち、前記ソース電極およびドレイン電極が形成される面とは反対側の面にゲート電極を形成する工程と
を含む、フレキシブル半導体装置の製造方法。
第13の態様:上記第10~12の態様のいずれかにおいて、前記ゲート電極の形成は、
前記封止樹脂層の面のうち、前記ソース電極およびドレイン電極が形成される面とは反対側の面に更なる金属箔を形成する工程と、
前記更なる金属箔をエッチングすることによって、ゲート電極を形成する工程と
を含むことを特徴とするフレキシブル半導体装置の製造方法。
第14の態様:上記第10~12の態様のいずれかにおいて、前記ゲート電極の形成は、
前記ゲート電極を含む配線層が形成された配線層形成面を備えたフレキシブル基板を用意する工程と、
前記フレキシブル基板の配線層形成面を、前記封止樹脂層の面のうち前記ソース電極およびドレイン電極が形成される面とは反対側の面に重ね合わせることにより前記反対側の面から封止樹脂層に埋め込む工程と
を含むことを特徴とするフレキシブル半導体装置の製造方法。
第15の態様:上記第10~14の態様のいずれかにおいて、前記金属箔を除去することによって、前記取出し電極パターンを前記封止樹脂層の表面から露出させる工程を含むことを特徴とするフレキシブル半導体装置の製造方法。
第16の態様:上記第10~15の態様のいずれかにおいて、前記半導体層の形成は、前記半導体層を覆うように絶縁材料からなる保護層を形成する工程を更に含むことを特徴とするフレキシブル半導体装置の製造方法。
第17の態様:上記第10~16の態様のいずれかにおいて、前記半導体層の形成は、
前記絶縁膜の上に半導体材料を堆積する工程と、
前記堆積した半導体材料に加熱処理を実行する工程と
を含むことを特徴とするフレキシブル半導体装置の製造方法。
第18の態様:上記第17の態様において、前記加熱処理は、熱アニール工程およびレーザアニール工程の少なくとも一つを含み、前記加熱処理によって、前記堆積した半導体材料の結晶化が実行されることを特徴とするフレキシブル半導体装置の製造方法。
第19の態様:上記第10~18の態様のいずれかにおいて、前記半導体層の形成工程が、プロセス温度が400℃以上のステップを含む高温プロセスにおいて実行されることを特徴とするフレキシブル半導体装置の製造方法。
第20の態様:上記第10~19の態様のいずれかにおいて、前記金属箔をエッチングする工程では、該金属箔をエッチングすることによって、前記ソース電極および前記ドレイン電極の形成と共に、コンデンサの電極層を形成することを特徴とするフレキシブル半導体装置の製造方法。
第21の態様:上記第13の態様において、前記更なる金属箔をエッチングする工程では、該更なる金属箔をエッチングすることによって、前記ゲート電極と共に、コンデンサの電極層を形成することを特徴とするフレキシブル半導体装置の製造方法。
第22の態様:第1のTFT素子と第2のTFT素子とを有するフレキシブル半導体装置の製造方法であって、
前記第1のTFT素子を構成する半導体層が形成された半導体層形成面を備えた第1金属箔と、前記第2のTFT素子を構成する半導体層が形成された半導体層形成面を備えた第2金属箔と、1つの封止樹脂フィルムとを用意する工程と、
前記第1金属箔の半導体層形成面を、前記封止樹脂フィルムの一方の面に重ね合わせることにより、前記第1のTFT素子を構成する半導体層を前記封止樹脂フィルムの一方の面に対して埋め込む積層工程と、
前記第2金属箔の半導体層形成面を前記封止樹脂フィルムの他方の面に重ね合わせることにより、前記第2のTFT素子を構成する半導体層を前記封止樹脂フィルムの他方の面に対して埋め込む積層工程と、
前記第1金属箔をエッチングすることにより、前記第1のTFT素子を構成するソース電極およびドレイン電極と、前記第2のTFT素子を構成するゲート電極とを形成するエッチング工程と、
前記第2金属箔をエッチングすることにより、前記第1のTFT素子を構成するゲート電極と、前記第2のTFT素子を構成するソース電極およびドレイン電極とを形成するエッチング工程と
を含む、フレキシブル半導体装置の製造方法。
第23の態様:上記第22の態様において、前記封止樹脂フィルムには、前記第1金属箔と前記第2金属箔とを導通する層間接続部材が形成されていることを特徴とするフレキシブル半導体装置の製造方法。
第24の態様:上記第22または23の態様において、前記第1金属箔のエッチングと、前記第2金属箔のエッチングとを同一工程にて実行することを特徴とするフレキシブル半導体装置の製造方法。
第25の態様:上記第22~24の態様のいずれかにおいて、前記第1金属箔の積層と、前記第2金属箔の積層とを同一工程にて実行することを特徴とするフレキシブル半導体装置の製造方法。
第26の態様:可撓性を有するフレキシブル半導体装置であって、
ゲート絶縁膜と、
前記ゲート絶縁膜の下面に位置する金属箔をエッチングすることによって形成されたソース電極およびドレイン電極と、
前記ゲート絶縁膜の上面に形成された半導体層と、
前記ソース電極および前記ドレイン電極のそれぞれと、前記半導体層とを電気的に接続する取出し電極パターンと、
前記取出し電極パターンおよび前記半導体層を封止する封止樹脂層と、
前記ゲート絶縁膜の下面に形成され、かつ、前記金属箔をエッチングすることによって形成されたゲート電極と
を備えた、フレキシブル半導体装置。
第27の態様:上記第26の態様において、前記ゲート電極の下面と、前記ソース電極およびドレイン電極の下面とは、それぞれ、同一平面上に位置していることを特徴とするフレキシブル半導体装置。
第28の態様:第26または27の態様のいずれかにおいて、コンデンサを更に備えており、前記コンデンサの誘電体層の下面と、前記ゲート絶縁膜の下面とが同一平面上に位置していることを特徴とするフレキシブル半導体装置。
第29の態様:上記第28の態様において、前記コンデンサの下部電極層が前記金属箔をエッチングすることによって形成されていることを特徴とするフレキシブル半導体装置。
第30の態様:上記第26~29の態様のいずれかにおいて、前記フレキシブル半導体装置は、前記半導体層と、前記ゲート絶縁膜と、前記ゲート電極と、前記ソース電極と、前記ドレイン電極とから構成されたTFT素子を少なくとも2つ有していることを特徴とするフレキシブル半導体装置。
第31の態様:上記第30の態様において、前記少なくとも2つのTFT素子のうち、第1のTFT素子を構成するゲート電極、ソース電極およびドレイン電極と、第2のTFT素子を構成するゲート電極、ソース電極およびドレイン電極とが、前記封止樹脂層の同一面にて形成されていることを特徴とするフレキシブル半導体装置。
第32の態様:上記第31の態様において、前記第1のTFT素子と、前記第2のTFT素子とは、前記金属箔をエッチングすることによって形成された配線を介して電気的に接続されていることを特徴とするフレキシブル半導体装置。
第33の態様:上記第30の態様において、前記少なくとも2つのTFT素子のうち、第1のTFT素子を構成するゲート電極、ソース電極およびドレイン電極が前記封止樹脂層の一方の面に形成されていると共に、第2のTFT素子を構成するゲート電極、ソース電極およびドレイン電極が前記封止樹脂層の他方の面に形成されていることを特徴とするフレキシブル半導体装置。
第34の態様:上記第33の態様において、前記第1のTFT素子と前記第2のTFT素子とが前記封止樹脂層の表裏を導通する層間接続部材を介して電気的に接続されていることを特徴とするフレキシブル半導体装置。
第35の態様:上記第33または34の態様において、前記封止樹脂層が、フィルム状の芯材と、該芯材の両面にそれぞれ積層された樹脂層とから構成されていることを特徴とするフレキシブル半導体装置。
第36の態様:上記第30の態様において、前記少なくとも2つのTFT素子のうち、第1のTFT素子を構成するゲート電極、ソース電極およびドレイン電極が前記封止樹脂層の面の何れか一方の面に形成されていると共に、第2のTFT素子を構成するゲート電極、ソース電極およびドレイン電極が前記封止樹脂層の内部に設けられていることを特徴とするフレキシブル半導体装置。
第37の態様:上記第36の態様において、前記封止樹脂層は、第1の封止樹脂層と第2の封止樹脂層とが積層されてなる積層構造を有しており、
前記第1のTFT素子を構成する前記ゲート電極、ソース電極およびドレイン電極は、前記第1の封止樹脂層の積層方向の外側の面に形成され、且つ、前記第2のTFT素子を構成する前記ゲート電極、ソース電極およびドレイン電極は、前記第2の封止樹脂層の積層方向の内側の面に(即ち、第1の封止樹脂層と第2の封止樹脂層との界面に対して面一となるように)形成されていることを特徴とするフレキシブル半導体装置。
第38の態様:上記第37の態様において、前記第1のTFT素子と、前記第2のTFT素子とは、前記第1の封止樹脂層の表裏を導通する層間接続部材を介して電気的に接続されていることを特徴とするフレキシブル半導体装置。
第39の態様:可撓性を有するフレキシブル半導体装置の製造方法であって、
金属箔を用意する工程(a)と、
前記金属箔の上にゲート絶縁膜を形成する工程(b)と、
前記ゲート絶縁膜の上に半導体層を形成する工程(c)と、
前記半導体層を覆うように、前記金属箔の上に封止樹脂層を形成する工程(d)と、
前記金属箔をエッチングすることによって、ゲート電極、ソース電極およびドレイン電極を形成する工程(e)と
を含むフレキシブル半導体装置の製造方法。
第40の態様:上記第39の態様において、前記工程(c)は、前記ゲート絶縁膜の上に、半導体材料を堆積する工程と前記堆積した半導体材料に加熱処理を実行する工程とを含むことを特徴とするフレキシブル半導体装置の製造方法。
第41の態様:上記第40の態様において、前記加熱処理は、熱アニール工程およびレーザアニール工程の少なくとも一つを含み、前記加熱処理によって、前記堆積した半導体材料の結晶化が実行されることを特徴とするフレキシブル半導体装置の製造方法。
第42の態様:上記第39~41の態様のいずれかにおいて、前記工程(b)から(c)は、プロセス温度が400℃以上のステップを含む高温プロセスにて実行されることを特徴とするフレキシブル半導体装置の製造方法。
第43の態様:上記第39~42の態様のいずれかにおいて、前記工程(c)の後、前記半導体層と接触するように、前記金属箔の上に少なくとも2つの取出し電極パターンを形成する工程を含むことを特徴とするフレキシブル半導体装置の製造方法。
第44の態様:上記第39~42の態様のいずれかにおいて、前記工程(b)の後、前記金属箔の上に、少なくとも2つの取出し電極パターンを形成する工程を含み、前記工程(c)では、前記形成した取出し電極パターンと接触するように、前記半導体層を形成することを特徴とするフレキシブル半導体装置の製造方法。
第45の態様:第43または44の態様において、前記工程(e)では、前記形成した少なくとも2つの取出し電極パターンとそれぞれ接続するように、前記ソース電極および前記ドレイン電極を形成することを特徴とするフレキシブル半導体装置の製造方法。
第46の態様:上記第39~45の態様のいずれかにおいて、前記工程(b)では、前記金属箔の上に、前記ゲート絶縁膜とともにコンデンサの誘電体層を形成することを特徴とするフレキシブル半導体装置の製造方法。
第47の態様:上記第39~45の態様のいずれかにおいて、前記工程(e)では、前記金属箔をエッチングすることによって、前記ゲート電極、ソース電極およびドレイン電極の形成と共に、コンデンサの下部電極層を形成することを特徴とするフレキシブル半導体装置の製造方法。
第48の態様:可撓性を有するフレキシブル半導体装置の製造方法であって、
一方の面が絶縁膜で被覆された金属箔を用意する工程と、
前記絶縁膜の上に半導体層を形成する工程と、
前記絶縁膜の一部を除去することにより、該絶縁膜の下に位置する金属箔を露出する開口部を形成する工程と、
前記開口部に露出した前記金属箔の上に、前記半導体層と接触する取出し電極パターンを形成する工程と、
前記取出し電極パターンおよび前記半導体層を覆うように、前記金属箔の上に封止樹脂層を形成する工程と、
前記金属箔をエッチングすることによって、ゲート電極、ソース電極およびドレイン電極を形成する工程と
を含む、フレキシブル半導体装置の製造方法。
第49の態様:上記第48の態様において、前記半導体層の形成は、前記絶縁膜の上面に、半導体材料を堆積する工程と、前記堆積した半導体材料に加熱処理を実行する工程とを含むことを特徴とするフレキシブル半導体装置の製造方法。
第50の態様:上記第49の態様において、前記加熱処理は、熱アニール工程およびレーザアニール工程の少なくとも一つを含み、前記加熱処理によって前記堆積した半導体材料の結晶化が実行されることを特徴とするフレキシブル半導体装置の製造方法。
第51の態様:上記第48~50の態様のいずれかにおいて、前記半導体層の形成工程は、プロセス温度が400℃以上のステップを含む高温プロセスにて実行されることを特徴とするフレキシブル半導体装置の製造方法。
第52の態様:第1のTFT素子と第2のTFT素子とを有するフレキシブル半導体装置の製造方法であって、
前記第1のTFT素子を構成する半導体層が形成された半導体層形成面を備えた第1金属箔と、前記第2のTFT素子を構成する半導体層が形成された半導体層形成面を備えた第2金属箔と、1つの封止樹脂フィルムとを用意する工程と、
前記第1金属箔の半導体層形成面を、前記封止樹脂フィルムの一方の面に重ね合わせることにより、前記第1のTFT素子を構成する半導体層を前記封止樹脂フィルムの一方の面に対して埋め込む積層工程と、
前記第2金属箔の半導体層形成面を前記封止樹脂フィルムの他方の面に重ね合わせることにより、前記第2のTFT素子を構成する半導体層を前記封止樹脂フィルムの他方の面に対して埋め込む積層工程と、
前記第1金属箔をエッチングすることにより、前記第1のTFT素子を構成するゲート電極、ソース電極およびドレイン電極を形成するエッチング工程と、
前記第2金属箔をエッチングすることにより、前記第2のTFT素子を構成するゲート電極、ソース電極およびドレイン電極を形成するエッチング工程と
を含む、フレキシブル半導体装置の製造方法。
第53の態様:上記第52の態様において、前記封止樹脂フィルムは、フィルム状の芯材と、該芯材の両面にそれぞれ積層された樹脂層とから構成されていることを特徴とするフレキシブル半導体装置の製造方法。
第54の態様:上記第52または53の態様において、前記封止樹脂フィルムには、該封止樹脂フィルムの表裏を導通する層間接続部材が形成されていることを特徴とするフレキシブル半導体装置の製造方法。
第55の態様:上記第52~54の態様のいずれかにおいて、前記第1金属箔のエッチングと、前記第2金属箔のエッチングとを同一工程にて実行することを特徴とするフレキシブル半導体装置の製造方法。
第56の態様:上記第52~55の態様のいずれかにおいて、前記第1金属箔の積層と、前記第2金属箔の積層とを同一工程にて実行することを特徴とするフレキシブル半導体装置の製造方法。
第57の態様:上記第52~56の態様のいずれかにおいて、前記半導体層形成面を有する第1金属箔および第2金属箔は、上記第39の態様の(a)~(c)の工程を経て作製されることを特徴とするフレキシブル半導体装置の製造方法。
第58の態様:第1のTFT素子と第2のTFT素子とを有するフレキシブル半導体装置の製造方法であって、
第1の封止樹脂フィルムと、前記第2のTFT素子を構成するゲート電極、ソース電極およびドレイン電極が形成された電極形成面を備えた第2の封止樹脂フィルムと、前記第1のTFT素子を構成する半導体層が形成された半導体層形成面を備えた金属箔とを用意する工程と、
前記金属箔の半導体層形成面を、前記第1の封止樹脂フィルムの一方の面に重ね合わせることにより、前記第1のTFT素子を構成する半導体層を前記第1の封止樹脂フィルムの一方の面に対して埋め込む積層工程と、
前記第2の封止樹脂フィルムの電極形成面を、前記第1の封止樹脂フィルムの他方の面に重ね合わせることにより、前記第2のTFT素子を構成するゲート電極、ソース電極およびドレイン電極を前記第1の封止樹脂フィルムの他方の面に対して埋め込む積層工程と、
前記金属箔をエッチングすることによって、前記第1のTFT素子を構成するゲート電極、ソース電極およびドレイン電極を形成するエッチング工程と
を含む、フレキシブル半導体装置の製造方法。
第59の態様:上記第58の態様において、前記第1封止樹脂フィルムには、該樹脂フィルムの表裏を上下方向に導通する層間接続部材が形成されていることを特徴とするフレキシブル半導体装置の製造方法。
第60の態様:上記第59の態様において、前記第2の封止樹脂フィルムの積層工程において、前記電極形成面に形成されたゲート電極、ソース電極およびドレイン電極のうちの何れかの電極を、前記層間接続部材に接続するように重ね合わせることを特徴とするフレキシブル半導体装置。
第61の態様:上記第58~60の態様のいずれかにおいて、前記金属箔の積層と、前記第2の封止樹脂フィルムの積層とを同一工程にて実行することを特徴とするフレキシブル半導体装置の製造方法。
第62の態様:上記第58~61の態様のいずれかにおいて、前記半導体層形成面を有する金属箔は、上記第39の態様の(a)~(c)の工程を経て作製されることを特徴とするフレキシブル半導体装置の製造方法。
第63の態様:上記第58~62の態様のいずれかにおいて、前記電極形成面を有する第2の封止樹脂フィルムは、上記第39の態様の(a)~(e)の工程を経て作製されることを特徴とするフレキシブル半導体装置の製造方法。
15 開口部
16 保護層,絶縁膜
17 開口部
20 半導体層
30d ドレイン用取出し電極パターン
30s ソース用取出し電極パターン
32s 延在部
32d 延在部
40 封止樹脂層・封止樹脂
41A 外側の面(第1の封止樹脂)
41B 内側の面(第2の封止樹脂)
42 ゲート絶縁膜(封止樹脂の一部)、芯材
43A 内側の面(第1の封止樹脂)
50 金属箔
50A 第1金属箔
50B 第2金属箔
50d ドレイン電極
50g ゲート電極
50s ソース電極
52 更なる金属箔
54 上面(金属箔)
54A 半導体層形成面
54B 半導体層形成面
54g ゲート電極
60,62 層間接続部材
65 貫通孔
70 積層方向
80 コンデンサ
82 誘電体層
84 上部電極層
85 調整用電極
86 下部電極層
88 配線
90 等価回路
92 配線
94 配線
100 フレキシブル半導体装置
100A フレキシブル半導体装置
100B フレキシブル半導体装置
100C フレキシブル半導体装置
100D フレキシブル半導体装置
100E フレキシブル半導体装置
100F フレキシブル半導体装置
100G フレキシブル半導体装置
100H フレキシブル半導体装置
100I フレキシブル半導体装置
100J フレキシブル半導体装置
100K フレキシブル半導体装置
100L フレキシブル半導体装置
100M,M’ フレキシブル半導体装置
100N,N’ フレキシブル半導体装置
100P フレキシブル半導体装置
100Q フレキシブル半導体装置
100R フレキシブル半導体装置
100S フレキシブル半導体装置
600 フレキシブル半導体装置
Claims (20)
- フレキシブル半導体装置を製造するための方法であって、
(i)金属箔の上面に絶縁膜を形成する工程、
(ii)前記金属箔の上面に取出し電極パターンを形成する工程、
(iii)前記取出し電極パターンと接するように、前記絶縁膜の上に半導体層を形成する工程、
(iv)前記半導体層および前記取出し電極パターンを覆うように、前記金属箔の上面に封止樹脂層を形成する工程、ならびに
(v)前記金属箔をエッチングすることによって電極を形成する工程
を含んで成り、
前記金属箔を、前記工程(i)~(iv)にて形成される前記絶縁膜、前記取出し電極パターン、前記半導体層および前記封止樹脂層のための支持体として用いると共に、前記工程(v)にて前記電極の構成材料として用いることを特徴とする、フレキシブル半導体装置の製造方法。 - 前記工程(iii)で形成された前記半導体層に対して加熱処理を施すことを特徴とする、請求項1に記載のフレキシブル半導体装置の製造方法。
- 前記加熱処理として、熱アニール処理および/またはレーザアニール処理を行うことを特徴とする、請求項2に記載のフレキシブル半導体装置の製造方法。
- 前記工程(iii)の半導体層の形成工程を400℃~1000℃の高温プロセスで実施することを特徴とする、請求項1に記載のフレキシブル半導体装置の製造方法。
- 前記工程(v)では、前記金属箔のエッチングによってソース電極およびドレイン電極を形成することを特徴とする、請求項1に記載のフレキシブル半導体装置の製造方法。
- 前記工程(v)では前記金属箔のエッチングによってゲート電極も形成し、それによって、前記ソース電極と前記ドレイン電極と前記ゲート電極とを同一平面上に形成することを特徴とする、請求項5に記載のフレキシブル半導体装置の製造方法。
- (vi)前記ソース電極および前記ドレイン電極とは非同一平面に位置するようにゲート電極を形成する工程を更に含んで成り、
前記工程(vi)においては、前記封止樹脂層の上面に更なる金属箔を供して該更なる金属箔をエッチングすることによって前記ゲート電極を形成することを特徴とする、請求項5に記載のフレキシブル半導体装置の製造方法。 - 前記金属箔をエッチングすることによってコンデンサの電極層も更に形成することを特徴とする、請求項1に記載のフレキシブル半導体装置の製造方法。
- 前記工程(ii)および前記工程(iii)に代えて、
(ii)’ 前記絶縁膜の上に半導体層を形成する工程、および
(iii)’ 前記半導体層と接触するように、前記金属箔の上面に取出し電極パターンを形成する工程
を実施することを特徴とする、請求項1に記載のフレキシブル半導体装置の製造方法。 - 絶縁膜と半導体層とゲート電極とソース電極とドレイン電極とを有して成るTFT素子を少なくとも2つ有して成るフレキシブル半導体装置の製造方法であって、
(a)第1のTFT素子を構成する絶縁膜および半導体層が設けられているTFT素子形成面を備えた第1金属箔と、第2のTFT素子を構成する絶縁膜および半導体層が設けられているTFT素子形成面を備えた第2金属箔と、1つの封止樹脂フィルムとを用意する工程、
(b)前記第1金属箔のTFT素子形成面を、前記封止樹脂フィルムの一方の面に重ね合わせることにより、前記第1のTFT素子を構成する前記絶縁膜および前記半導体層を前記封止樹脂フィルムに前記一方の面から埋め込む工程と、
(c)前記第2金属箔のTFT素子形成面を前記封止樹脂フィルムの他方の面に重ね合わせることにより、前記第2のTFT素子を構成する前記絶縁膜および前記半導体層を前記封止樹脂フィルムに前記他方の面から埋め込む工程、ならびに
(d)前記第1金属箔および前記第2金属箔をエッチングすることにより、前記第1のTFT素子の電極および前記第2のTFT素子の電極を形成する工程
を含んで成り、
前記第1金属箔を、前記工程(a)~(c)にて前記第1のTFT素子を構成する前記絶縁膜および前記半導体層の支持体として用いると共に、前記工程(d)にて前記第1のTFT素子の前記電極の構成材料として用い、また
前記第2金属箔を、前記工程(a)~(c)にて前記第2のTFT素子を構成する前記絶縁膜および前記半導体層の支持体として用いると共に、前記工程(d)にて前記第2のTFT素子の前記電極の構成材料として用いることを特徴とする、フレキシブル半導体装置の製造方法。 - 前記工程(d)では、前記第1金属箔をエッチングすることにより前記第1のTFT素子を構成するソース電極およびドレイン電極と前記第2のTFT素子を構成するゲート電極とを形成すると共に、前記第2金属箔をエッチングすることにより前記第1のTFT素子を構成するゲート電極と前記第2のTFT素子を構成するソース電極およびドレイン電極とを形成することを特徴とする、請求項10に記載のフレキシブル半導体装置の製造方法。
- 前記工程(d)では、前記第1金属箔をエッチングすることにより、前記第1のTFT素子を構成するゲート電極、ソース電極およびドレイン電極を形成すると共に、前記第2金属箔をエッチングすることにより前記第2のTFT素子を構成するゲート電極、ソース電極およびドレイン電極を形成することを特徴とする、請求項10に記載のフレキシブル半導体装置の製造方法。
- フレキシブル半導体装置であって、
絶縁膜、
前記絶縁膜の上面に形成された半導体層、
前記絶縁膜の下面側に位置する電極、
前記電極と前記半導体層とを電気的に接続する取出し電極パターン、ならびに
前記取出し電極パターンおよび前記半導体層を封止する封止樹脂層
を有して成り、
前記電極が、前記絶縁膜、前記半導体層、前記取出し電極パターンおよび前記封止樹脂層の支持体として機能していた金属箔をエッチングすることによって形成されたものであることを特徴とする、フレキシブル半導体装置。 - 前記電極がその厚み方向にテーパー形状を有していることを特徴とする、請求項13に記載のフレキシブル半導体装置。
- 前記電極厚さが4μm~約20μmであることを特徴とする、請求項13に記載のフレキシブル半導体装置。
- 前記金属箔をエッチングすることによって形成された電極がソース電極、ドレイン電極およびゲート電極であって、
前記ソース電極と前記ドレイン電極と前記ゲート電極とが同一平面上に位置していることを特徴とする、請求項13に記載のフレキシブル半導体装置。 - 前記金属箔をエッチングすることによって形成された電極がソース電極およびドレイン電極であり、また、
前記封止樹脂層を挟んで前記半導体層と対向するように前記封止樹脂層の上面にゲート電極を有して成り、前記ゲート電極が前記金属箔とは別の金属箔をエッチングすることによって形成されたものであって、前記ソース電極および前記ドレイン電極に対して非同一平面となるように前記ゲート電極が位置していることを特徴とする、請求項13に記載のフレキシブル半導体装置。 - 前記金属箔をエッチングすることによって形成された電極がソース電極およびドレイン電極であり、
前記半導体層の周縁部の下面と、前記ソース電極用および前記ドレイン電極用の前記取出し電極パターンの周縁部の上面とが部分的に相互に接していることを特徴とする、請求項13に記載のフレキシブル半導体装置。 - 前記金属箔をエッチングすることによって形成された電極がソース電極およびドレイン電極であり、
前記半導体層の周縁部の上面と、前記ソース電極用および前記ドレイン電極用の前記取出し電極パターンの周縁部の下面とが部分的に相互に接していることを特徴とする、請求項13に記載のフレキシブル半導体装置。 - 前記電極がゲート電極、ソース電極およびドレイン電極であって、
前記絶縁膜と前記半導体層と前記ゲート電極と前記ソース電極と前記ドレイン電極とを有して成るTFT素子を少なくとも2つ有して成ることを特徴とする、請求項13に記載のフレキシブル半導体装置。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2009801005512A CN102047396B (zh) | 2008-08-04 | 2009-07-30 | 柔性半导体装置及其制造方法 |
US12/681,445 US8343822B2 (en) | 2008-08-04 | 2009-07-30 | Flexible semiconductor device and method for manufacturing same |
EP09804694.9A EP2312620A4 (en) | 2008-08-04 | 2009-07-30 | FLEXIBLE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME |
JP2010523736A JP4659925B2 (ja) | 2008-08-04 | 2009-07-30 | フレキシブル半導体装置およびその製造方法 |
US13/687,105 US8525172B2 (en) | 2008-08-04 | 2012-11-28 | Flexible semiconductor device |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008-200767 | 2008-08-04 | ||
JP2008200767 | 2008-08-04 | ||
JP2008200766 | 2008-08-04 | ||
JP2008-200766 | 2008-08-04 |
Related Child Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/681,445 A-371-Of-International US8343822B2 (en) | 2008-08-04 | 2009-07-30 | Flexible semiconductor device and method for manufacturing same |
US13/687,105 Division US8525172B2 (en) | 2008-08-04 | 2012-11-28 | Flexible semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2010016207A1 true WO2010016207A1 (ja) | 2010-02-11 |
Family
ID=41663436
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2009/003616 WO2010016207A1 (ja) | 2008-08-04 | 2009-07-30 | フレキシブル半導体装置およびその製造方法 |
Country Status (7)
Country | Link |
---|---|
US (2) | US8343822B2 (ja) |
EP (1) | EP2312620A4 (ja) |
JP (2) | JP4659925B2 (ja) |
KR (1) | KR20110050580A (ja) |
CN (1) | CN102047396B (ja) |
TW (1) | TW201017823A (ja) |
WO (1) | WO2010016207A1 (ja) |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2011142081A1 (ja) * | 2010-05-12 | 2011-11-17 | パナソニック株式会社 | フレキシブル半導体装置およびその製造方法 |
WO2011142089A1 (ja) * | 2010-05-14 | 2011-11-17 | パナソニック株式会社 | フレキシブル半導体装置およびその製造方法ならびに画像表示装置 |
JP2015053444A (ja) * | 2013-09-09 | 2015-03-19 | パナソニックIpマネジメント株式会社 | フレキシブル半導体装置およびその製造方法ならびに画像表示装置 |
JP2015055872A (ja) * | 2013-09-11 | 2015-03-23 | 三星ディスプレイ株式會社Samsung Display Co.,Ltd. | 表示パネル及びその製造方法 |
JP2017092485A (ja) * | 2011-11-30 | 2017-05-25 | 株式会社半導体エネルギー研究所 | 半導体装置 |
JP2017168838A (ja) * | 2016-03-10 | 2017-09-21 | 株式会社半導体エネルギー研究所 | トランジスタ、電子機器 |
JP2019208058A (ja) * | 2013-09-05 | 2019-12-05 | 株式会社半導体エネルギー研究所 | 表示装置 |
JP2019216276A (ja) * | 2010-09-03 | 2019-12-19 | 株式会社半導体エネルギー研究所 | 半導体装置 |
JP2021013036A (ja) * | 2011-01-12 | 2021-02-04 | 株式会社半導体エネルギー研究所 | トランジスタ及び半導体装置 |
JP2022167961A (ja) * | 2010-01-22 | 2022-11-04 | 株式会社半導体エネルギー研究所 | 半導体装置 |
Families Citing this family (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101791370B1 (ko) * | 2009-07-10 | 2017-10-27 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치 |
WO2013042562A1 (en) * | 2011-09-22 | 2013-03-28 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
WO2013125421A1 (ja) | 2012-02-21 | 2013-08-29 | 株式会社村田製作所 | 抵抗スイッチングデバイスおよびその製造方法 |
JP5910294B2 (ja) * | 2012-05-10 | 2016-04-27 | 富士通株式会社 | 電子装置及び積層構造体の製造方法 |
KR102119914B1 (ko) * | 2012-05-31 | 2020-06-05 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치 및 그 제작 방법 |
JP6095903B2 (ja) * | 2012-06-15 | 2017-03-15 | 浜松ホトニクス株式会社 | 固体撮像装置の製造方法及び固体撮像装置 |
CN107253394B (zh) * | 2012-08-06 | 2019-05-03 | 株式会社尼康 | 转印装置以及基板处理装置 |
TWI463620B (zh) * | 2012-08-22 | 2014-12-01 | 矽品精密工業股份有限公司 | 封裝基板之製法 |
JP5842262B2 (ja) * | 2012-08-24 | 2016-01-13 | 国立大学法人大阪大学 | 有機薄膜トランジスタ及びその製造方法 |
WO2014035014A1 (ko) * | 2012-08-27 | 2014-03-06 | 한국과학기술원 | 유연 전자소자 및 그 제조방법, 응력 완화에 의한 배터리 용량 증대 방법 및 이에 의하여 증대된 용량을 갖는 유연 배터리 |
KR101922118B1 (ko) * | 2012-08-27 | 2018-11-26 | 삼성전자주식회사 | 플렉서블 반도체소자 및 그 제조방법 |
JP6121149B2 (ja) * | 2012-11-28 | 2017-04-26 | 富士フイルム株式会社 | 酸化物半導体素子、酸化物半導体素子の製造方法、表示装置及びイメージセンサ |
JP6136644B2 (ja) * | 2013-06-28 | 2017-05-31 | 富士電機株式会社 | 半導体圧力センサ装置およびその製造方法 |
KR102059167B1 (ko) * | 2013-07-30 | 2020-02-07 | 엘지디스플레이 주식회사 | 플렉서블 유기전계 발광소자 및 그 제조 방법 |
US9558929B2 (en) | 2013-11-25 | 2017-01-31 | Nutech Ventures | Polymer on graphene |
TWI555150B (zh) | 2014-05-27 | 2016-10-21 | 財團法人工業技術研究院 | 電子元件及其製法 |
US10020403B2 (en) * | 2014-05-27 | 2018-07-10 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
US9391208B2 (en) * | 2014-10-17 | 2016-07-12 | Industrial Technology Research Institute | Electronic device and method of manufacturing the same |
TWI628721B (zh) | 2015-07-08 | 2018-07-01 | 聯華電子股份有限公司 | 氧化物半導體元件及其製造方法 |
EP3136445B1 (en) | 2015-08-25 | 2021-03-17 | Emberion Oy | A method for forming apparatus comprising two dimensional material |
CN105810713A (zh) * | 2016-01-15 | 2016-07-27 | 广州奥翼电子科技股份有限公司 | 柔性显示器及其制备方法 |
CN109416897B (zh) * | 2016-07-29 | 2021-07-02 | 索尼公司 | 显示装置、显示装置制造方法以及电子设备 |
KR102597588B1 (ko) * | 2016-11-23 | 2023-11-02 | 엘지디스플레이 주식회사 | 표시장치와 그의 열화 보상 방법 |
JP7085491B2 (ja) * | 2016-12-02 | 2022-06-16 | 株式会社半導体エネルギー研究所 | 半導体装置 |
CN107146773B (zh) * | 2017-05-15 | 2019-11-26 | 深圳市华星光电半导体显示技术有限公司 | Tft基板的制作方法 |
TWI631741B (zh) * | 2017-10-19 | 2018-08-01 | 元太科技工業股份有限公司 | 驅動基板 |
CN109698241A (zh) * | 2018-12-28 | 2019-04-30 | 天津大学 | 高介电常数栅介质层的柔性薄膜晶体管及其制造方法 |
US11587474B2 (en) | 2019-07-24 | 2023-02-21 | Au Optronics Corporation | Flexible device array substrate and manufacturing method of flexible device array substrate |
Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003258264A (ja) * | 2002-03-05 | 2003-09-12 | Sangaku Renkei Kiko Kyushu:Kk | 電界効果トランジスター、その製造方法及び該電界効果トランジスターを製造するための積層体 |
JP2004297084A (ja) | 1995-02-16 | 2004-10-21 | Semiconductor Energy Lab Co Ltd | 半導体装置の作製方法 |
JP2005123290A (ja) * | 2003-10-15 | 2005-05-12 | Toppan Printing Co Ltd | 薄膜トランジスタおよびその製造方法 |
JP2005166742A (ja) * | 2003-11-28 | 2005-06-23 | Tdk Corp | 積層体の製造方法及び有機電界効果トランジスタの製造方法 |
JP2006269475A (ja) * | 2005-03-22 | 2006-10-05 | Toppan Printing Co Ltd | 薄膜トランジスタの製造方法 |
JP2007067263A (ja) | 2005-09-01 | 2007-03-15 | Konica Minolta Holdings Inc | 有機半導体材料、有機半導体膜、有機半導体デバイス及び有機薄膜トランジスタ |
JP2007073857A (ja) * | 2005-09-09 | 2007-03-22 | Sony Corp | 半導体装置の製造方法および半導体装置 |
JP2008200766A (ja) | 2007-02-16 | 2008-09-04 | Toppan Printing Co Ltd | 断裁装置および製袋機 |
JP2008200767A (ja) | 2007-02-16 | 2008-09-04 | Toyo Tire & Rubber Co Ltd | 研磨パッド溝加工機及び研磨パッド溝加工方法 |
WO2009063583A1 (ja) * | 2007-11-16 | 2009-05-22 | Panasonic Corporation | フレキシブル半導体装置の製造方法及びフレキシブル半導体装置 |
WO2009069248A1 (ja) * | 2007-11-28 | 2009-06-04 | Panasonic Corporation | フレキシブル半導体装置の製造方法およびフレキシブル半導体装置 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB8406330D0 (en) * | 1984-03-10 | 1984-04-11 | Lucas Ind Plc | Amorphous silicon field effect transistors |
JP4472064B2 (ja) * | 1998-08-31 | 2010-06-02 | 株式会社半導体エネルギー研究所 | 半導体装置の製造方法 |
US6509217B1 (en) * | 1999-10-22 | 2003-01-21 | Damoder Reddy | Inexpensive, reliable, planar RFID tag structure and method for making same |
US6197663B1 (en) * | 1999-12-07 | 2001-03-06 | Lucent Technologies Inc. | Process for fabricating integrated circuit devices having thin film transistors |
JP4748986B2 (ja) * | 2002-11-01 | 2011-08-17 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
KR100900542B1 (ko) * | 2002-11-14 | 2009-06-02 | 삼성전자주식회사 | 박막 트랜지스터 기판 및 그의 제조 방법 |
US6905908B2 (en) * | 2002-12-26 | 2005-06-14 | Motorola, Inc. | Method of fabricating organic field effect transistors |
ITTO20030145A1 (it) * | 2003-02-28 | 2004-09-01 | Infm Istituto Naz Per La Fisi Ca Della Mater | Procedimento per la fabbricazione di dispositivi ad effetto di campo a film sottile privi di substrato e transistore a film sottile organico ottenibile mediante tale procedimento. |
TWI372462B (en) * | 2003-10-28 | 2012-09-11 | Semiconductor Energy Lab | Method for manufacturing semiconductor device |
JP2006073774A (ja) * | 2004-09-02 | 2006-03-16 | Matsushita Electric Ind Co Ltd | 薄膜トランジスタ及びその製造方法 |
US7977170B2 (en) * | 2006-10-03 | 2011-07-12 | Eastman Kodak Company | Flexible substrate with electronic devices and traces |
WO2010058541A1 (ja) * | 2008-11-18 | 2010-05-27 | パナソニック株式会社 | フレキシブル半導体装置およびその製造方法 |
-
2009
- 2009-07-30 JP JP2010523736A patent/JP4659925B2/ja active Active
- 2009-07-30 CN CN2009801005512A patent/CN102047396B/zh active Active
- 2009-07-30 EP EP09804694.9A patent/EP2312620A4/en not_active Withdrawn
- 2009-07-30 WO PCT/JP2009/003616 patent/WO2010016207A1/ja active Application Filing
- 2009-07-30 US US12/681,445 patent/US8343822B2/en active Active
- 2009-07-30 KR KR1020107007003A patent/KR20110050580A/ko not_active Application Discontinuation
- 2009-07-31 TW TW098125862A patent/TW201017823A/zh unknown
-
2010
- 2010-12-22 JP JP2010285471A patent/JP5420529B2/ja active Active
-
2012
- 2012-11-28 US US13/687,105 patent/US8525172B2/en active Active
Patent Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004297084A (ja) | 1995-02-16 | 2004-10-21 | Semiconductor Energy Lab Co Ltd | 半導体装置の作製方法 |
JP2003258264A (ja) * | 2002-03-05 | 2003-09-12 | Sangaku Renkei Kiko Kyushu:Kk | 電界効果トランジスター、その製造方法及び該電界効果トランジスターを製造するための積層体 |
JP2005123290A (ja) * | 2003-10-15 | 2005-05-12 | Toppan Printing Co Ltd | 薄膜トランジスタおよびその製造方法 |
JP2005166742A (ja) * | 2003-11-28 | 2005-06-23 | Tdk Corp | 積層体の製造方法及び有機電界効果トランジスタの製造方法 |
JP2006269475A (ja) * | 2005-03-22 | 2006-10-05 | Toppan Printing Co Ltd | 薄膜トランジスタの製造方法 |
JP2007067263A (ja) | 2005-09-01 | 2007-03-15 | Konica Minolta Holdings Inc | 有機半導体材料、有機半導体膜、有機半導体デバイス及び有機薄膜トランジスタ |
JP2007073857A (ja) * | 2005-09-09 | 2007-03-22 | Sony Corp | 半導体装置の製造方法および半導体装置 |
JP2008200766A (ja) | 2007-02-16 | 2008-09-04 | Toppan Printing Co Ltd | 断裁装置および製袋機 |
JP2008200767A (ja) | 2007-02-16 | 2008-09-04 | Toyo Tire & Rubber Co Ltd | 研磨パッド溝加工機及び研磨パッド溝加工方法 |
WO2009063583A1 (ja) * | 2007-11-16 | 2009-05-22 | Panasonic Corporation | フレキシブル半導体装置の製造方法及びフレキシブル半導体装置 |
WO2009069248A1 (ja) * | 2007-11-28 | 2009-06-04 | Panasonic Corporation | フレキシブル半導体装置の製造方法およびフレキシブル半導体装置 |
Non-Patent Citations (1)
Title |
---|
See also references of EP2312620A4 |
Cited By (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP7174882B2 (ja) | 2010-01-22 | 2022-11-17 | 株式会社半導体エネルギー研究所 | 半導体装置 |
JP2022167961A (ja) * | 2010-01-22 | 2022-11-04 | 株式会社半導体エネルギー研究所 | 半導体装置 |
WO2011142081A1 (ja) * | 2010-05-12 | 2011-11-17 | パナソニック株式会社 | フレキシブル半導体装置およびその製造方法 |
US8525178B2 (en) | 2010-05-12 | 2013-09-03 | Panasonic Corporation | Flexible semiconductor device and method for producing the same |
JP5719992B2 (ja) * | 2010-05-12 | 2015-05-20 | パナソニックIpマネジメント株式会社 | フレキシブル半導体装置およびその製造方法 |
WO2011142089A1 (ja) * | 2010-05-14 | 2011-11-17 | パナソニック株式会社 | フレキシブル半導体装置およびその製造方法ならびに画像表示装置 |
CN102598231A (zh) * | 2010-05-14 | 2012-07-18 | 松下电器产业株式会社 | 柔性半导体装置及其制造方法以及图像显示装置 |
JPWO2011142089A1 (ja) * | 2010-05-14 | 2013-07-22 | パナソニック株式会社 | フレキシブル半導体装置およびその製造方法ならびに画像表示装置 |
JP2019216276A (ja) * | 2010-09-03 | 2019-12-19 | 株式会社半導体エネルギー研究所 | 半導体装置 |
JP2021013036A (ja) * | 2011-01-12 | 2021-02-04 | 株式会社半導体エネルギー研究所 | トランジスタ及び半導体装置 |
US10084072B2 (en) | 2011-11-30 | 2018-09-25 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
JP2017092485A (ja) * | 2011-11-30 | 2017-05-25 | 株式会社半導体エネルギー研究所 | 半導体装置 |
JP2019208058A (ja) * | 2013-09-05 | 2019-12-05 | 株式会社半導体エネルギー研究所 | 表示装置 |
JP2020074499A (ja) * | 2013-09-05 | 2020-05-14 | 株式会社半導体エネルギー研究所 | 表示装置 |
JP2020149058A (ja) * | 2013-09-05 | 2020-09-17 | 株式会社半導体エネルギー研究所 | 表示装置 |
JP2015053444A (ja) * | 2013-09-09 | 2015-03-19 | パナソニックIpマネジメント株式会社 | フレキシブル半導体装置およびその製造方法ならびに画像表示装置 |
JP2015055872A (ja) * | 2013-09-11 | 2015-03-23 | 三星ディスプレイ株式會社Samsung Display Co.,Ltd. | 表示パネル及びその製造方法 |
JP2017168838A (ja) * | 2016-03-10 | 2017-09-21 | 株式会社半導体エネルギー研究所 | トランジスタ、電子機器 |
Also Published As
Publication number | Publication date |
---|---|
TW201017823A (en) | 2010-05-01 |
US8343822B2 (en) | 2013-01-01 |
US8525172B2 (en) | 2013-09-03 |
EP2312620A1 (en) | 2011-04-20 |
CN102047396A (zh) | 2011-05-04 |
US20130168677A1 (en) | 2013-07-04 |
JP5420529B2 (ja) | 2014-02-19 |
EP2312620A4 (en) | 2013-12-25 |
KR20110050580A (ko) | 2011-05-16 |
CN102047396B (zh) | 2013-01-09 |
JP2011101030A (ja) | 2011-05-19 |
JP4659925B2 (ja) | 2011-03-30 |
US20100283054A1 (en) | 2010-11-11 |
JPWO2010016207A1 (ja) | 2012-01-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4659925B2 (ja) | フレキシブル半導体装置およびその製造方法 | |
JP4550944B2 (ja) | フレキシブル半導体装置およびその製造方法 | |
US8367488B2 (en) | Manufacturing method of flexible semiconductor device | |
JP4653860B2 (ja) | フレキシブル半導体装置およびその製造方法 | |
JP4370366B2 (ja) | フレキシブル半導体装置の製造方法およびフレキシブル半導体装置 | |
CN102742013B (zh) | 柔性半导体装置的制造方法 | |
JP5719992B2 (ja) | フレキシブル半導体装置およびその製造方法 | |
US8617943B2 (en) | Method for making a semiconductor device on a flexible substrate | |
TW200913336A (en) | Semiconductor device, manufacturing method thereof and image display device | |
JP2005354035A (ja) | 半導体装置の形成方法 | |
CN101714611A (zh) | 薄膜晶体管及其制造方法、和电子设备 | |
JP2010238873A (ja) | フレキシブル半導体装置およびその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 200980100551.2 Country of ref document: CN |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 09804694 Country of ref document: EP Kind code of ref document: A1 |
|
ENP | Entry into the national phase |
Ref document number: 20107007003 Country of ref document: KR Kind code of ref document: A |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2009804694 Country of ref document: EP |
|
ENP | Entry into the national phase |
Ref document number: 2010523736 Country of ref document: JP Kind code of ref document: A |
|
WWE | Wipo information: entry into national phase |
Ref document number: 12681445 Country of ref document: US |
|
NENP | Non-entry into the national phase |
Ref country code: DE |