WO2011142081A1 - フレキシブル半導体装置およびその製造方法 - Google Patents
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- WO2011142081A1 WO2011142081A1 PCT/JP2011/002203 JP2011002203W WO2011142081A1 WO 2011142081 A1 WO2011142081 A1 WO 2011142081A1 JP 2011002203 W JP2011002203 W JP 2011002203W WO 2011142081 A1 WO2011142081 A1 WO 2011142081A1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K2102/00—Constructional details relating to the organic devices covered by this subclass
- H10K2102/301—Details of OLEDs
- H10K2102/311—Flexible OLED
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
Definitions
- the present invention relates to a flexible semiconductor device and a manufacturing method thereof.
- a display medium is formed using an element using liquid crystal, organic EL (organic electroluminescence), electrophoresis, or the like.
- a technique using an active drive element (TFT element) as an image drive element has become mainstream in order to ensure uniformity of screen brightness, screen rewrite speed, and the like.
- TFT element active drive element
- these TFT elements are formed on a substrate, and liquid crystal, organic EL elements, etc. are sealed.
- semiconductors such as a-Si (amorphous silicon) and p-Si (polysilicon) can be mainly used for the TFT elements, and these Si semiconductors (and metal films as necessary) are multilayered.
- a TFT element is manufactured by sequentially forming source, drain, and gate electrodes on a substrate.
- the substrate material is restricted to be a material that can withstand the process temperature. Therefore, in practice, it is necessary to use a material having excellent heat resistance, such as a glass substrate, as the substrate.
- a quartz substrate can be used, it is expensive, and there is an economical problem in increasing the size of the display. Therefore, a glass substrate is generally used as a substrate on which TFT elements are formed.
- the display is heavy, lacks flexibility, and may be broken by a drop impact.
- These characteristics resulting from the formation of TFT elements on a glass substrate are undesirable in satisfying the need for an easy-to-use portable thin display accompanying the progress of computerization.
- Patent Document 2 discloses a technique in which a TFT element is manufactured on a support (for example, a glass substrate) by a process substantially similar to the conventional process, and then the TFT element is peeled off from the glass substrate and transferred onto a resin substrate. ing.
- a TFT element is formed on a glass substrate, and the TFT element is adhered to the resin substrate through a sealing layer such as an acrylic resin, and then the glass substrate is peeled off, whereby the TFT element is formed on the resin substrate.
- Developments have been made in the formation of TFT elements that do not use a glass substrate as a final component by forming them by transfer.
- TFT elements and peripheral circuits used in the display unit and drive unit of a display device require finer elements, higher integration, and multi-layering.
- TFT elements are formed by sequentially forming them on the substrate and forming them into multiple layers, if the wiring is multilayered, parasitic capacitance is generated between the wirings arranged above and below via the insulating film between layers, and the operation speed is increased. The problem of disturbing may occur.
- it is necessary to take measures such as forming a thick insulating film between layers and using a low dielectric constant material for the insulating film material.
- the vertical interval (insulating film thickness) of the wiring is reduced, or the dielectric layer (insulating film) of the capacitor part. It is necessary to devise a method such as forming the film by a process different from that of the insulating film or using a material having a high dielectric constant.
- the present invention has been made in view of the above points, and its main object is to reduce a parasitic capacitance generated between multilayer wirings (wirings arranged above and below), and a capacitor incorporated in a semiconductor element or circuit. It is to provide a flexible semiconductor device capable of increasing the capacity of a part and a method for manufacturing the same.
- the flexible semiconductor device according to the present invention is a flexible semiconductor device including an insulating film on which a semiconductor element is formed, and having an upper wiring pattern layer and a lower wiring pattern layer on the upper surface and the lower surface of the insulating film, respectively.
- the semiconductor element is A semiconductor layer formed on an upper surface of the insulating film; A source electrode and a drain electrode formed on an upper surface of the insulating film so as to be in contact with the semiconductor layer; A gate electrode formed on the lower surface of the insulating film so as to face the semiconductor layer, The upper surface of the gate electrode protrudes from the upper surface of the lower wiring pattern layer to the semiconductor layer side,
- the first film thickness of the insulating film facing the source electrode, the drain electrode, the upper wiring pattern layer, and the lower wiring pattern layer is a second thickness of the insulating film between the gate electrode and the semiconductor layer. It is characterized by being thicker than the film thickness.
- the first film thickness of the insulating film facing the source electrode, the drain electrode, the upper wiring pattern layer, and the lower wiring pattern layer is the gate. Since it is thicker than the second film thickness of the insulating film between the electrode and the semiconductor layer, in the capacitor portion incorporated in the semiconductor element, parasitic capacitance generated between the wirings is ensured even when the wiring is multilayered while ensuring a large capacity. Capacity can be reduced.
- the first film thickness is 1 ⁇ m or more thicker than the second film thickness.
- the gate electrode and the lower wiring pattern layer may be made of the same kind of metal.
- the metal may be selected from aluminum, silver, nickel, iron, copper, or an alloy foil containing any one of them.
- the surface roughness of the upper surface of the gate electrode in contact with the insulating film is smaller than the surface roughness of the upper surface of the lower wiring pattern in contact with the insulating film. In this way, the film thickness variation of the insulating film on the gate electrode functioning as the gate insulating film can be reduced while maintaining high adhesion strength between the insulating film and the lower wiring pattern, and the electrical characteristics are excellent.
- a gate insulating film can be formed.
- the surface roughness of the upper surface of the gate electrode is preferably set to an Ra value of 100 nm or less, more preferably an Ra value of 50 nm or less.
- the surface roughness of the upper surface of the lower wiring pattern is preferably Ra value 500 nm or more, more preferably Ra value 1 ⁇ m or more.
- a sealing layer made of an insulating material covering the semiconductor layer is formed on the semiconductor layer.
- the sealing layer may be made of a resin material, or may be composed of a film-like core material and resin layers laminated on both surfaces of the core material.
- the interlayer connection via that electrically connects the source electrode and the lower electrode or between the drain electrode and the lower electrode
- the interlayer connection via It is preferable that the gate electrode and the lower wiring pattern layer are made of the same kind of metal.
- a capacitor may be further formed by an upper electrode formed on the upper surface of the insulating film and a lower electrode formed on the lower surface of the insulating film so as to face the upper electrode.
- the third film thickness of the insulating film between the upper electrode and the lower electrode is preferably smaller than the first film thickness, and the third film thickness is 1 ⁇ m from the first film thickness. More preferably, it is thinner.
- the flexible semiconductor device may have two layers of the insulating film, and the semiconductor element may be provided on each of the insulating films. Further, at that time, the two-layer insulating film is bonded via the interlayer insulating film, and the semiconductor elements respectively formed on the two-layer insulating film are provided with an interlayer connection provided through the interlayer insulating film. It is preferable that they are connected via a member. Furthermore, it is preferable that the interlayer insulating film is formed as a sealing layer covering one semiconductor element provided in the two insulating films.
- a method for manufacturing a flexible semiconductor device includes: A gate electrode and a lower wiring pattern layer connected to the gate electrode are formed on the lower surface of the insulating film, a semiconductor layer opposed to the gate electrode on the upper surface of the insulating film, a source electrode and a drain electrode connected to the semiconductor layer, A method for manufacturing a flexible semiconductor device in which is formed, A lower electrode wiring manufacturing step of forming one or more convex portions on one surface of the metal foil; An insulating film forming step of forming the insulating film on the one surface on which the convex portions are formed so that a film thickness on the convex portions is thinner than a film thickness on the concave portions excluding the convex portions; A semiconductor layer forming step of forming the semiconductor layer on the insulating film so as to face at least one of the convex portions; It is characterized by including.
- the convex portion in the lower electrode wiring manufacturing step, can be formed by etching, and on the surface of the metal foil, the same metal material as the metal foil, or The convex portions can also be formed by stacking different metal materials.
- the convex portion is formed so that the height of the convex portion is 1 ⁇ m or more.
- convex portions having different heights may be formed in the convex portion forming step.
- an interlayer connection via for connecting the lower wiring pattern layer and the source electrode or the drain electrode can be formed.
- an upper electrode wiring manufacturing step of forming an upper wiring pattern connected to the source electrode, the drain electrode, and the source electrode or the drain electrode on the upper surface of the insulating film is performed. Can be included.
- an upper electrode connected to the upper wiring pattern is formed so as to face at least one of the convex portions, and a capacitor is formed.
- An element may be formed.
- an electrode wiring pattern is formed by applying a liquid material in which a conductive material is dissolved in a solvent, and the solvent is removed from the electrode wiring pattern. May include.
- the insulating film forming step includes: Forming a coating film by dissolving and coating an insulating film material in a solvent on one surface of the metal foil; and Removing the solvent from the coating film.
- a second insulating film made of the same or different insulating film material as the first insulating film is formed in the recess, and includes the first insulating film and the second insulating film.
- the insulating film may be formed.
- the semiconductor layer forming step includes: Depositing a semiconductor material on the insulating film; A crystallization step of heat-treating the deposited semiconductor material to crystallize the semiconductor material; May be included.
- the method for manufacturing a flexible semiconductor device according to the present invention may include a heat treatment at 400 ° C. or higher.
- the source electrode, the drain electrode, and the semiconductor layer are placed between the insulating film and the resin sheet by pressing a resin sheet on the upper surface of the insulating film.
- a sealing step of embedding and sealing can be included.
- two first and second flexible semiconductor devices are manufactured by the method for manufacturing a flexible semiconductor device,
- the lower wiring pattern of the first flexible semiconductor device and the upper wiring pattern of the second flexible semiconductor device are pressed against each other through a resin sheet, whereby the first and second flexible semiconductor devices are bonded together.
- the resin sheet is formed with a via having one end connected to the gate electrode or the lower wiring pattern of the first flexible semiconductor device and the other end connected to the upper wiring pattern of the first flexible semiconductor device. .
- the flexible semiconductor device of the present invention it is possible to reduce the parasitic capacitance / leakage current generated between the wirings causing delay and loss, and the gate insulating film of a semiconductor element such as a TFT element.
- a semiconductor element such as a TFT element.
- the capacitor element portion formed in the portion or the substrate it is possible to secure a capacity, and it is possible to improve the characteristics of each element.
- the manufacturing method which can manufacture the said flexible semiconductor device of this invention is provided.
- the method for manufacturing a flexible semiconductor device according to the present invention is a simplified manufacturing method because it is possible to adjust the film thickness of the insulating film by forming a concavo-convex portion by a simple process by using a metal foil as a supporting substrate.
- a flexible semiconductor device can be manufactured in the process.
- a metal foil is used as a support substrate, it is also possible to use a semiconductor material or an insulating film material that has superior characteristics that require formation at a higher temperature than a mode in which a resin substrate is used as the support substrate. Therefore, according to the manufacturing method according to the present invention, a flexible semiconductor device having high performance and excellent productivity can be provided.
- FIG. (A) is a cross-sectional schematic diagram which shows the cross section of the flexible semiconductor device 100 which concerns on one Embodiment of this invention
- (b) is an upper surface schematic which shows the upper surface of the flexible semiconductor device 100 which concerns on one Embodiment of this invention.
- FIG. (A)-(g) is process sectional drawing which shows the manufacturing process of the flexible semiconductor device 100 which concerns on one Embodiment of this invention.
- (A)-(g) is process sectional drawing which shows the manufacturing process of the flexible semiconductor device 200 which concerns on one Embodiment of this invention.
- (A)-(h) is process sectional drawing which shows the manufacturing process of the flexible semiconductor device 300 which concerns on one Embodiment of this invention.
- (A)-(h) is process sectional drawing which shows the manufacturing process of the flexible semiconductor device 400 which concerns on one Embodiment of this invention.
- (A) is a cross-sectional schematic diagram which shows the flexible semiconductor device 500 concerning one Embodiment of this invention
- (b) is an equivalent circuit diagram which shows the drive circuit of the image display apparatus concerning one Embodiment of this invention.
- (A)-(c) is process sectional drawing which shows the manufacturing process of the flexible semiconductor device 500 concerning one Embodiment of this invention.
- FIG. 1B is a schematic top view of the flexible semiconductor device 100
- FIG. 1A is a schematic cross-sectional view showing a cross section taken along the line Ia-Ia in FIG.
- the flexible semiconductor device 100 includes an insulating film 20, a source electrode 40 s and a drain electrode 40 d formed on the insulating film 20, a semiconductor layer 30, a gate insulating film 20 g that functions as a gate insulating film, and a gate electrode 10 g. And a lower wiring pattern layer 10a that is extracted from the gate electrode 10g and functions as a wiring portion.
- the sealing layer 50 also serves as a base material for supporting the TFT structure, and is preferably made of a flexible resin material that can be bent even after being cured. Moreover, it is preferable to make it thin as long as the TFT structure can be supported.
- resin materials include, for example, epoxy resins, polyimide (PI) resins, acrylic resins, polyethylene terephthalate (PET) resins, polyethylene naphthalate (PEN) resins, polyphenylene sulfide (PPS) resins, polyphenylene ethers (PPE). ) Resin, polyparaxylylene (PPX) resin and composites thereof. These resin materials are excellent in the property of dimensional stability, and are preferable as materials for the flexible substrate in the flexible semiconductor device 100 of the present embodiment.
- the sealing layer 50 has a semiconductor layer 30 and a source electrode 40 s and a drain electrode 40 d formed so as to be in contact with the semiconductor layer 30 embedded therein.
- a semiconductor such as silicon (for example, Si) or germanium (Ge) may be used, or an oxide semiconductor may be used.
- the oxide semiconductor include simple oxides such as zinc oxide (ZnO), tin oxide (SnO 2 ), indium oxide (In 2 O 3 ), and titanium oxide (TiO 2 ), InGaZnO, InSnO, InZnO, and ZnMgO. These composite oxides are mentioned.
- a compound semiconductor for example, GaN, SiC, ZnSe, CdS, GaAs, etc.
- an organic semiconductor for example, pentacene, poly-3-hexylthiophene, porphyrin derivative, copper phthalocyanine, C60, etc.
- the metal constituting the source electrode 40s and the drain electrode 40d is preferably a metal material having good conductivity.
- copper (Cu), nickel (Ni), aluminum (Al), stainless steel (SUS), gold (Au) Silver (Ag) can be used.
- An insulating film 20 including a gate insulating film 20g is provided under the semiconductor layer 30, the source electrode 40s, and the drain electrode 40d.
- An inorganic compound having a dielectric constant and excellent insulating properties is preferred.
- Typical examples of inorganic compounds having such a relative dielectric constant and insulating properties include, for example, tantalum oxide (Ta 2 O 5 etc.), aluminum oxide (Al 2 O 3 etc.), silicon oxide (SiO 2 etc.) , Zeolite oxide (such as ZrO 2 ), titanium oxide (such as TiO 2 ), yttrium oxide (such as Y 2 O 3 ), lanthanum oxide (such as La 2 O 3 ), hafnium oxide (such as HfO 2 ), etc. And metal nitrides thereof.
- a dielectric such as barium titanate (BaTiO 3 ), strontium titanate (SrTiO 3 ), or calcium titanate (CaTiO 3 ) may be used.
- a gate electrode 10g is formed under the gate insulating film 20g, and a lower wiring pattern layer 10a connected to the gate electrode 10g is formed integrally with the gate electrode 10g.
- the upper surface of the gate electrode 10g protrudes in the direction of the semiconductor layer 30 from the upper surface of the lower wiring pattern layer 10a, and the thickness of the gate insulating film 20g on the gate electrode 10g is the other electrode or pattern. It is thinner than the thickness of the insulating film facing (source electrode, drain electrode, upper wiring pattern layer, lower wiring pattern layer, etc.).
- the metal constituting the gate electrode 10g and the lower wiring pattern layer 10a is preferably a metal material having good conductivity, such as copper (Cu), nickel (Ni), aluminum (Al), or stainless steel (SUS). can do.
- the flexible semiconductor device of the first embodiment configured as described above, it is possible to reduce the parasitic capacitance / leakage current generated between the wirings causing delay and loss, and to reduce the semiconductor element such as a TFT element. Capacitance can be secured in the gate insulating film portion and the capacitor element portion formed in the substrate, and the characteristics of each element can be improved.
- 2A to 2G are process cross-sectional views for explaining the manufacturing process of the flexible semiconductor device 100. FIG. This will be described below.
- a metal foil 10 is prepared.
- the metal foil 10 for example, a SUS foil having a thickness of 70 ⁇ m can be used.
- the metal foil 10 is processed to form a convex portion for forming the gate electrode 10g.
- a similar convex portion is also formed on the portion that becomes the lower electrode of the capacitor.
- This convex portion can be formed by etching, for example.
- An appropriate etchant may be used according to the material of the metal foil 10 and the like.
- ferric chloride can be used.
- the metal foil 10 for example, it is preferable to use a metal foil having a small surface roughness with an Ra value (arithmetic average roughness) of 100 nm or less.
- the surface roughness of the upper surface of the convex portion can be reduced, and an insulating film having a small film thickness variation can be formed thinly on the upper surface of the convex portion.
- the gate insulating film 20g having a high withstand voltage can be formed.
- the convex portion is formed by etching, even when a metal foil having a small surface roughness is used, the etching surface other than the upper surface of the convex portion (the upper surface of the lower wiring pattern) is compared with the upper surface of the convex portion.
- the surface roughness can be increased, and the adhesion strength between the insulating film 20 and the lower wiring pattern 10a can be increased.
- the surface roughness of the upper surface of the lower wiring pattern is preferably set to an Ra value (arithmetic average roughness) of 500 nm or more by adjusting etching conditions or the like.
- the insulating film 20 including the gate insulating film 20g is formed on the metal foil 10 on which the convex portions are formed in the step (b).
- the formation of the insulating film 20 can include a process executed at the heat resistant temperature of the metal foil 10. Examples of the method for forming the insulating film 20 include a sol-gel method and a chemical synthesis method.
- a dispersion solution in which nanoparticles of barium titanate (BaTiO 3 ) are dispersed is applied onto the metal foil 10 and dried, and then pre-baked and main-baked (for example, a baking temperature of 600) under a nitrogen atmosphere.
- the coating method of the dispersion solution is not particularly limited, and for example, a dip method, a spin coating method, a roll coating method, a curtain coating method, a spray method, a droplet discharge method, or the like can be used.
- the insulating film 20 manufactured through such a baking process (high temperature process) has a higher relative dielectric constant than a polymer material, and thus is particularly preferable as a material for the insulating film 20 in the flexible semiconductor device 100.
- an insulating film is formed on the surface of the metal foil 10 that is uneven due to the formation of the convex portion. Even in this case, it is easy to flatten the surface of the insulating film.
- a method for forming the insulating film 20 other general thin film forming methods can be used, and typical examples thereof include a vacuum deposition method, a laser ablation method, a sputtering method, and a CVD method (for example, a plasma method). CVD method).
- the laser ablation method can form a film with little composition change of the inorganic compound.
- the CVD method is preferable in that an inorganic insulating film can be easily formed, a multi-component film can be synthesized, and a high dielectric constant film can be formed.
- a semiconductor layer 30 facing the gate electrode 10g is formed on the gate insulating film 20g.
- the semiconductor layer 30 is formed, for example, by depositing a semiconductor material on the upper surface of the insulating film 20.
- a thin film forming process such as a vacuum evaporation method, a sputtering method, or a plasma CVD method, or a printing process such as an inkjet method can be used.
- the formation of the semiconductor layer 30 can include a process executed at a temperature that does not exceed the heat resistance temperature of the metal foil 10 and the insulating film 20.
- the heat treatment is preferably performed on the deposited semiconductor material.
- the method for heating the semiconductor material is not particularly limited, and may be, for example, a thermal annealing process (atmosphere heating), a laser annealing process, or a process using them together. By performing the heat treatment (high-temperature process) in this manner, crystallization of the semiconductor proceeds, and as a result, semiconductor characteristics (typically carrier mobility) can be improved.
- the semiconductor layer 30 can be formed as follows. First, the cyclopentasilane-containing solution is irradiated with UV to obtain a higher order silane compound, and then the higher order silane compound-containing solution is applied to the upper surface of the inorganic insulating film 20. Next, the semiconductor layer 30 made of amorphous silicon is formed by heat treatment at 300 ° C. to 600 ° C. Then, a polysilicon film having high carrier mobility is formed by performing laser annealing.
- the method for applying the solution is not particularly limited, and for example, a spin coating method, a roll coating method, a curtain coating method, a spray method, a droplet discharge method, or the like may be used.
- an oxide semiconductor for example, a mixture of organometallics is deposited on the insulating film 20, and is heat-treated (for example, 600 ° C. or higher) to be sintered, whereby an oxide semiconductor having high carrier mobility. Can be formed.
- the source electrode 40s and the drain electrode 40d are formed so as to be in contact with the semiconductor layer 30, and the upper wiring pattern layer including the source electrode 40s and the drain electrode 40d is formed.
- a method for forming the upper wiring pattern layer including the source electrode 40s and the drain electrode 40d is not particularly limited.
- the upper wiring pattern layer can be easily formed by a vacuum deposition method or a sputtering method.
- a method of curing by heating or a method of printing and baking nano metal particle ink by an ink jet method may be used.
- Examples of the material of the source electrode 40s and the drain electrode 40d include gold (Au), silver (Ag), copper (Cu), nickel (Ni), chromium (Cr), cobalt (Co), magnesium (Mg), and calcium. (Ca), platinum (Pt), molybdenum (Mo), iron (Fe), zinc (Zn) and other metal materials, tin oxide (SnO2), indium tin oxide (ITO), fluorine-containing tin oxide (FTO), Examples thereof include conductive oxides such as ruthenium oxide (RuO2), iridium oxide (IrO2), and platinum oxide (PtO2).
- a sealing layer 50 is formed so as to cover the surface on which the semiconductor layer 30, the source electrode 40s, and the drain electrode 40d are formed.
- the method for forming the sealing layer 50 is not particularly limited. For example, a method of bonding a semi-cured resin sheet onto the semiconductor layer 30, the source electrode 40s, and the drain electrode 40d and curing (in this case, the bonding surface of the resin sheet) Or an adhesive material may be applied to the semiconductor layer 30, the source electrode 40s, and the drain electrode 40d by spin coating or the like and cured. .
- the sealing layer 50 it is possible to protect the semiconductor layer 30 and to stably handle and transport the next process (such as the etching process of the metal layer 10).
- the sealing layer 50 is formed by pressure-bonding (adhering while applying pressure) the resin sheet 50 to the surface on which the semiconductor layer 30, the source electrode 40s, and the drain electrode 40d are formed. .
- the resin sheet 50 is laminated and integrated, and the semiconductor layer 30, the source electrode 42 s and the drain electrode 42 d are embedded in the resin sheet 50.
- the resin sheet 50 for example, a resin film surface coated with an adhesive material (for example, epoxy resin, acrylic resin, polyimide resin, etc.), an uncured resin film, or the like can be used.
- the resin sheet 50 is prepared by applying an adhesive epoxy resin to the surface of a polyimide resin film having a thickness of 12.5 ⁇ m, and is bonded and integrated on the upper surface of the insulating film 20.
- the gate electrode 10g and the lower wiring pattern layer 10a are formed from the metal foil 10 by etching the metal foil 10 on which the convex portions to be the gate electrode 10g are formed.
- An appropriate etchant may be used according to the material of the metal foil 10.
- ferric chloride can be used.
- the flexible semiconductor device 100 can be constructed.
- the insulating films of the upper wiring pattern layer including the source electrode and the drain electrode and the lower wiring pattern layer are thickened by a simple method and formed in the gate insulating film portion of the TFT element or in the substrate.
- the insulating film on the capacitor portion can be controlled to be thin, and the parasitic capacitance and leakage current generated between the wirings can be suppressed, and a semiconductor element and a capacitor having high characteristics can be manufactured with high productivity.
- the convex portion that becomes the gate electrode 10g is formed on the metal foil 10, and the insulating film thereon is thinned by the convex portion.
- the semiconductor layer 30, the source electrode, and the drain electrode can be accurately formed on the flat surface. Furthermore, it is possible to form the capacitor part of the required capacity without forming the dielectric layer of the capacitor part incorporated in the semiconductor element or circuit in a process different from that of the insulating film or using a high dielectric constant material. become.
- a metal material as a support substrate, it is possible to use a semiconductor material or an insulating film material that has superior characteristics that require formation at a higher temperature than a form in which a resin substrate is used as a support substrate. According to the method, a flexible semiconductor device having high performance and excellent productivity can be provided.
- each of the plurality of TFTs is inspected and evaluated, and only the ones evaluated as good are selected to form the sealing layer 50. Can do. According to this aspect, the occurrence of defects in the final product can be prevented in the middle of manufacturing, and waste of materials and the like in the subsequent process can be eliminated. Further, by forming the sealing layer 50 on the semiconductor layer 30 after the inspection / evaluation, it is possible to improve the reliability by suppressing the occurrence of defects and the deterioration of the semiconductor characteristics in a later process as a good protective layer.
- FIG. 3 shows a configuration of a flexible semiconductor device 200 according to an embodiment of the present invention.
- the second embodiment is different from the first embodiment described above in that a multilayer metal foil in which different metal materials have a structure of two or more layers is used. That is, the prepared metal foil has a multilayer structure, and the gate electrode 10g and the lower wiring pattern layer 10a are formed of different metal materials.
- Embodiment 2 An example of the manufacturing process of Embodiment 2 will be described with reference to FIGS. 3 (a) to 3 (g). It should be noted that description of parts other than the matters specifically mentioned and overlapping with the first embodiment will be omitted.
- a multilayer metal foil 60 in which a first metal layer 61 and a second metal layer 62 are sequentially laminated is prepared.
- the metal constituting the first metal layer 61 and the second metal layer 62 is preferably a metal having conductivity and a relatively high melting point, such as copper (Cu, melting point: 1083 ° C.), nickel (Ni, melting point: 1453 ° C.), aluminum (Al, melting point: 660 ° C.), and stainless steel (SUS) can be used and can be used in combination. Further, a material in which a conductive oxide is deposited on the second metal layer 62 can also be used.
- the lamination method is not particularly limited, and can be performed by, for example, a vacuum deposition method, a sputtering method, a plasma CVD method, a plating method, or the like.
- a SUS foil having a thickness of 70 ⁇ m is used as the second metal foil 62
- a multilayer metal foil 60 in which a Cu layer having a thickness of 2 ⁇ m is formed is used as the first metal foil 61.
- the gate electrode 61g and the capacitor electrode portion are formed by etching the first metal layer 61.
- the first metal layer 61 is deposited using a mask in FIG.
- the insulating film 20 and the gate insulating film 20g are formed in the same manner as in FIGS. 2C to 2F described above, After the semiconductor layer 30 is formed on the insulating film 20 and the upper wiring pattern layer including the source electrode 40s and the drain electrode 40d is formed, the upper wiring pattern layer including the semiconductor layer 30, the source electrode 40s and the drain electrode 40d is formed. The process of forming the resin layer 50 so that the covered surface may be covered is performed.
- the second metal layer 62 is etched to form a lower wiring pattern layer 62a from the second metal layer 62.
- An appropriate etchant may be used according to the material of the second metal foil 62.
- ferric chloride can be used.
- the flexible semiconductor device 200 according to the second embodiment can be constructed.
- the manufacturing method of the second embodiment by selecting materials having different etching rates and etchants for the first metal layer 61 and the second metal layer 62, the upper wiring pattern layer including the source electrode 40s and the drain electrode 40d It is easy to control the thickness of the insulating film between the lower wiring pattern layers, and by forming a desired insulating film thickness, it is possible to design a highly accurate structure considering electric characteristics, and to provide a flexible semiconductor device having excellent electric characteristics. Can be provided.
- FIG. 4 shows a configuration of a flexible semiconductor device 300 according to an embodiment of the present invention.
- the third embodiment is different from the first embodiment described above in that the second insulating film 21 is formed together with the insulating film 20 in the recess formed in the metal foil 10.
- An example of the manufacturing process will be described with reference to FIGS. 4 (a) to 4 (h). It should be noted that description of parts other than the matters specifically mentioned and overlapping with the first embodiment will be omitted.
- a metal foil 10 is prepared (produced, purchased, etc.).
- the metal foil 10 can be, for example, a SUS foil having a thickness of 70 ⁇ m.
- the metal foil 10 is etched to form a convex portion to be a gate electrode and a capacitor electrode and other concave portions on the surface of the metal foil 10.
- the insulating film 20 including the gate insulating film 20g is formed on the metal foil 10 on which the convex portions and concave portions are formed in the step (b). Form the same thickness.
- the method for forming the insulating film 20 include a sol-gel method and a chemical synthesis method.
- a method for applying the solution of the insulating film 20 for example, a dipping method, a spin coat method, a roll coat method, a curtain coat method, a spray method, a droplet discharge method, or the like can be used.
- a general thin film forming method can be used, and typical examples thereof include a vacuum deposition method, a laser ablation method, a sputtering method, a CVD method (for example, a plasma CVD method), and the like.
- a vacuum deposition method for example, a vacuum deposition method
- a laser ablation method for example, a laser ablation method
- a sputtering method for example, a plasma CVD method
- CVD method for example, a plasma CVD method
- the like can be used to easily form the insulating film 20 having the same thickness over the convex portion and the concave portion.
- the insulating film 20 may be a metal oxide film of a metal constituting the metal foil 10. In that case, the insulating film 20 can be formed by oxidizing the upper surface of the metal foil 10.
- the oxidation treatment of the metal foil 10 is performed by, for example, an anodic oxidation method, a thermal oxidation method (surface oxidation treatment by heating), or a chemical oxidation method (surface oxidation treatment by an oxidizing agent).
- the metal which comprises the metal foil 10 should just be a metal which can be oxidized by the said oxidation process, and is not restrict
- a valve metal eg, aluminum, tantalum, etc.
- an anodic oxidation method can be applied, and an oxide film can be easily formed on the metal surface (for example, 1 ⁇ m or less, preferably 0.6 ⁇ m or less).
- a second insulating film 21 is further formed in the recesses formed in the metal foil 10.
- the second insulating film 21 may be made of a material different from that of the insulating film 20 or the same material. Therefore, the material of the insulating film 20 described above can be used for the second insulating film 21.
- the forming method include a sol-gel method and a chemical synthesis method.
- a coating method for example, a droplet discharge method using an inkjet method can be used.
- a general thin film forming method can be used, and typical examples thereof include a vacuum evaporation method and a sputtering method using a mask.
- the thickness of the second insulating film 21 can be arbitrarily set such that the total thickness of the second insulating film 21 and the insulating film 20 is larger than that of the insulating film 20.
- the second insulating film 21 can be formed so as to be recessed by about 1 ⁇ m from the surface of the insulating film 20 formed on the part.
- a semiconductor layer 30 is formed.
- the source electrode 40s and the drain electrode 40d are formed so as to be in contact with the semiconductor layer 30, and the upper wiring pattern layer including the source electrode 40s and the drain electrode 40d is formed.
- the formation method of the upper wiring pattern layer including the source electrode 40s and the drain electrode 40d is not particularly limited as described in the first and second embodiments, and can be easily performed by, for example, a vacuum deposition method or a sputtering method. Other methods (for example, a method of printing and curing an organic metal paste, a method of printing and baking nano metal particle ink by an ink jet method, etc.) may be used. Therefore, FIG.
- FIG. 4 of the third embodiment shows an example in which the upper wiring pattern layer including the source electrode 40s and the drain electrode 40d is formed using an ink jet method.
- the convex portion in FIG. 4D, by forming the convex portion so that the upper surface of the gate insulating film 10g is raised, the convex portion functions as a partition, and it is not necessary to form the partition in a separate process in the wiring formation by the ink jet method. It is possible to form a narrow pitch between the source electrode and the drain electrode.
- the upper wiring including the semiconductor layer 30, the source electrode 40s, and the drain electrode 40d in the same manner as in the first and second embodiments described above.
- the resin layer 50 is formed so as to cover the surface on which the pattern layer is formed, and the metal foil 10 is etched to form the gate electrode 10g and the lower wiring pattern layer 10a from the metal foil 10.
- the flexible semiconductor device 300 according to the third embodiment can be constructed.
- a thin gate insulating film on the gate electrode is formed to form a TFT element having high characteristics, and parasitic capacitance and leakage current between the upper wiring pattern layer and the lower wiring pattern layer are suppressed. It becomes possible to do.
- the upper wiring pattern layer is formed by an ink jet method, it is possible to easily form a convex portion that becomes a partition wall, and it is possible to provide a flexible semiconductor device having excellent electrical characteristics and productivity.
- the gate oxide film and the insulating film 20 constituting the capacitor unit are formed using a high dielectric constant material, and the second insulating film 21 is formed using a low dielectric constant material. It is possible to use properly according to the function and purpose, etc., and it is possible to increase the capacitance of the capacitor portion incorporated in the semiconductor element or circuit while reducing the parasitic capacitance generated between the wirings more effectively. .
- FIGS. 5A to 5H are process cross-sectional views for explaining the manufacturing process of the flexible semiconductor device 400.
- FIG. This will be described below.
- a metal foil 10 is prepared.
- a 70 ⁇ m thick SUS foil can be used as the metal foil 10.
- the metal foil 10 is processed to form a convex portion for forming an interlayer connection via 10v that electrically connects the upper wiring pattern and the lower wiring pattern.
- This convex portion can be formed by, for example, forming a mask at a position where the convex portion is to be formed and etching the upper surface of the metal foil 10, and has the same thickness as the gate insulating film 20g to be formed later. It is formed to be slightly higher than the height or the thickness of the gate insulating film 20g.
- An appropriate etchant may be used according to the material of the metal foil 10 and the like. For example, in the case of silver foil or SUS foil, ferric chloride can be used.
- a mask is formed at a position where a projection for forming the gate electrode 10g is further formed, and the metal foil 10 is etched to form a projection for the gate electrode 10g.
- the mask for forming the convex portion for the interlayer connection via 10v is left without being removed, and the mask is used. Processing is performed so that the convex portion of the interlayer connection via 10v becomes high.
- the etchant an appropriate material may be used according to the material of the metal foil 10 as in the step (b).
- the insulating film 20 including the gate insulating film 20g is formed on the metal foil 10 on which the convex portions are formed in the step (b) and the step (c). At this time, the insulating film 20 is formed so that the surface of the interlayer connection via 10v is exposed.
- the insulating film 20 may be exposed by removing only the insulating film 20 on the surface of the interlayer connection via 10v using a laser after forming the insulating film 20 on the entire surface using a method, a spray method, or the like.
- a semiconductor layer 30 facing the gate electrode 10g is formed on the gate insulating film 20g.
- the source electrode 40s and the drain electrode 40d are formed so as to be in contact with the semiconductor layer 30, and a layer including the source electrode 40s and the drain electrode 40d is formed. At this time, it is electrically connected to the exposed surface of the interlayer connection via 10v.
- the sealing layer 50 is formed so as to cover the surface on which the semiconductor layer 30, the source electrode 40s, and the drain electrode 40d are formed.
- the metal foil 10 formed with the convex portions to be the gate electrode 10g and the interlayer connection via 10v is etched, so that the gate electrode 10g and the lower wiring pattern layer 10a are formed from the metal foil 10.
- an interlayer connection via 10v is formed.
- An appropriate etchant may be used according to the material of the metal foil 10.
- the flexible semiconductor device 400 according to the fourth embodiment can be constructed.
- the gate electrode and the lower wiring pattern and the source electrode or drain electrode layer can be electrically connected by a simple method.
- FIG. 6A is a cross-sectional view schematically showing a cross section of a flexible semiconductor device 500 mounted on an image display device (here, an organic EL display).
- the flexible semiconductor device 500 includes a plurality of transistor structures.
- the flexible semiconductor device 500 includes a semiconductor layer 30A, a gate insulating film 20Ag, a gate electrode 10Ag, a source electrode 40As, and a drain electrode 40Ad.
- the TFT transistor 500A includes the TFT transistor 500A configured, the semiconductor layer 30B, the gate insulating film 20Bg, the gate electrode 10Bg, the source electrode 40Bs, and the drain electrode 40Bd.
- the flexible semiconductor device 500 includes a switching TFT transistor 500A (hereinafter referred to as “Sw-Tr”) and a driving TFT transistor 500B (hereinafter referred to as “Dr-Tr”). It is comprised from these.
- the flexible semiconductor device 500 has a laminated structure, and the Dr-Tr 500B is laminated on the Sw-Tr 500A.
- the source electrode 40As and the drain electrode 40Ad of the Sw-Tr 500A are connected to the gate electrode 10Bg of the Dr-Tr 500B, the lower electrode layer 10Bc of the capacitor 80, and the Dr ⁇ by interlayer connection members 70, 71, 72 formed on the sealing layer 50A.
- the lower wiring pattern layer 10Ba formed in the Tr 500B is electrically connected.
- the flexible semiconductor device 500 includes one capacitor 80. That is, as shown in FIG. 6B, each pixel of the image display device is configured by combining two TFT transistors 500A and 500B and one capacitor 80.
- the gate electrode 10Ag of the Sw-Tr 500A is connected to the selection line 94, one of the source electrode 40As and the drain electrode 40Ad is connected to the data line 92, and the other is the Dr-Tr 500B. It is connected to the gate electrode 10Bg.
- One of the source electrode 10Bs and the drain electrode 10Bd of the Dr-Tr 500B is connected to the power supply line 96, and the other is connected to the display unit (here, an organic EL element).
- the capacitor 80 is connected between the source electrode 10Bs and the gate electrode 10Bg of the Dr-Tr 500B.
- the drive voltage is input from the data line 92, selected by the Sw-Tr 500A, and electric charge is accumulated in the capacitor 80. Then, a voltage generated by the electric charge is applied to the gate electrode 10Bg of the Dr-Tr 500B, and a drain current corresponding to the voltage is supplied to the display unit, so that the organic EL element emits light.
- a TFT for driving a display which is one of the important uses of a flexible semiconductor device, requires a capacitor that holds a capacitance in order to drive the element. In this way, by directly incorporating the capacitor 80 into the flexible semiconductor device, it is not necessary to separately provide a capacitor outside the flexible semiconductor device 500. Therefore, it is possible to realize a small and high-density image display device.
- the lower electrode layer 10Bc of the capacitor 80 is formed in the same plane as the gate electrode 10Bg of the Dr-Tr 500B, and is composed of a common metal layer 10B.
- the dielectric layer 20Bc of the capacitor 80 is formed in the same plane as the gate insulating film 20B of the Sw-Tr 500B, and is composed of a common insulating film 20B.
- a drive circuit (equivalent circuit) 90 having the structure shown in FIG. 6A is shown in FIG.
- the wiring 92 shown in FIG. 6B is a data line
- the wiring 94 is a selection line
- the wiring 96 is a power supply line.
- a flexible semiconductor device 500 is formed for each pixel of each image display device. Depending on the configuration of the display, not only two TFT elements may be provided for each pixel, but there may be more TFT elements. Therefore, the flexible semiconductor device 500 may be modified accordingly.
- FIG. 7 illustrates an example of a manufacturing process of the flexible semiconductor device 500 according to the fifth embodiment of the present invention with reference to FIGS. 7 (a) to (c). It should be noted that description of parts other than the matters specifically mentioned and overlapping with the first embodiment will be omitted.
- a TFT transistor 500B serving as a Dr-Tr is formed.
- the capacitor 80 is formed on the same surface side of the insulating film 20B.
- the formation method is such that when the metal foil 10B is formed with a convex portion as shown in FIG. 2B, the gate electrode 10Bg and the portion of the TFT element and the portion that becomes the lower electrode layer 10Bc of the capacitor 80 are formed as the convex portion. To do. Thereafter, when forming the insulating film 20B, a gate insulating film 20Bg and a capacitor dielectric layer 20Bc are formed.
- the sealing layer 50B is formed, and the metal layer 10B is processed, whereby the lower wiring pattern layer 10Ba, the gate electrode 10Bg, and the lower electrode layer of the capacitor 10Bc is formed.
- a sealing transistor 50A including a TFT transistor 500A to be an SW-Tr completed up to FIG. 2E and interlayer connection members 70, 71, 72 is prepared.
- the interlayer connection member for example, a paste via can be used.
- the interlayer connection members 70, 71, 72 are made of, for example, a conductive paste (paste via) filled in an opening that communicates the upper and lower surfaces using a sheet-like material for the sealing layer 50.
- a conductive paste for example, a mixture of an Ag plating coated copper powder and a resin composition containing an epoxy resin as a main component can be given.
- the TFT transistor 500A is pressure-bonded to the sealing layer 50A, thereby connecting the interlayer connection member 70 and the source electrode 40As, and the interlayer connection members 71 and 72 and the drain electrode 40Ad, respectively. To do.
- a method of applying pressure while heating with a roll laminate, a vacuum laminate, a hot press, or the like may be employed as the method of the above-described pressure bonding.
- an adhesive material for example, epoxy resin, acrylic resin, polyimide resin, or the like
- an uncured resin film, or the like can be used.
- a surface in which an adhesive epoxy resin is applied to the surface of a polyimide resin film having a thickness of 12.5 ⁇ m is prepared as the sealing layer 50A, and the semiconductor layer 30A, the source electrode 40As, and the drain electrode Ad of the TFT transistor 500A are formed. Bond together to integrate.
- the lower wiring pattern formed in the TFT transistor 500B so as to be connected to the interlayer connection members 70, 71, 72 of the sealing layer 50 on the surface of the sealing layer 50 opposite to the surface to which the TFT transistor 500A is pressure-bonded.
- the layer 10Ba, the gate electrode 10Bg, and the lower electrode layer 10Bc of the capacitor are pressure bonded.
- the TFT transistor 500B and the sealing layer 50 are laminated and integrated, and the gate electrode 10Bg of the TFT transistor 500B, the lower electrode layer 10Bc of the capacitor 80, and the lower wiring pattern layer 10Ba formed on the Dr-Tr 500B are electrically connected.
- the pressure bonding of the TFT element 300A and the pressure bonding of the TFT transistor 500B may be performed in the same process, or may be performed in different processes as necessary.
- the gate electrode 10Ag is formed by processing the metal layer 10A of the TFT transistor 500A. In this way, the flexible semiconductor device 500 according to the fifth embodiment shown in FIG. 6 can be manufactured.
- a structure in which a plurality of transistors are stacked is described.
- a plurality of transistors may be arranged in the same plane.
- more wirings can be accommodated in the same element area due to the effect of arranging the wirings three-dimensionally. . That is, a thick wiring having a larger cross-sectional area can be used if the number of wirings is the same, so that a voltage drop due to wiring resistance can be reduced and an etching process yield for wiring formation can be improved. .
- the present invention is not limited thereto, and a method of manufacturing in a form corresponding to a plurality of devices may be executed.
- a roll-to-roll manufacturing method can be used.
- the flexible semiconductor device according to the present invention is useful for electronic devices such as organic EL displays and electronic paper. Furthermore, it is useful not only for displays but also for applications such as mounting on communication devices such as RFID and electronic devices such as memory devices.
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Abstract
Description
ここで、TFT素子には主にa-Si(アモルファスシリコン)、p-Si(ポリシリコン)等の半導体を用いることができ、これらのSi半導体(必要に応じて金属膜も)を多層化し、ソース、ドレイン、ゲート電極を基板上に順次形成していくことでTFT素子が製造される。
すなわち、本発明に係るフレキシブル半導体装置は、半導体素子が形成された絶縁膜を備え、その絶縁膜の上面と下面にそれぞれ上部配線パターン層と下部配線パターン層を有してなるフレキシブル半導体装置であって、
前記半導体素子は、
前記絶縁膜の上面に形成された半導体層と、
前記半導体層と接するように前記絶縁膜の上面に形成されたソース電極とドレイン電極と、
前記半導体層に対向するように前記絶縁膜の下面に形成されたゲート電極と、を含んでなり、
前記ゲート電極の上面が前記下部配線パターン層の上面より前記半導体層側に突出しており、
前記絶縁膜において、前記ソース電極、前記ドレイン電極、前記上部配線パターン層及び前記下部配線パターン層と対向する絶縁膜の第1の膜厚が、前記ゲート電極と前記半導体層間の絶縁膜の第2の膜厚より厚いことを特徴とする。
以上のように構成された本発明に係るフレキシブル半導体装置は、前記ソース電極、前記ドレイン電極、前記上部配線パターン層及び前記下部配線パターン層と対向する絶縁膜の第1の膜厚が、前記ゲート電極と前記半導体層間の絶縁膜の第2の膜厚より厚いので、半導体素子に組み込まれるキャパシタ部では、容量を大きく確保しつつ、配線を多層化した場合であっても、配線間に生じる寄生容量を小さくできる。
前記金属として、アルミ、銀、ニッケル、鉄、銅、またはそれらの何れかを成分とする合金箔から選ばれたものであってもよい。
このようにすると、前記絶縁膜と前記下部配線パターンとの間の密着強度を高く保ちつつ、ゲート絶縁膜として機能するゲート電極上の絶縁膜の膜厚バラツキを小さくでき、電気的特性が優れたゲート絶縁膜を形成することができる。
この場合、好ましくは前記ゲート電極の上面の表面粗さを、Ra値100nm以下、より好ましくはRa値50nm以下とする。また、前記下部配線パターンの上面の表面粗さを、好ましくはRa値500nm以上、より好ましくはRa値1μm以上とする。これにより、前記絶縁膜と前記下部配線パターンとの間の密着強度をより高く保つことができ、かつゲート電極上の絶縁膜の電気的特性や膜厚のバラツキをよりいっそう小さくできる。
また、前記封止層が、樹脂材料からなっていてもよいし、フィルム状の芯材と、前記芯材の両面にそれぞれ積層された樹脂層とから構成されていてもよい。
また、前記上部電極と前記下部電極間の前記絶縁膜の第3の膜厚が、前記第1の膜厚より薄いことが好ましく、前記第3の膜厚が、前記第1の膜厚より1μm以上薄いことがさらに好ましい。
また、その際、前記2層の絶縁膜を層間絶縁膜を介して接合して、前記2層の絶縁膜にそれぞれ形成された半導体素子は、前記層間絶縁膜を貫通して設けられた層間接続部材を介して接続されていることが好ましい。
さらに、前記層間絶縁膜は、前記2層の絶縁膜に設けられた一方の半導体素子を被覆する封止層として形成されていることが好ましい。
絶縁膜の下面にゲート電極とそのゲート電極に接続された下部配線パターン層が形成され、前記絶縁膜の上面にゲート電極と対向する半導体層と該半導体層に接続されたソース電極とドレイン電極とが形成されてなるフレキシブル半導体装置の製造方法であって、
金属箔の一方の面に1又は2以上の凸部を形成する下部電極配線作製工程と、
前記凸部を形成した前記一方の面に、前記凸部上の膜厚が該凸部を除く凹部上の膜厚より薄くなるように前記絶縁膜を形成する絶縁膜形成工程と、
前記凸部の少なくとも1つに対向するように前記半導体層を前記絶縁膜上に形成する半導体層形成工程と、
を含むことを特徴とする。
このようにすると、ゲート電極に加え、例えば、前記下部配線パターン層と前記ソース電極若しくは前記ドレイン電極とを接続する層間接続ビアを形成することができる。
前記金属箔の一方の面に絶縁膜材料を溶媒に溶解して塗工することにより塗布膜を形成する工程と、
前記塗布膜から溶媒を除去する工程と、を含んでいてもよい。
第1絶縁膜を形成したのち、前記第1絶縁膜と同一又は異なる絶縁膜材からなる第2絶縁膜を前記凹部に形成して、前記第1絶縁膜と前記第2絶縁膜とを含んでなる前記絶縁膜を形成するようにしてもよい。
前記絶縁膜の上に半導体材料を堆積する工程と、
前記堆積した半導体材料を加熱処理して前記半導体材料を結晶化する結晶化工程と、
を含んでいてもよい。
前記第1のフレキシブル半導体装置の下部配線パターンと、第2のフレキシブル半導体装置の上部配線パターンとが樹脂シートを介して対向させて圧着することにより、前記第1と第2のフレキシブル半導体装置とを接合するようにしてもよい。
また、前記樹脂シートに、一端が第1のフレキシブル半導体装置のゲート電極又は下部配線パターンに接続され、他端が第1のフレキシブル半導体装置の上部配線パターンに接続されるビアを形成することが好ましい。
また、本発明のフレキシブル半導体装置の製造方法によれば、前記本発明のフレキシブル半導体装置の製造が可能な製造方法が提供される。
また、本発明のフレキシブル半導体装置の製造方法は、金属箔を支持基材として使うことにより簡易なプロセスで凹凸部を形成して絶縁膜の膜厚の調整が可能になるので、簡略化した製造工程でフレキシブル半導体装置を製造することができる。
さらに、金属箔を支持基板として用いていることより支持基板として樹脂基板を使用する形態より高温での形成が必要な特性に優れた半導体材料や絶縁膜材料を用いることも可能である。
したがって、本発明に係る製造方法によれば、高性能で、かつ、生産性に優れたフレキシブル半導体装置を提供することができる。
図1(a)及び(b)を参照しながら、本発明の実施形態1に係るフレキシブル半導体装置100について説明する。
図1(b)は、フレキシブル半導体装置100の上面模式図であり、図1(a)は、図1(b)のIa-Ia断面を示す断面模式図である。
フレキシブル半導体装置100は、絶縁膜20と、絶縁膜20上に形成されたソース電極40s、及びドレイン電極40d、半導体層30、絶縁膜20でもゲート絶縁膜として機能するゲート絶縁膜20g、ゲート電極10gからなるTFT構造体と、ゲート電極10gより引き出されて配線部として機能する下部配線パターン層10aとを含んで構成されている。
また、金属箔10として、例えば、Ra値(算術平均粗さ)が100nm以下の表面粗さの小さい金属箔を用いることが好ましい。表面粗さの小さい金属箔10を使用すると、凸部上面の表面粗さを小さくでき、凸部上面に膜厚のバラツキが小さい絶縁膜を薄く形成することが可能になる。これによって、耐電圧の高いゲート絶縁膜20gを形成することができる。
一方、エッチングにより凸部を形成すると、表面粗さの小さい金属箔を用いた場合であっても、凸部の上面以外のエッチング面(下部配線パターンの上面)については凸部の上面に比較して表面粗さを大きくでき、絶縁膜20と下部配線パターン10aとの間の密着強度を高くすることができる。下部配線パターンの上面の表面粗さは、エッチングの条件の調整等によりRa値(算術平均粗さ)500nm以上にすることが好ましい。
しかしながら、本発明において、絶縁膜20の形成方法としては、その他の一般的な薄膜形成法を使用することができ、その代表例として真空蒸着法、レーザーアブレーション法、スパッタリング法、CVD法(例えばプラズマCVD法)等を挙げることができる。レーザーアブレーション法では、無機化合物の組成変化の少ない膜形成が可能である。CVD法では、無機絶縁膜の成膜が容易で、多成分膜の合成が可能となり、高誘電率膜を形成できる点で好ましい。
また、本実施形態1の製造方法によれば、金属箔10にゲート電極10gとなる凸部を形成してその凸部によりその上の絶縁膜が薄くなるようにしているので、絶縁膜の表面を平坦にすることが可能であり、その平坦な表面に半導体層30やソース電極及びドレイン電極を精度良く形成することができる。
さらに、半導体素子や回路内に組み込まれるキャパシタ部の誘電体層を絶縁膜とは異なる工程で形成したり高誘電率な材料を使用することなく、必要な容量のキャパシタ部を形成することが可能になる。
図3に、本発明の一実施形態に係るフレキシブル半導体装置200の構成を示す。この実施形態2では、異なる金属材料が2層以上の構造を有する多層金属箔を用いる点において、上述した実施形態1とは異なる。すなわち、用意する金属箔が多層構造を有しておりゲート電極10gと下部配線パターン層10aとが異なる金属材料により形成されている。
図4に、本発明の一実施形態に係るフレキシブル半導体装置300の構成を示す。この実施形態3では、金属箔10に形成した凹部において絶縁膜20とともに第2の絶縁膜21が形成されている点において、上述した実施形態1とは異なる。その製造プロセスの一例を図4(a)~(h)を参照しつつ説明する。なお、特に言及している事項以外の事柄であって実施形態1と重複する部分についての説明は省略する。
また、本実施形態3の製造方法では、例えば、ゲート酸化膜やキャパシタ部を構成する絶縁膜20を高誘電率の材料により形成し、第2絶縁膜21として低誘電率の材料を用いて形成するなど、機能と目的に応じて使い分けることが可能であり、より効果的に配線間に発生する寄生容量を低減しつつ、半導体素子や回路内に組み込まれるキャパシタ部の容量を大きくすることができる。
次に、図5(a)~(h)を参照しながら、本実施形態4のフレキシブル半導体装置400の製造方法について説明する。図5(a)~(h)は、フレキシブル半導体装置400の製造工程を説明するための工程断面図である。以下、これについて説明する。
次に、図5(b)に示すように、金属箔10を加工することによって、上部配線パターンと下部配線パターンを電気的に接続する層間接続ビア10vを構成するための凸部を形成する。この凸部は、例えば、凸部を形成する位置にマスクを形成して金属箔10の上面をエッチングすることにより形成することが可能であり、後で形成されるゲート絶縁膜20gの厚さと同じ高さ又はゲート絶縁膜20gの厚さより若干高くなるように形成される。エッチャントとしては、金属箔10の材料などに応じて適当なものを使用すればよい。例えば銀箔やSUS箔の場合、塩化第二鉄を用いることができる。
次に、図5(f)に示すように、半導体層30に接触するようにソース電極40s、ドレイン電極40dを形成し、それらソース電極40s、ドレイン電極40dを含む層を形成する。このとき露出した層間接続ビア10v表面と電気的に接続される。
次に、図5(h)に示すように、ゲート電極10gや層間接続ビア10vとなる凸部を形成した金属箔10をエッチングすることによって、金属箔10からゲート電極10g、下部配線パターン層10aおよび層間接続ビア10vを形成する。エッチャントとしては、金属箔10の材料に応じて適当なものを使用すればよい。
続いて、図6(a)および(b)を参照しつつ、本実施形態に係るフレキシブル半導体装置を画像表示装置に搭載する場合について説明する。図6(a)は、画像表示装置(ここでは有機ELディスプレイ)に搭載されるフレキシブル半導体装置500の断面を模式的に示した断面図である。フレキシブル半導体装置500は、トランジスタ構造体を複数有し、図6(a)に示した例では、半導体層30Aとゲート絶縁膜20Agと、ゲート電極10Agと、ソース電極40Asと、ドレイン電極40Adとから構成されたTFTトランジスタ500Aと、半導体層30Bとゲート絶縁膜20Bgと、ゲート電極10Bgと、ソース電極40Bsと、ドレイン電極40Bdとから構成されたTFTトランジスタ500Bを有する。
10a、10Ba、62a 下部配線パターン層
10g、10Ag、10Bg、61g ゲート電極
20、20A、20B 絶縁膜
20g、20Ag、20Bg ゲート絶縁膜
20Bc 誘電体層
21 第2の絶縁膜
30、30A、30B 半導体層
40s、40As、40Bs ソース電極
40d、40Ad、40Bd ドレイン電極
50、50A、50B 封止層
60 多層金属箔
61 第1金属層
62 第2金属層
70、71、72 層間接続部材
80 コンデンサ
10Bc 下部電極層
100、200、300、400、500、500A、500B フレキシブル半導体装置
500A、500B TFTトランジスタ
Claims (33)
- 半導体素子が形成された絶縁膜を備え、その絶縁膜の上面と下面にそれぞれ上部配線パターン層と下部配線パターン層を有してなるフレキシブル半導体装置であって、
前記半導体素子は、
前記絶縁膜の上面に形成された半導体層と、
前記半導体層と接するように前記絶縁膜の上面に形成されたソース電極とドレイン電極と、
前記半導体層に対向するように前記絶縁膜の下面に形成されたゲート電極と、を含んでなり、
前記ゲート電極の上面が前記下部配線パターン層の上面より前記半導体層側に突出しており、
前記絶縁膜において、前記ソース電極、前記ドレイン電極、前記上部配線パターン層及び前記下部配線パターン層と対向する絶縁膜の第1の膜厚が、前記ゲート電極と前記半導体層間の絶縁膜の第2の膜厚より厚いことを特徴とするフレキシブル半導体装置。 - 前記絶縁膜において、前記第1の膜厚が、前記第2の膜厚より1μm以上厚い請求項1記載のフレキシブル半導体装置。
- 前記ゲート電極と前記下部配線パターン層が、同種の金属からなることを特徴とする、請求1又は2に記載のフレキシブル半導体装置。
- 前記金属が、アルミ、銀、ニッケル、鉄、銅、またはそれらの何れかを成分とする合金箔から選ばれたものである請求項3に記載のフレキシブル半導体装置。
- 前記絶縁膜に接する前記ゲート電極の上面の表面粗さが、前記絶縁膜に接する前記下部配線パターンの上面の表面粗さより小さい請求項1~4のうちのいずれか1つに記載のフレキシブル半導体装置。
- 前記ゲート電極の上面の表面粗さが、Ra値100nm以下である請求項1~5のうちのいずれか1つに記載のフレキシブル半導体装置。
- 前記下部配線パターンの上面の表面粗さが、Ra値500nm以上である請求項1~6のうちのいずれか1つに記載のフレキシブル半導体装置。
- 前記半導体層の上には、前記半導体層を被覆する絶縁材料からなる封止層が形成されている請求項1~7のうちのいずれか1つに記載のフレキシブル半導体装置。
- 前記封止層が、樹脂材料からなる請求項8に記載のフレキシブル半導体装置。
- 前記封止層が、フィルム状の芯材と、前記芯材の両面にそれぞれ積層された樹脂層とから構成されている樹脂シートからなる請求項9に記載のフレキシブル半導体装置。
- 前記ソース電極と前記下部電極間又は前記ドレイン電極と前記下部電極間を電気的に接続する層間接続ビアをさらに有し、該層間接続ビアと前記ゲート電極と前記下部配線パターン層とが同種の金属からなる請求項1~10のうちのいずれか1つに記載のフレキシブル半導体装置。
- 前記絶縁膜の上面に形成された上部電極と該上部電極に対向して前記絶縁膜の下面に形成された下部電極とによってコンデンサがさらに形成された請求項1~11のうちのいずれか1つに記載のフレキシブル半導体装置。
- 前記上部電極と前記下部電極間の前記絶縁膜の第3の膜厚が、前記第1の膜厚より薄い請求項12に記載のフレキシブル半導体装置。
- 前記第3の膜厚が、前記第1の膜厚より1μm以上薄い請求項12に記載のフレキシブル半導体装置。
- 前記フレキシブル半導体装置は、前記絶縁膜を2層有し、該絶縁膜にそれぞれ前記半導体素子が設けられている請求項1~14のうちのいずれか1つに記載のフレキシブル半導体装置。
- 前記2層の絶縁膜は、層間絶縁膜を介して接合されており、前記2層の絶縁膜にそれぞれ形成された半導体素子は、前記層間絶縁膜を貫通して設けられた層間接続部材を介して接続されている請求項15に記載のフレキシブル半導体装置。
- 前記層間絶縁膜は、前記2層の絶縁膜に設けられた一方の半導体素子を被覆する封止層として形成された請求項16に記載のフレキシブル半導体装置。
- 絶縁膜の下面にゲート電極とそのゲート電極に接続された下部配線パターン層が形成され、前記絶縁膜の上面にゲート電極と対向する半導体層と該半導体層に接続されたソース電極とドレイン電極とが形成されてなるフレキシブル半導体装置の製造方法であって、
金属箔の一方の面に1又は2以上の凸部を形成する下部電極配線作製工程と、
前記凸部を形成した前記一方の面に、前記凸部上の膜厚が該凸部を除く凹部上の膜厚より薄くなるように前記絶縁膜を形成する絶縁膜形成工程と、
前記凸部の少なくとも1つに対向するように前記半導体層を前記絶縁膜上に形成する半導体層形成工程と、
を含むことを特徴とするフレキシブル半導体装置の製造方法。 - 前記下部電極配線作製工程において、前記凸部をエッチングによって形成する請求項18に記載のフレキシブル半導体装置の製造方法。
- 前記金属箔の表面に、前記金属箔と同種の金属材料、もしくは異なる金属材料を積層することによって前記凸部を形成する請求項18に記載のフレキシブル半導体装置の製造方法。
- 前記凸部の高さが1μm以上になるように前記凸部を形成する請求項18~20のうちのいずれか1つに記載のフレキシブル半導体装置の製造方法。
- 前記凸部形成工程において、高さの異なる凸部を形成する請求項18~21のうちのいずれか1つに記載のフレキシブル半導体装置の製造方法。
- 前記絶縁膜の上面に、前記ソース電極、前記ドレイン電極及び前記ソース電極又は前記ドレイン電極に接続された上部配線パターンを形成する上部電極配線作製工程を含む請求項18~22のうちのいずれか1つに記載のフレキシブル半導体装置の製造方法。
- 前記上部電極配線作製工程において、前記上部配線パターンに接続された上部電極を前記凸部のうちの少なくとも1つに対向するように形成する請求項18~22のうちのいずれか1つに記載のフレキシブル半導体装置の製造方法。
- 前記上部電極配線作製工程において、
導電性材料を溶媒に溶解した液体材料を塗布することにより電極配線パターンを形成し、電極配線パターンから前記溶媒を除去することを含む請求項23又は24に記載のフレキシブル半導体装置の製造方法。 - 前記絶縁膜形成工程が、
前記金属箔の一方の面に絶縁膜材料を溶媒に溶解して塗工することにより塗布膜を形成する工程と、
前記塗布膜から溶媒を除去する工程と、
を含む請求項18~25のうちのいずれか1つに記載のフレキシブル半導体装置の製造方法。 - 前記絶縁膜形成工程において、
第1絶縁膜を形成したのち、前記第1絶縁膜と同一又は異なる絶縁膜材からなる第2絶縁膜を前記凹部に形成して、前記第1絶縁膜と前記第2絶縁膜とを含んでなる前記絶縁膜を形成する請求項18~26のうちのいずれか1つに記載のフレキシブル半導体装置の製造方法。 - 前記半導体層形成工程は、
前記絶縁膜の上に半導体材料を堆積する工程と、
前記堆積した半導体材料を加熱処理して前記半導体材料を結晶化する結晶化工程とを含む請求項18~27のうちのいずれか1つに記載のフレキシブル半導体装置の製造方法。 - レーザ照射によって前記加熱処理を実行する請求項28に記載のフレキシブル半導体装置の製造方法。
- 400℃以上の加熱処理を含む請求項18~29のうちのいずれか1つに記載のフレキシブル半導体装置の製造方法。
- 前記絶縁膜の上面に、樹脂シートを圧着することにより、前記ソース電極、前記ドレイン電極及び前記半導体層を前記絶縁膜と前記樹脂シートとの間に埋設して封止する封止工程を含む請求項18~30のうちのいずれか1つに記載のフレキシブル半導体装置の製造方法。
- 請求項18~30のうちのいずれか1つに記載のフレキシブル半導体装置の製造方法によって、2つの第1と第2のフレキシブル半導体装置を作製して、
前記第1のフレキシブル半導体装置の下部配線パターンと、第2のフレキシブル半導体装置の上部配線パターンとが樹脂シートを介して対向させて圧着することにより、前記第1と第2のフレキシブル半導体装置とを接合することを含むフレキシブル半導体装置の製造方法。 - 前記樹脂シートに、一端が第1のフレキシブル半導体装置のゲート電極又は下部配線パターンに接続され、他端が第1のフレキシブル半導体装置の上部配線パターンに接続されるビアを形成することを含む請求項32に記載のフレキシブル半導体装置の製造方法。
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JP2013165132A (ja) * | 2012-02-09 | 2013-08-22 | Semiconductor Energy Lab Co Ltd | 半導体装置 |
US9755084B2 (en) | 2012-02-09 | 2017-09-05 | Semiconductor Energy Laboratory Co., Ltd. | Multi-level stacked transistor device including capacitor and different semiconductor materials |
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Publication number | Publication date |
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JP5719992B2 (ja) | 2015-05-20 |
US8525178B2 (en) | 2013-09-03 |
CN102576678B (zh) | 2015-11-25 |
US20120181543A1 (en) | 2012-07-19 |
CN102576678A (zh) | 2012-07-11 |
JPWO2011142081A1 (ja) | 2013-07-22 |
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