WO2010001549A1 - 電子回路装置 - Google Patents
電子回路装置 Download PDFInfo
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- WO2010001549A1 WO2010001549A1 PCT/JP2009/002885 JP2009002885W WO2010001549A1 WO 2010001549 A1 WO2010001549 A1 WO 2010001549A1 JP 2009002885 W JP2009002885 W JP 2009002885W WO 2010001549 A1 WO2010001549 A1 WO 2010001549A1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
Definitions
- a plurality of components that realize the same function are cascaded in the vertical direction or the horizontal direction to constitute an electronic circuit of a predetermined scale, and a unique identification number is assigned to each component that is cascaded.
- the present invention relates to an electronic circuit device capable of selecting a desired component and instructing execution of a function without assignment.
- Patent Document 1 If the invention shown in Japanese Patent Application Laid-Open No. 2005-228981 (Patent Document 1) is used, a plurality of chips of the same type are stacked, power is supplied to each chip by conventional wire bonding, and data communication between chips is performed by inductive coupling. Can do.
- a method of selecting and operating a desired chip from among the stacked chips information on the stack position of each chip is assigned as a unique chip identification number to each chip, a chip selection address is sent to all chips, A method of selecting and specifying a chip by comparing a chip selection address and a chip identification number with the chip is known. For example, if each chip has a unique 8-bit identification number, 256 chips can be distinguished and selected.
- the chip identification number can be embedded in the chip manufacturing process. For example, in the case of a flash memory, a chip identification number may be written in a specific area of the flash memory at the stage of testing each chip and selecting non-defective products. Alternatively, in the case of a DRAM, the chip identification number can be written by cutting the fuse with a laser. In the DRAM, if each chip is tested and a defective bit is found, the defective bit string can be replaced with a spare bit string by irradiating a laser to cut the fuse of the redundant circuit.
- the chips are completely the same, information on the order of stacking can be given to the chip by wire bonding when stacking.
- the first chip is (GND, GND)
- the second chip is (GND, VDD)
- the third chip is (VDD, GND)
- the fourth chip When a potential of (VDD, VDD) is given to, it is possible to recognize in what order the chips are stacked.
- the cost of stacked mounting becomes high, or stacked mounting becomes difficult. Therefore, the following inventions have been made in order to assign a unique chip identification number to each chip, instead of embedding a chip identification number in the manufacturing process or giving a chip identification number by wire bonding at the time of mounting.
- Patent Document 8 In the case of the invention disclosed in Japanese Patent Application Laid-Open No. 2003-110086 (Patent Document 8), a unique chip identification number is generated using manufacturing variations for each semiconductor chip such as charging time for parasitic capacitance. It is not always possible to obtain a different chip control number.
- Patent Document 9 the chips are stacked and connected in cascade, so that the arithmetic circuit mounted on each chip generates a chip identification number. ing.
- an increment operation circuit that generates a 3-bit output value (S0, S1, S2) obtained by adding 1 to a 3-bit input value (A0, A1, A2) is installed in each chip, and is arranged according to the stacking order of the chips. Increment operation circuits are connected in cascade, and a connection path is formed so that the operation output (S0, S1, S2) of the previous stage becomes the operation input (A0, A1, A2) of the subsequent stage. A number is assigned. Further, a comparator for comparing a chip selection address commonly connected to all the chips with a chip identification number of each chip is provided, and a chip selection signal is output when a match is detected.
- the upper limit of the number of stacked chips is determined from the number of bits of the arithmetic unit prepared in advance, it is not possible to stack more chips. For example, in the above example, since it is 3 bits, a maximum of 8 chips can be stacked. In order to stack more chips, it is necessary to redesign the circuit. Alternatively, in order to ensure a large upper limit of the number of stacked chips in advance, the number of bits of the arithmetic circuit must be increased more than necessary, resulting in high calculation and communication costs. Further, in both inventions of Japanese Patent Application Laid-Open No. 2003-110086 (Patent Document 8) and Japanese Patent Application Laid-Open No.
- a chip selection address is sent to all chips and compared with the chip identification number of each chip.
- a common connection path must be formed for all the chips.
- the distance that can be connected is about the diameter of the coil. Therefore, in order to form a common connection path for all the chips, a coil having a diameter corresponding to the distance in the thickness direction of the chips when all the chips are stacked and mounted is required.
- the chip thickness is 50 ⁇ m, when 64 chips are stacked, the thickness becomes 3 mm or more.
- a coil having a diameter of 3 mm or more is required, and it is expensive to integrate this into a chip of about 10 mm.
- the present invention constitutes a device by laminating electronic circuit elements such as a plurality of semiconductor chips or devices classified into the same type or two to three types in any number of vertical or horizontal directions, An object of the present invention is to provide a stacked device capable of selecting and communicating with a desired electronic circuit board.
- each constituent element is a sequential logic circuit, stacked constituent elements in the previous stage, and constituent elements in the subsequent stage.
- the sequential logic circuit of each component determines the next internal state based on the current internal state of the component and the control signal received from the previous component.
- Each component has a configuration for determining the processing content of the component itself based on the internal state determined by the sequential logic circuit and executing the processing.
- the present invention makes it possible to configure an electronic circuit device having an arbitrary capability by stacking an arbitrary number of components having the same function.
- the configuration of the present invention eliminates the need to assign an identification number to each component. Therefore, when changing the capability of the entire apparatus by adding or deleting the components, it is not necessary to redesign the components and can be realized at low cost. In addition, it is not necessary to transmit information for selection to all the stacked components, and driving with low power is possible.
- (a) is a diagram showing a first embodiment of the present invention
- (b) is a detailed view of a memory chip of the first embodiment.
- (a) is a schematic diagram of a transmission / reception circuit using inductive coupling
- (b) is a detailed view thereof
- (c) and (e) are diagrams showing configuration examples of a transmission coil and a reception coil
- (a) is a diagram showing a first example of stacking components by inductive coupling
- (b) is a diagram showing a second example of stacking components by inductive coupling State transition diagram of the first embodiment
- stacking of the component by 3rd Example (a) is a figure which shows the example of lamination
- (b) is a figure which shows the detail of the component by 4th Example
- FIG. 1 is a diagram showing a first embodiment of the present invention, in which an arbitrary number of memory chips having a predetermined memory capacity are stacked to constitute a memory circuit device having a large capacity.
- a control chip which is a control element for controlling each memory chip, is stacked in the front row of the stacked memory chips.
- inductive coupling is used as a communication means between the control chip and the memory chip.
- FIG. 1A is a diagram showing the overall configuration of the embodiment, in which n memory chips having the same function (memory chip 1 to memory chip n) are stacked, and a control chip 100 is stacked in the front row of the memory chips. Has been.
- communication circuits 111 to 113 In the memory chip, communication circuits 111 to 113, a memory cell of a predetermined capacity not shown, and a read / write control circuit are integrated.
- a transmission / reception circuit is provided in the communication circuit. In this embodiment, communication is performed by inductive coupling, and the communication distance can be designed to an arbitrary value.
- the reception circuit in the transmission / reception circuit of the memory chip m receives the signal from the memory chip my and passes it to the control circuit in the memory chip m.
- the transmission circuit of the memory chip m transmits the data of the control circuit to the memory chip m + x.
- the transmission / reception circuit can be configured to receive and transmit signals from the front components and transmit to the rear components, and to transmit and receive signals from the rear components and transmit to the front components. It is. Therefore, although the above “x” and “y” can be positive or negative integers, hereinafter, “x” and “y” are both assumed to be 1.
- a reset signal 103 is output in parallel from the control chip 100 to each memory chip.
- Each memory chip that has received the reset signal 103 initializes a communication circuit in the memory chip.
- the data input / output unit 104 of the control chip 100 is inductively coupled to the communication circuit 111 of the memory chip 1.
- the communication circuit 111 of the memory chip 1 is inductively coupled to the communication circuit 112 of the memory chip 2 stacked in the subsequent stage.
- the memory chip m is inductively coupled to the communication circuit of the memory chip m ⁇ 1 stacked in the previous stage and the communication circuit of the memory chip m + 1 stacked in the subsequent stage.
- the last-stage memory chip n is inductively coupled only with the communication circuit of the memory chip n-1 stacked in the previous stage.
- the control chip 100 When accessing a memory cell integrated in a specific memory chip m among n memory chips, the control chip 100 outputs control data for selecting the memory chip m from the data input / output unit 104. The memory chip m is set to the selected state. Next, the control chip 100 outputs an address of a memory cell to be accessed and a write / read control signal, and executes data write / read on the address.
- FIG. 1B is a diagram showing a configuration of the memory chip m.
- the communication circuit 120 includes a transmission / reception circuit 122 and a sequential logic circuit 135.
- the transmission / reception circuit 122 controls the entire communication circuit 120, the reception circuit unit 123 inductively coupled to the transmission / reception circuit of the preceding memory chip m-1, the transmission circuit unit 127 inductively coupled to the transmission / reception circuit of the subsequent memory chip m + 1, and the communication circuit 120.
- a control circuit 125 is included.
- the sequential logic circuit 135 includes a flip-flop 134 that stores 3-bit state information [S1, S2, S3] 133 representing the operation state of the memory chip, and a combinational logic circuit 136.
- the combinational logic circuit 136 is based on the value of the flip-flop 134 and the 2-bit control information (D1, D2) 131 sent from the transmission / reception circuit 122 from the previous memory chip m-1 (control chip 100 in the memory chip 1). The operation state to be taken next by the memory chip m is determined, and the corresponding state information is stored in the flip-flop 134.
- the control circuit 125 determines the operation of the memory chip m based on the state information [S1, S2, S3] 133 and controls the entire memory chip m.
- the control circuit 125 has a signal line 137 for transmitting read / write control signals and address information to the memory cells in the memory chip, and for transferring read / write data.
- FIG. 2A is a circuit example of the transmission / reception circuit 122 of FIG. 1, and FIG. 2B is a detailed diagram of the transmission / reception circuit 122.
- the transmission / reception circuit 122 includes a reception circuit unit 123, a transmission circuit unit 127, and a control circuit 125.
- the reception circuit unit 123 includes a reception coil 141 and a receiver 142
- the transmission circuit unit 127 includes a transmission coil 145 and a transmitter 146.
- the control circuit 125 controls the receiver 142, the transmitter 146, and the memory cell based on the state information 133 shown in FIG. 1, and controls data exchange by the reception circuit unit 123 and the transmission circuit unit 127.
- the data received via the receiver circuit unit 123 is transmitted to an internal circuit such as a memory cell. Similarly, the received data is transferred to the next memory chip via the transmission circuit unit 127 ( There is an operation of relaying, and an operation of transmitting data of an internal circuit such as a memory cell to the next-stage memory chip (or control chip 100) via the transmission circuit unit 127.
- FIG. 2B shows a circuit example of the receiver 142 and the transmitter 146.
- the receiver 142 amplifies the voltage (V R ) generated in the receiving coil 141 by inductive coupling, and outputs it to the control circuit 125 as [Rxdata], and ON / OFF between the receiving coil 141 and the amplifying circuit 143 It is comprised from the gate circuit 144 which controls.
- the gate circuit 144 is controlled by a [disable] signal from the control circuit 125.
- the reception circuit unit 123 is in a reception state
- the amplification circuit 143 amplifies the signal received by the reception coil 141 and passes it to the control circuit.
- the gate circuit 144 When the [disable] signal is output from the control circuit 125, the gate circuit 144 is turned off, the amplifier circuit 143 and the reception coil 141 are separated, and the reception operation is disabled.
- the transmitter 146 controls the direction of the pulse current (I T ) flowing through the transmission coil 145 in response to “1” and “0” of the data signal [Txdata] output from the control circuit 125, and Inductive coupling corresponding to the output signal is generated between them.
- I T pulse current
- FIG. 2C to FIG. 2E are diagrams showing examples of arrangement of the reception coil and the transmission coil.
- FIG. 2C shows a configuration in which the reception coil 141 and the transmission coil 145 are provided separately. By adopting this configuration, the installation positions of the reception coil 141 and the transmission coil 145 can be arbitrarily determined, and interference between the coils can be reduced.
- FIG. 2D shows a configuration in which a single coil 147 serves as both a transmission coil and a reception coil, and the coil is used by switching between transmission and reception.
- the coil 148 in FIG. 2 (e) has a configuration in which a transmission coil and a reception coil are arranged coaxially.
- the transmission circuit 146 is driven and the reception circuit 142 is set in the dormant state during transmission, and the reception circuit 142 is driven and the transmission circuit 146 is set in the dormant state during reception. Prevents mutual interference.
- FIG. 3 is a diagram showing data exchange between five stacked memory chips.
- FIG. 3A shows an example of a three-coil type channel in which one coil is constituted by three coils
- FIG. 3B shows one or the coaxial shown in FIG. 2D or FIG. It is an example of the channel of 1 coil type comprised by the coil. Note that components other than the coil, such as a receiver, a transmitter, and a control circuit, are omitted.
- the interval between the stacked chips is shorter than the distance at which the transmission coil and the reception coil are inductively coupled. In the same figure, the intervals are 150 ⁇ m.
- the three-coil channel shown in FIG. 3 (a) is composed of one transmitting coil and two receiving coils, one of the two receiving coils is set in the receiving state, and the other receiving coil is in the resting state.
- Set to The coil A of the chip 151 is a transmission coil
- the coil B is a reception coil set in a pause state
- the coil C is a reception coil set in a reception state.
- the coil A of the chip 152 is a receiving coil set in the receiving state
- the coil B is a transmitting coil
- the coil C is a receiving coil set in the resting state.
- the control circuit of the chip 151 drives the transmission coil A via the transmitter
- the reception coil A set to the reception state of the chip 152 detects a signal by inductive coupling, and the signal received by the control circuit of the chip 152 ( Rxdata).
- Rxdata the signal received by the control circuit of the chip 152
- the control circuit of the chip 152 drives the transmission coil B of the chip 152 based on the signal to be transmitted.
- the inductive coupling by the transmission coil B reaches the reception coil B of the chip 151 and the reception coil B of the chip 153. Since the receiving coil B of the chip 151 is set in a resting state, no signal is detected.
- the receiving coil B of the chip 153 is set to the receiving state, the signal is detected and passed to the control unit of the chip 153.
- data is transmitted from the chip 152 to the chip 153.
- data is transmitted from the transmission coil C of the chip 153 to the reception coil C set to the reception state of the chip 154, and further, the reception state of the chip 155 is set from the transmission coil A of the chip 154.
- Data is transmitted to the receiving coil A.
- the control chip 100 in FIG. 1 can transmit data to the stacked memory chips 1 to n.
- data transmission can be performed in the direction from the chip 155 to the chip 151 by changing the setting of each receiving coil constituting the channel. For example, by setting the receiving coil B of the chip 151 to the operating state and the receiving coil B of the chip 153 to the inactive state, the inductive coupling by the transmitting coil B of the chip 152 is detected by the receiving coil B of the chip 151, and the data is To the chip 151. With this configuration, the memory chips 1 to n in FIG. 1 can transmit data to the control chip 100.
- FIG. 3B shows an example in which data transmission / reception between chips is performed using one or a single-coil channel constituted by a coaxial coil.
- D in FIG. 3 (b) is a one-coil channel, and the transmission coil and the reception coil shown in FIG. 2 (d) are combined, or the transmission coil and the reception coil shown in FIG. 2 (e) are coaxial.
- Data is transmitted and received between chips by a transmission / reception circuit in the form of a coil.
- the coil D of the chip 162 when data is transmitted from the chip 162 to the chip 163, the coil D of the chip 162 is set to the transmission state, the coil D of the chip 161 is in the pause state, and the coil D of the chip 163 is in the reception state. Set.
- the coil D of the chip 162 When the coil D of the chip 162 is driven by the transmission data, inductive coupling occurs between the coil D of the chip 161 and the coil D of the chip 163. Since the coil D of the chip 161 is set to the dormant state, the chip 161 does not receive the data of the chip 162. On the other hand, the coil D of the chip 163 is set to the receiving state, and receives data from the chip 162 by inductive coupling. Therefore, data can be transmitted from the chip 162 to the chip 163 by setting the coil D of the chip 161 to the resting state and setting the coil D of the chip 163 to the receiving state.
- data can be transmitted from the chip 162 to the chip 161 by setting the coil D of the chip 163 to the resting state and the coil D of the chip 161 to the receiving state.
- the coil structure of each chip becomes the same, and all the stacked chips can have the same function and the same structure.
- the configuration shown in FIG. 1 is a stack of a plurality of memory chips.
- the control chip 100 selects a memory chip for writing / reading data, gives an address of a memory cell in the chip for writing / reading to the selected chip, and instructs writing / reading of data to write data. Data is transmitted or read data is received.
- Each memory chip is selected from the control chip 100 and performs a plurality of operations such as a state of writing / reading data and a state of relaying data such as an address exchanged between the selected memory chip and the control chip 100.
- the operation state to be taken next is determined based on the control data transmitted by the control chip 100 and the current operation state.
- the state of each memory chip is determined by 3 bits held by the flip-flop 134 in the sequential logic circuit 135. Based on the 3-bit status information ⁇ S 1, S 2, S 3 ⁇ held by the flip-flop 134 and the 2-bit data “D 1, D 2” received by the receiving circuit, the combinational logic circuit 136 should next take the memory chip. 3-bit data representing the operating state is calculated and stored in the flip-flop 134. Further, the control circuit 125 inputs the 3-bit status information stored in the flip-flop 134 and performs an operation determined by the status information. When the control chip 100 instructs a specific memory chip to write / read data, it outputs a reset signal to all the memory chips via the reset line 103 to reset the flip-flop 134 of each memory chip. By the reset process, the states of all the memory chips are set to the initial state. Following the reset process, the control chip 100 outputs the 2-bit data “D1, D2” to the stacked memory chips via the data channel 104.
- FIG. 4 is a diagram showing a state transition of the sequential logic circuit 135 by the 2-bit data “D1, D2”.
- Reception state ⁇ 000 ⁇ The flip-flop 134 is reset by the reset signal output from the control chip 100 and becomes ⁇ 000 ⁇ , and the communication circuit enters the reception state.
- the memory chip m in the receiving state is the 2-bit data “D1” received from the memory chip m ⁇ 1 (the memory chip 1 is the control chip 100: hereinafter referred to as “previous device”.
- the memory chip m + 1 is referred to as “subsequent device”).
- D2 to the combinational logic circuit 136.
- the combinational logic circuit 136 determines the next internal state based on the state information ⁇ 000 ⁇ and the above-described 2-bit data “D1, D2”.
- the 2-bit data “D1, D2” is “00”
- the internal state maintains the reception state ⁇ 000 ⁇ .
- “D1, D2” is “01”, “11”, and “10”
- the internal state transitions to the transfer state ⁇ 001 ⁇ , the selection preparation state ⁇ 010 ⁇ , and the sleep preparation state ⁇ 100 ⁇ , respectively.
- Transfer state ⁇ 001 ⁇ The communication circuit 120 in the transfer state ⁇ 001 ⁇ functions as a transfer (relay) circuit, and transmits the 2-bit data “D1, D2” received from the preceding device to the succeeding device. Further, the state information is maintained at ⁇ 001 ⁇ for all the 2-bit data “D1, D2”.
- the selection preparation state ⁇ 010 ⁇ is a preparation stage state in which, when the 2-bit data “00” is received, its own memory chip is shifted to a selection state in which a read / write operation can be performed.
- the communication circuit 120 in the selection preparation state receives the 2-bit data “01”, “11”, and “10” from the previous stage device, the state information is maintained in the selection preparation state ⁇ 010 ⁇ , and the received 2-bit data “D1, D2” is received. Is transmitted to the subsequent apparatus.
- Selection state ⁇ 011 ⁇ is an operation state in which memory cells can be read / written.
- the communication circuit 120 set to the selected state ⁇ 011 ⁇ does not change its internal state due to the 2-bit data “D1, D2” received from the preceding device, and the received 2-bit data “D1, D2” is not changed. There is no transmission to the subsequent device.
- Sleep ready state ⁇ 100 ⁇ In the sleep ready state ⁇ 100 ⁇ , when two-bit data “00” is received, functions other than the minimum function such as a reset operation of the own memory chip are stopped, and sleep with low power consumption is performed. This is a state in a preparation stage for making a transition to a state.
- the 2-bit data “D1, D2” received by the communication circuit 120 in the sleep ready state from the preceding device is “01”, “11”, “10”, the state information is maintained in the sleep ready state ⁇ 100 ⁇ and received.
- the transmitted 2-bit data “D1, D2” is transmitted to the subsequent apparatus.
- the internal state is set to the sleep state ⁇ 110 ⁇ with low power consumption, and the 2-bit data “00” is transmitted to the downstream device.
- Sleep state ⁇ 110 ⁇ The memory chip in the sleep state ⁇ 110 ⁇ stops functions other than the smallest functional unit such as a reset circuit to reduce power consumption. The operation of receiving the 2-bit data “D1, D2” from the preceding apparatus is also stopped.
- the memory chip in the selected state ⁇ 011 ⁇ has a communication path set by the control chip 100 transmitting the 2-bit data “D1, D2” and the read / write control signal and address signal output from the control chip 100.
- data is read from the memory area specified by the address signal and transmitted to the control chip 100 via the communication path.
- the data transmitted by the control chip 100 via the communication path is written into the memory area designated by the address signal.
- Memory chips stacked between the control chip 100 and the memory chip in the selected state ⁇ 011 ⁇ are set to the transfer state ⁇ 001 ⁇ .
- the memory chip in the transfer state ⁇ 001 ⁇ performs relay processing of addresses, data, and the like exchanged between the control chip 100 and the memory chip in the selected state ⁇ 011 ⁇ .
- FIG. 5 is an example of a sequential logic circuit that realizes the state transition shown in FIG.
- the sequential logic circuit 135 includes a flip-flop 134 and a combinational logic circuit 136.
- the flip-flop 134 is a circuit that stores the state information ⁇ S1, S2, S3 ⁇ , and is reset by the reset signal 103 output from the control chip 100, and becomes ⁇ 0, 0, 0 ⁇ , that is, the reception state ⁇ 000 ⁇ .
- the combinational logic circuit 136 uses the combinational logic circuit 136 shown in FIG. 5 to output the 3-bit output ⁇ S 1, S 2, S 3 ⁇ of the flip-flop 134 and the 2-bit data “D 1, D 2” received by the reception circuit 123 from the preceding device. A logical operation is performed, and the result is held in the flip-flop 134.
- FIG. 6 shows a procedure for setting a memory chip 5 to a selected state in order to write / read data to / from a predetermined memory chip, for example, the memory chip 5 in a memory system in which eight memory chips are stacked.
- the control chip 100 transmits a reset signal 103 to all the memory chips and sets the memory chip to the receiving state ⁇ 000 ⁇ .
- the memory chip 1 in the reception state ⁇ 000 ⁇ receives the 2-bit data “01”, the memory chip 1 transits to the transfer state ⁇ 001 ⁇ .
- Second step (# 2) The control chip 100 transmits 2-bit data “01” to put the memory chip 2 into a transfer state.
- the memory chip 1 in the transfer state ⁇ 001 ⁇ transfers the 2-bit data “01” to the subsequent memory chip 2.
- the memory chip 2 in the reception state ⁇ 000 ⁇ receives the 2-bit data “01”, the memory chip 2 transits to the transfer state ⁇ 001 ⁇ .
- the 2-bit data “01” is transferred to the memory chip 3 via the memory chip 1 and the memory chip 2 in the transfer state ⁇ 001 ⁇ .
- Step 4 The control chip 100 transmits 2-bit data “01” to put the memory chip 4 into a transfer state.
- the 2-bit data “01” transmitted by the control chip 100 is transferred to the memory chip 4 via the memory chips 1 to 3 in the transfer state ⁇ 001 ⁇ , and the memory chip 4 is changed to the transfer state ⁇ 001 ⁇ . .
- the control chip 100 transmits 2-bit data “11” in order to put the memory chip 5 into a selection preparation state.
- the data is transferred to the memory chip 5 via the memory chips 1 to 4 in the transfer state ⁇ 001 ⁇ .
- the memory chip 5 in the reception state ⁇ 000 ⁇ receives the 2-bit data “11”, the memory chip 5 transits to the selection preparation state ⁇ 010 ⁇ .
- the control chip 100 transmits 2-bit data “10” in order to set the memory chip 7 to the sleep ready state.
- the data is transferred to the memory chip 7 via the memory chips 1 to 4 in the transmission state ⁇ 001 ⁇ , the memory chip 5 in the selection preparation state ⁇ 010 ⁇ , and the memory chip 6 in the sleep preparation state ⁇ 100 ⁇ .
- the memory chip 7 in the reception state ⁇ 000 ⁇ receives the 2-bit data “10”, it transitions to the sleep preparation state ⁇ 100 ⁇ .
- Eighth step (# 8) The control chip 100 transmits 2-bit data “10” in order to set the memory chip 8 to the sleep ready state.
- the data is transferred to the memory chip 8 via the memory chips 1 to 4 in the transfer state ⁇ 001 ⁇ , the memory chip 5 in the selection preparation state ⁇ 010 ⁇ , the memory chip 6 in the sleep preparation state ⁇ 100 ⁇ , and the memory chip 7. Is done.
- the memory chip 8 in the reception state ⁇ 000 ⁇ receives the 2-bit data “10”, it transitions to the sleep preparation state ⁇ 100 ⁇ .
- the 2-bit data “00” is transmitted to the memory chip 5 via the memory chips 1 to 4 in the transfer state ⁇ 001 ⁇ .
- the memory chip 5 in the selection preparation state ⁇ 010 ⁇ that has received the 2-bit data “00” transitions to the selection state ⁇ 011 ⁇ and transmits the 2-bit data “00” to the memory chip 6 in the subsequent stage.
- the memory chip 6 in the sleep ready state ⁇ 100 ⁇ that has received the 2-bit data “00” makes a transition to the sleep state ⁇ 110 ⁇ and transmits the 2-bit data “00” to the subsequent memory chip 7.
- the memory chip 7 and the memory chip 8 in the sleep preparation state ⁇ 100 ⁇ perform the same operation as the memory chip 6 and transition to the sleep state ⁇ 110 ⁇ .
- the control chip 100 executes steps 1 to 9 shown in FIG. 6 so that the memory chips 1 to 4 are in the transfer state, the memory chip 5 is in the selected state, and the memory chips 6 to 8 are in the sleep state. Set to state. After completing the above settings, the control chip 100 transmits information necessary for accessing the memory chip 5, such as write / read control information and address information.
- the memory chips 1 to 4 set to the transfer state perform a transfer (relay) process of data exchanged between the control chip 100 and the memory chip 5.
- the memory chip 5 receives the read / write control signal and the address signal output from the control chip 100, reads data from the memory area specified by the address signal according to the read / write control signal, and passes through the communication path. To the control chip 100. Alternatively, the data transmitted by the control chip 100 via the communication path is written into the memory area designated by the address signal.
- the present invention relates to an electronic circuit device configured by stacking a plurality of components such as memory chips having the same function, without adding identification information to each component, and adding any component of the stacked components. It will be selectable. With the configuration according to the first embodiment of the present invention, it is not necessary to set information for identifying the constituent elements such as the stacking order for the constituent elements to be stacked. Therefore, there is no limit to the number of layers that can be stacked, and any number of electronic circuits can be stacked.
- FIG. 7 is a state transition diagram of the second embodiment.
- the states of the stacked components are the reception state, the transfer state, and the selection state, and the state information, that is, the information held in the flip-flop 134 of the sequential logic circuit 135 is 2 bits.
- Reception state ⁇ 00 ⁇ With the reset signal output from the control chip, the state information of the memory chip is reset to ⁇ 00 ⁇ , and the communication circuit enters the reception state.
- the 2-bit data “D1, D2” from the preceding device is “01”
- the state information becomes ⁇ 01 ⁇ and the memory chip transitions to the transfer state.
- the 2-bit data “D1, D2” is “11”
- the state information becomes ⁇ 10 ⁇
- the memory chip transitions to the selected state.
- “D1, D2” is “00” “10”
- the reception state ⁇ 00 ⁇ is maintained.
- Transfer state ⁇ 01 ⁇ The memory chip in the transfer state ⁇ 01 ⁇ performs a relay process of data exchanged between the preceding device and the succeeding device.
- Selection state ⁇ 10 ⁇ The memory chip in the selection state ⁇ 10 ⁇ sets its memory circuit to a selection state in which reading / writing is possible, and reads / writes the memory in accordance with access information such as address information transmitted from the preceding device. Perform writing.
- the memory chip in the selected state ⁇ 10 ⁇ does not transmit the data transmitted from the preceding device to the succeeding device. Therefore, the succeeding apparatus remains in the reception state ⁇ 00 ⁇ .
- the configuration of the sequential logic circuit is simplified by reducing the state taken by each component, and the 2-bit data “D1, D2” transmitted by the control chip to set the state of each component ”Can be reduced. Therefore, it is possible to reduce the control amount and time required for setting the electronic circuit device in which a plurality of components are stacked to a target state.
- FIG. 8 is a diagram showing the configuration of an electronic circuit device according to the third embodiment of the present invention.
- a group is formed by connecting a plurality of predetermined number of components (members).
- two groups 210 and 220 are shown.
- Each group includes two members.
- the group 210 includes members 211 and 215.
- Identification information is given to each member.
- “ID1” is assigned to the member 211
- “ID2” is assigned to the member 215.
- the identification information is set by a method that is set in advance in the component, or a method that is automatically set according to the position in the group.
- a target electronic circuit device is configured by cascading a plurality of groups.
- One member in each group (group 1 and member 2 in group 2) has communication circuits 216 and 226, respectively, and is connected in cascade.
- the state setting data 202 (2-bit data “D1, D2” in FIG. 1) output from the control chip 200 is transferred between the communication circuits.
- the communication circuits 216 and 226 have the same function as the communication circuit of the first embodiment or the second embodiment, and the operation state of the communication circuits 216 and 226 is determined by the 2-bit data “D1, D2” output from the control chip 200. To decide.
- the control chip 200 according to the present embodiment transmits ID information for designating members in the group after the setting of the operation state for each communication circuit is completed.
- the communication circuits 216 and 226 have designation circuits 217 and 227 for designating members in the group based on the ID information transmitted from the control chip 200 when the communication circuits 216 and 226 are set to the selected state.
- a member not having a communication circuit has operation control circuits 212 and 222 for controlling its own operation (memory cell access operation in the case of a memory chip) in accordance with the designation of the designation circuit. ing.
- the designation circuits 217 and 227 execute the function of the operation control circuit.
- the communication circuit for example, 226 set to the selected state receives the ID information transmitted from the control chip 200 via the communication circuit 216
- the designation circuit 227 determines the member designated by the ID information, and The operation control circuit of the member to be instructed to respond to the access request of the control chip 200.
- the control chip 200 transmits memory access control information such as a memory cell address and a read / write control signal.
- the operation control circuit (or the designation circuit) included in the member designated by the control chip 200 receives the control information and executes the designated operation.
- the operation control circuits of the other members transfer the operation control information transmitted from the control chip 200 to the subsequent members.
- a communication circuit is provided for each group.
- the selection operation by the control chip 200 is a configuration in which after selecting a group, members in the group are designated. Therefore, the selection operation by the control chip 200, that is, the transmission of the status data and the transmission of the ID information is sufficient by the total number of groups and the number of members in the group, and a high-speed selection operation is possible.
- the required number of communication circuits is the number of groups, and the configuration can be simplified and the power consumption can be reduced.
- FIG. 9A is a diagram showing a configuration of an electronic circuit device according to a fourth embodiment of the present invention
- FIG. 9B is a diagram showing components stacked at a position farthest from the control element. is there.
- a wired communication path is set between the control element (control chip) and the component (that is, the memory chip n) stacked farthest from the control element by using bonding wiring or the like.
- An electronic circuit device according to the present invention has a configuration in which a plurality (n) of components are stacked in a vertical direction or a horizontal direction on a control chip that is a control element, and a component in which signals from the control element are stacked Are configured to relay sequentially.
- the input circuit 330 for directly inputting the control data of the control chip 300 is provided in the receiving circuit unit 323 of the component stacked at the position farthest from the control element.
- the control chip 300 that has detected that a failure has occurred in the k-th component and that communication with a device subsequent to the component cannot be performed, controls the input means 330 of the component n, and the control chip 300 performs the control.
- the control data output via the line 310 is set to be passed to the receiving circuit unit 323.
- the control chip 300 transmits data to be transmitted from the component 1 to the component k-1 from the data channel 309 to the component 1.
- the component 1 sequentially transfers the data to the component k-1 according to the same procedure as in the first to third embodiments, and sets the operation state of each component.
- the control chip 300 transmits data to be transmitted from the component k + 1 to the component n to the component n via the data line 310.
- the components k + 1 to n transfer the control information received by the component n via the data line 310 toward the component k + 1 using the configuration for changing the data transmission direction described in FIG. Then, the operating state of each component is set.
- the fourth embodiment in an electronic circuit in which a plurality of components are stacked, it is possible to transfer a control signal from a control element from a component at the last stage of the stacked components in a direction opposite to normal. To do.
- the control signal from the control element is transferred from the last-stage component in the opposite direction to the normal state. By doing so, it is possible to continue to use components that operate normally. With this configuration, it is possible to reduce a decrease in function due to a failure.
- the present invention constitutes an electronic circuit device having an arbitrary ability by stacking an arbitrary number of components having the same function.
- the constituent elements to be stacked have the same structure or are classified into two to three types.
- the present invention constitutes a device by laminating components having the same function in any number of vertical or horizontal directions, and does not depend on the functions of the components.
- any communication means such as mechanical connection by a connector or a contact or optical coupling by a light emitting element and a light receiving element is possible.
- the control element does not need to notify the selection destination information to all the components, and the power can be reduced. Further, the amount of data transmitted by each component is small, and communication power can be reduced.
- a stacked semiconductor device capable of selecting and communicating a desired semiconductor chip by radio or wire from the same function semiconductor chips stacked in multiple layers in the electronic circuit device.
- an electronic circuit device capable of selecting and communicating a desired electronic circuit board wirelessly or by wire from a plurality of electronic circuit boards having the same function that are stacked in multiple layers and are detachable.
- the fourth embodiment of the present invention by providing a signal path for transmitting data to the component at the end farthest from the control element, a part of the stacked components becomes an obstacle, Even when data cannot be relayed, normal components can be operated.
- control elements are stacked on the frontmost part (or the last part) of a plurality of stacked structural elements (memory chips or the like).
- a form in which constituent elements are stacked before and after the control element, and the control element is positioned at an intermediate portion of the plurality of constituent elements is possible.
- the distance between the control element and the component to be controlled that is, the number of components that perform the transfer (relay) operation is reduced, and the control required for setting the electronic circuit device to the target state.
- the amount or time required for control can be reduced.
- data and the like are exchanged between adjacent control elements or components. However, as shown in FIG.
- Patent Document 1 by using inductive coupling, it is possible to adopt a configuration in which data and the like are exchanged between elements stacked separately. Also in the present invention, it is possible to configure the communication means of the control element and the component to exchange data etc. with the elements stacked at a distant position. It is possible to reduce the amount of control required for setting the component or the time required for control.
- the embodiment described in this specification is a configuration in which data is exchanged between each component by inductive coupling.
- a configuration for sending and receiving data a configuration is provided in which contact points that contact the preceding component and the subsequent component are provided in the component, and contact points of each component are contacted to form data transfer by stacking the components Alternatively, data transfer using a light emitting element and a light receiving element is possible.
- Use of data transfer by inductive coupling has the following effects.
- a coil for inductive coupling can be applied with a normal integration technique or a printed circuit board technique, and does not have a mechanical connection structure such as a connector or a through via, and can be laminated at a low cost and with a low power.
- a device provided with a non-contact connector, such as a non-contact memory card, can be realized.
- the present invention is applicable not only to the field of large-capacity memory devices by stacking a plurality of memory chips, but also to devices that realize a large processing capacity by connecting a plurality of components having the same function.
- Application to the memory field has the following effects.
- application to a memory non-volatile memory or random access memory
Abstract
Description
このような積層型半導体装置内に多層に積層されたチップ間や、積層されたプリント配線基板間を無線接続する技術として、本発明者らは、チップ上の配線やプリント配線基板上の配線により形成されるコイルを介して積層実装されるチップ間や基板間で誘導結合による通信を行う電子回路を提案している(特許文献1~7、非特許文献1~8参照。)。
各チップを何番目の順位に積層実装するかを予め決めておけば、チップの製造過程でチップ識別番号を埋め込むことができる。例えば、フラッシュメモリの場合、各チップをテストして良品を選別する段階で、フラッシュメモリの特定の領域にチップ識別番号を書き込めば良い。或いは、DRAMの場合、レーザーでヒューズを切断することで、チップ識別番号を書き込むことができる。DRAMでは、各チップをテストして不良ビットが見つかれば、レーザーを照射して冗長回路のヒューズを切断することで、不良ビット列を予備のビット列に置き換えることができるからである。
そこで、製造過程にチップ識別番号を埋め込むことや実装時にワイヤボンディングでチップ識別番号を与えるのではなく、各チップに固有のチップ識別番号を割り当てるために、以下のような発明が行われている。
更に、特開2003-110086号公報(特許文献8)および特開2007-157266号公報(特許文献9)いずれの発明においても、全チップにチップ選択アドレスを送り、各チップのチップ識別番号と比較することで所望の半導体チップを選択するために、全チップに共通の接続経路を形成しなければならない。誘導結合で接続する場合、接続できる距離は、コイルの直径程度である。したがって、全チップに共通の接続経路を形成するためには、全チップを積層実装したときのチップの厚さ方向の距離に相当する直径のコイルが必要になる。チップの厚さが50μmの場合、64枚のチップを積層すると3mm以上の厚さになる。この場合、全チップに共通の接続経路を形成するためには3mm以上の直径のコイルが必要になり、これを10mm程度のチップに集積するのは高価になる。
また、抜き差しできる基板が積層された状態にある場合、基板の挿抜のたびにチップ識別番号を生成する必要があり、そのための電力が必要になる。
本発明は、上記問題点に鑑み、同一種類或いは2乃至3種類に分類される複数の半導体チップ又は装置等の電子回路要素を任意の数縦方向或いは横方向に積層させて装置を構成し、所望の電子回路基板を選択して通信することが可能な積層型装置を提供することを目的としている。また、少ない消費電力により積層された複数の電子回路要素から任意の電子回路要素を選択することが可能な構成を提供することを目的としている。また、多層に積層される複数の電子回路要素から所望の電子回路要素を端子の接触、光結合、或いは電磁結合により選択的に結合し通信することが可能な電子回路に応用できることを目的としている。
図1(a)は同実施態様の全体構成を示す図であり、同一機能のn個のメモリチップ(メモリチップ1からメモリチップn)が積層され、メモリチップの最前列にコントロールチップ100が積層されている。メモリチップは通信回路111乃至113と、図示されていない所定の容量のメモリセルと読み出し/書き込み制御回路が集積されている。
通信回路内には送受信回路が設けられている。当該実施態様は誘導結合により通信を行うものであり、通信距離は任意の値に設計可能である。メモリチップmの送受信回路内の受信回路はメモリチップm-yからの信号を受信し、メモリチップm内の制御回路に渡す。また、メモリチップmの送信回路は制御回路のデータをメモリチップm+xに送信する。メモリチップmが転送状態にある時、受信回路が受信した信号を送信回路により送信することにより、メモリチップm-yからの信号をチップm+xに転送(中継)する。
当該実施態様の送受信回路は、前方の構成要素から信号を受信し、後方の構成要素に送信する送受信形態と、後方の構成要素から信号を受信し、前方の構成要素に送信する送受信形態が可能である。従って上記の「x」と「y」は正もしくは負の整数が可能であるが、以下、「x」と「y」はいずれも1の場合で説明する。
n個のメモリチップの中の特定のメモリチップm内に集積されているメモリセルにアクセスする場合、コントロールチップ100はデータ入出力部104からメモリチップmを選択する制御データを出力することにより、メモリチップmを選択状態に設定する。次に、コントロールチップ100は、アクセスするメモリセルのアドレスと、書き込み/読み出し制御信号を出力し、前記アドレスに対してデータの書き込み/読み出しを実行する。
送受信回路122は前段のメモリチップm-1の送受信回路と誘導結合する受信回路部123と、後段のメモリチップm+1の送受信回路と誘導結合する送信回路部127と、通信回路120の全体を制御する制御回路125を有している。
順序論理回路135はメモリチップの動作状態を表す3ビットの状態情報[S1、 S2、 S3]133を記憶するフリップフロップ134と、組合せ論理回路136を有している。組合せ論理回路136はフリップフロップ134の値と送受信回路122が前段のメモリチップm-1(メモリチップ1ではコントロールチップ100)から送信された2ビットの制御情報(D1、D2)131に基づいて、メモリチップmが次に採るべき動作状態を決定し、対応する状態情報をフリップフロップ134に記憶する。
制御回路125は状態情報[S1、 S2、 S3]133に基づいてメモリチップmの動作を決定し、メモリチップmの全体を制御する。制御回路125はメモリチップ内のメモリセルに読み出し/書き込みの制御信号とアドレス情報を送信し、読み出したデータ或いは書き込むデータを授受する信号線137を有している。
データの授受には、受信器回路部123を介して受信したデータをメモリセル等の内部回路に送信する動作、同じく、受信したデータを送信回路部127を介して次段のメモリチップに転送(中継)する動作、メモリセル等の内部回路のデータを送信回路部127を介して次段のメモリチップ(又はコントロールチップ100)に送信する動作がある。
ゲート回路144は制御回路125からの[disable]信号により制御される。ゲート回路144がオンの時、受信回路部123は受信状態となり、増幅回路143は受信コイル141が受信した信号を増幅して制御回路に渡す。制御回路125から[disable]信号が出力されるとゲート回路144はオフとなり、増幅回路143と受信コイル141は分離され、受信動作は休止状態(disabled)となる。
送信器146は制御回路125が出力するデータ信号[Txdata]の「1」「0」に対応して送信コイル145に流れるパルス電流(IT)の向きを制御し、次段の受信コイルとの間に出力信号に対応した誘導結合を生成する。
なお、同図では、受信回路部と送信回路部は各一つのみが記載されているが、必要に応じて任意の数とすることが可能である。
図2(c)は受信コイル141と送信コイル145を個別に設ける構成である。当該構成を採用することにより、受信コイル141と送信コイル145の設置位置を任意に決定することが可能となり、各コイル間の干渉を小さくすることが可能となる。
図2(d)は1つのコイル147により送信コイルと受信コイルを兼用する構成であり、コイルを送信時と受信時に切り換えて使用する。図2(e)のコイル148は送信コイルと受信コイルを同軸に配置する構成である。図2(d)及び図2(e)の構成は、送信時は送信回路146を駆動し受信回路142を休止状態とし、受信時は受信回路142を駆動し送信回路146を休止状態とすることにより相互干渉を防止する。
チップ151の制御回路が送信器を介して送信コイルAを駆動すると、チップ152の受信状態に設定されている受信コイルAは誘導結合により信号を検知し、チップ152の制御回路に受信した信号(Rxdata)を渡す。この動作により、チップ151からチップ152にデータの送信が行われる。
チップ152の制御回路は送信する信号に基づいてチップ152の送信コイルBを駆動する。送信コイルBによる誘導結合はチップ151の受信コイルBとチップ153の受信コイルBに到達する。チップ151の受信コイルBは休止状態に設定されているため信号を検知することはない。一方チップ153の受信コイルBは受信状態に設定されているため信号を検知しチップ153の制御部に渡す。上記動作により、チップ152からチップ153にデータの送信が行われる。
次に、チップ153の送信コイルCからチップ154の受信状態に設定されている受信コイルCにデータの送信が行われ、更に、チップ154の送信コイルAからチップ155の受信状態に設定されている受信コイルAにデータの送信が行われる。当該構成と動作により、図1のコントロールチップ100は積層されたメモリチップ1乃至メモリチップnにデータを送信することが可能となる。
図3(b)において、チップ162からチップ163にデータを送信する場合、チップ162のコイルDを送信状態に設定すると共に、チップ161のコイルDを休止状態、チップ163のコイルDを受信状態に設定する。チップ162のコイルDを送信データにより駆動すると、チップ161のコイルDとチップ163のコイルDに誘導結合が発生する。チップ161のコイルDを休止状態に設定されているため、チップ161はチップ162のデータを受信することはない。これに対して、チップ163のコイルDは受信状態に設定されており、誘導結合によりチップ162からのデータを受信する。
従って、チップ161のコイルDを休止状態、チップ163のコイルDを受信状態に設定することにより、チップ162からチップ163にデータを送信することが可能となる。また、チップ163のコイルDを休止状態、チップ161のコイルDを受信状態に設定することにより、チップ162からチップ161にデータを送信することが可能となる。
チップ間のデータの送受信を行う全てのチャネルを1コイル型とすることにより、各チップのコイルの構造は同一となり、積層するチップを全て同一機能且つ同一構造とすることが可能となる。
各メモリチップは、コントロールチップ100から選択され、データの書き込み/読み出しを行う状態、選択されたメモリチップとコントロールチップ100との間で授受されるアドレス等のデータを中継する状態等、複数の動作状態を有し、コントロールチップ100が送信した制御データと現在の動作状態に基づいて、次に採るべき動作状態を決定する。
コントロールチップ100は特定のメモリチップにデータの書き込み/読み出しを指示する際、リセットライン103を介して全てのメモリチップにリセット信号を出力し、各メモリチップのフリップフロップ134をリセットする。当該リセット処理により、全てのメモリチップの状態は初期状態に設定される。コントロールチップ100は、上記リセット処理に続いて、2ビットデータ「D1、D2」を、データチャネル104を介して積層されたメモリチップに出力する。
受信状態{000}:コントロールチップ100が出力したリセット信号により、フリップフロップ134はリセットされ、{000}となり、通信回路は受信状態となる。受信状態のメモリチップmはメモリチップm-1(メモリチップ1はコントロールチップ100:以下「前段装置」と言う。また、メモリチップm+1を「後段装置」と言う)から受信した2ビットデータ「D1、D2」を組合せ論理回路136に渡す。組合せ論理回路136は状態情報{000}と上記の2ビットデータ「D1、D2」に基づいて次の内部状態を決定する。2ビットデータ「D1、D2」が「00」の時は、内部状態は受信状態{000}を維持する。また「D1、D2」が「01」「11」「10」の時、内部状態は各々、転送状態{001}、選択準備状態{010}、スリープ準備状態{100}に遷移する。
転送状態{001}:転送状態{001}にある通信回路120は転送(中継)回路として機能し、前段装置から受信した2ビットデータ「D1、D2」を後段装置に送信する。また、全ての2ビットデータ「D1、D2」に対して状態情報は{001}に維持される。
選択準備状態にある通信回路120が前段装置から2ビットデータ「01」「11」「10」を受信すると、状態情報を選択準備状態{010}に維持し、受信した2ビットデータ「D1、D2」を後段装置に送信する。前段装置から2ビットデータ「00」を受信すると、内部状態をメモリセルの読み出し/書き込み動作可能な状態である選択状態{011}に遷移させると共に、2ビットデータ「00」を後段装置に送信する。
選択状態{011}:選択状態{011}は、メモリセルの読み出し/書き込みが可能な動作状態である。選択状態{011}に設定されている通信回路120は、前段装置から受信した2ビットデータ「D1、D2」により内部状態が変化することはなく、また受信した2ビットデータ「D1、D2」を後段装置に送信することもない。
スリープ準備状態にある通信回路120が前段装置から受信した2ビットデータ「D1、D2」が「01」「11」「10」の時は、状態情報をスリープ準備状態{100}に維持し、受信した2ビットデータ「D1、D2」を後段装置に送信する。前段装置から2ビットデータ「00」を受信すると、内部状態を消費電力が小さいスリープ状態{110}に設定すると共に2ビットデータ「00」を後段装置に送信する。
スリープ状態{110}:スリープ状態{110}にあるメモリチップは、リセット回路等の最小の機能部以外の機能を停止し消費電力を小さくする。前段装置から2ビットデータ「D1、D2」を受信する動作も停止する。
コントロールチップ100と、選択状態{011}にあるメモリチップとの間に積層されているメモリチップは転送状態{001}に設定される。転送状態{001}にあるメモリチップは、コントロールチップ100と選択状態{011}のメモリチップとの間で授受されるアドレスやデータ等の中継処理を行う。
順序論理回路135はフリップフロップ134と、組合せ論理回路136からなる。フリップフロップ134は状態情報{S1、S2、S3}を記憶する回路であり、コントロールチップ100が出力するリセット信号103によりリセットされ、{0、0、0}即ち、受信状態{000}となる。
組合せ論理回路136は、フリップフロップ134の3ビット出力{S1、S2、S3}と受信回路123が前段装置から受信した2ビットデータ「D1、D2」とを図5に示される組合せ論理回路136により論理演算を行い、その結果をフリップフロップ134に保持する。
メモリチップの状態の設定を開始する時、コントロールチップ100は全てのメモリチップにリセット信号103を送信し、メモリチップを受信状態{000}に設定する。
第1ステップ(#1):コントロールチップ100はメモリチップ1を転送状態にするために2ビットデータ「01」を送信する。受信状態{000}にあるメモリチップ1は、2ビットデータ「01」を受信すると転送状態{001}に遷移する。
第2ステップ(#2):コントロールチップ100はメモリチップ2を転送状態にするために2ビットデータ「01」を送信する。転送状態{001}となっているメモリチップ1は2ビットデータ「01」を後段のメモリチップ2に転送する。受信状態{000}のメモリチップ2は2ビットデータ「01」を受信すると転送状態{001}に遷移する。
第3ステップ(#3):コントロールチップ100はメモリチップ3を転送状態にするために2ビットデータ「01」を送信する。当該2ビットデータ「01」は、転送状態{001}にあるメモリチップ1とメモリチップ2を介してメモリチップ3に転送される。受信状態{000}のメモリチップ3は2ビットデータ「01」を受信すると転送状態{001}に遷移する。
第4ステップ(#4):コントロールチップ100はメモリチップ4を転送状態にするために2ビットデータ「01」を送信する。コントロールチップ100が送信した2ビットデータ「01」は、転送状態{001}にあるメモリチップ1乃至メモリチップ3を介してメモリチップ4に転送され、メモリチップ4を転送状態{001}に遷移させる。
第6ステップ(#6):コントロールチップ100はメモリチップ5の読み出し/書き込み動作に関与しないメモリチップ6をスリープ状態にするため、まず、メモリチップ6をスリープ準備状態に設定する2ビットデータ「10」を送信する。当該データは転送状態{001}のメモリチップ1乃至メモリチップ4と、選択準備状態{010}のメモリチップ5を介してメモリチップ6に転送される。受信状態{000}のメモリチップ6は2ビットデータ「10」を受信するとスリープ準備状態{100}に遷移する。
第7ステップ(#7):コントロールチップ100はメモリチップ7をスリープ準備状態に設定するために、2ビットデータ「10」を送信する。当該データは送信状態{001}のメモリチップ1乃至メモリチップ4、選択準備状態{010}のメモリチップ5、スリープ準備状態{100}のメモリチップ6を介してメモリチップ7に転送される。受信状態{000}のメモリチップ7は2ビットデータ「10」を受信するとスリープ準備状態{100}に遷移する。
第8ステップ(#8):コントロールチップ100はメモリチップ8をスリープ準備状態に設定するために、2ビットデータ「10」を送信する。当該データは転送状態{001}のメモリチップ1乃至メモリチップ4、選択準備状態{010}のメモリチップ5、スリープ準備状態{100}のメモリチップ6とメモリチップ7を介してメモリチップ8に転送される。受信状態{000}のメモリチップ8は2ビットデータ「10」を受信するとスリープ準備状態{100}に遷移する。
第9ステップ(#9):コントロールチップ100は選択準備状態とスリープ準備状態にあるメモリチップを各々、選択状態とスリープ状態に遷移させるため、2ビットデータ「00」を送信する。2ビットデータ「00」は転送状態{001}のメモリチップ1乃至メモリチップ4を介してメモリチップ5に送信される。2ビットデータ「00」を受信した選択準備状態{010}にあるメモリチップ5は、選択状態{011}に遷移すると共に、2ビットデータ「00」を後段のメモリチップ6に送信する。2ビットデータ「00」を受信したスリープ準備状態{100}にあるメモリチップ6は、スリープ状態{110}に遷移すると共に、2ビットデータ「00」を後段のメモリチップ7に送信する。スリープ準備状態{100}にあるメモリチップ7とメモリチップ8はメモリチップ6と同様の動作を行いスリープ状態{110}に遷移する。
上記の設定を終了したコントロールチップ100は、書き込み/読み出し制御情報、アドレス情報等、メモリチップ5のアクセスに必要な情報を送信する。転送状態に設定されたメモリチップ1乃至メモリチップ4は、コントロールチップ100とメモリチップ5の間で授受されるデータの転送(中継)処理を行う。
メモリチップ5は、コントロールチップ100が出力した、読み出し/書き込み制御信号、及びアドレス信号を受信し、読み出し/書き込み制御信号に従って、アドレス信号により指定されたメモリ領域からデータを読み出し、前記通信路を介してコントロールチップ100に送信する。或いは、前記通信路を介してコントロールチップ100が送信したデータをアドレス信号により指定されたメモリ領域に書き込む。
転送状態{01}:転送状態{01}にあるメモリチップは、前段装置と後段装置の間で授受されるデータの中継処理を行う。
選択状態{10}:選択状態{10}にあるメモリチップは自身のメモリ回路を読み出し/書き込みが可能な選択状態にセットし、前段装置から送信されるアドレス情報等のアクセス情報に従ってメモリの読み出し/書き込みを実行する。選択状態{10}にあるメモリチップは前段装置から送信されたデータを後段装置に送信することはない。従って、後段装置は受信状態{00}のままである。
当実施態様は複数のグループを縦続接続して目的の電子回路装置を構成する。各グループ内の一つのメンバー(グループ1及びグループ2のメンバー2)は各々通信回路216、226を有しており縦続接続されている。コントロールチップ200から出力される状態設定データ202(図1の2ビットデータ「D1、D2」)が通信回路間を転送される。
通信回路216、226は、自身が選択状態に設定された時、コントロールチップ200から送信されたID情報に基づいてグループ内のメンバーを指定する指定回路217、227を有している。
通信回路を有しないメンバー(グループ1及びグループ2のメンバー1)は、指定回路の指定に従って自身の動作(メモリチップの場合はメモリセルのアクセス動作)を制御する動作制御回路212、222を有している。通信回路を有すメンバー(グループ1及びグループ2のメンバー2)の場合、指定回路217、227が動作制御回路の機能を実行する。
選択状態に設定されている通信回路(例えば、226)が、コントロールチップ200が送信したID情報を通信回路216を介して受信すると、指定回路227は当該ID情報が指定するメンバーを判別し、該当するメンバーの動作制御回路にコントロールチップ200のアクセス要求に応答することを指示する。
本発明に係る電子回路装置は、制御要素であるコントロールチップに複数(n個)の構成要素を縦方向或いは横方向に積層した構成であり、上記制御要素からの信号を積層されている構成要素が順次中継する構成である。従って、n個の構成要素の中間に位置する構成要素、例えばk番の構成要素に障害が発生し、制御要素からの信号の中継が行えなくなった場合、正常に動作することが可能であるk+1番からn番の構成要素も利用することができなくなる。
本実施態様では、制御要素から最も遠い位置に積層されている構成要素の受信回路部323に、コントロールチップ300の制御データを直接入力する入力手段330を設けたものである。k番の構成要素に障害が発生し、当該構成要素より後段の装置との通信が行えなくなったことを検知したコントロールチップ300は、構成要素nの入力手段330を制御し、コントロールチップ300が制御ライン310を介して出力する制御データを受信回路部323に渡す設定とする。
コントロールチップ300は、構成要素k+1から構成要素nに送信するデータを、データライン310を介して構成要素nに送信する。構成要素k+1乃至構成要素nは、図3で説明されているデータの送信方向を変更する構成を用いて、構成要素nがデータライン310を介して受信した制御情報を構成要素k+1に向けて転送し、各構成要素の動作状態を設定する。
本発明は同一の機能を有する構成要素を任意の数縦方向或いは横方向に積層させて装置を構成するものであり、構成要素が有する機能に依存するものではない。また、積層された構成素間の通信手段として、コネクタ或いは接点による機械的な接続、発光素子と受光素子とによる光結合等任意の通信手段が可能である。
本発明の構成により、構成要素の再設計をすること無く構成要素を追加、或いは削除が可能となり、装置全体の能力の変更が可能となる。また、識別番号を各構成要素に割り当てる必要がなくコストの低減が可能となる。制御要素は選択先情報を全ての構成要素に知らせる必要がなく低電力化が可能となる。また、各構成要素が送信するデータ量が少なく、通信電力の削減が可能となる。
本発明の第3の実施態様では、グループ選択を行い、グループ内のメンバー選択を別の手段で行うことにより、構成要素の数が多いときの選択を高速に行うことが可能となる。
本発明の第4の実施態様では、制御要素から最も離れている最終端の構成要素にデータを送信する信号路を設けることにより、積層された構成要素の一部が障害となり、制御要素からのデータを中継することが不可能となった場合であっても、正常な構成要素を動作させることが可能となる。
また、上記の第1乃至第3の実施態様は、隣接する制御要素又は構成要素間でデータ等の授受を行う形態である。しかし、特許文献1の図4に示される様に、誘導結合を用いることにより、離れて積層されている要素間でデータ等の授受を行う構成とすることが可能である。本発明においても、制御要素及び構成要素の通信手段を、離れた位置に積層されている要素との間でデータ等の授受を行う構成することが可能であり、同構成により、制御要素は目的とする構成要素の設定に要する制御量、或いは制御に要する時間を小さくすることが可能となる。
誘導結合用のコイルは通常の集積技術、或いはプリント基板の技術の適用が可能であり、コネクタや貫通ビアなどの機械式接続の構造が無く、低コスト、低電力に基板を積層できる。
非接触コネクタを備えた装置、例えば非接触メモリカードなどが実現できる。
Claims (10)
- 少なくとも1つの制御要素と同一の機能を実現する複数の構成要素を積層した電子回路装置であって、
前記制御要素及び前記構成要素はデータを送受信する通信手段を有し、
前記制御要素は前記通信手段を介して前記構成要素の状態の変更を指示するデータを前記構成要素の一つに送信する手段を有し、
前記構成要素は前段の制御要素又は構成要素から送信された前記状態の変更を指示するデータに従って動作状態を変更する手段と、
前記通信手段を介して前記前段の制御要素又は構成要素から送信された前記状態の変更を指示するデータを後段の構成要素に送信する手段を有することを特徴とする電子回路装置。 - 請求項1記載の電子回路装置であって、
前記構成要素は動作状態を表す状態情報を保持する状態情報保持手段と、
前記状態の変更を指示するデータと前記状態情報保持手段に保持された状態情報に基づいて動作状態を決定する組合せ論理手段を有することを特徴とする電子回路装置。 - 請求項2記載の電子回路装置であって、
前記制御要素は前記状態情報を初期状態にリセットする信号を出力するリセット手段を有することを特徴とする電子回路装置。 - 請求項1乃至請求項3記載の電子回路装置であって、
前記構成要素は同一の機能を実現する複数のメンバーと、
前記制御要素が指示したメンバーを選択するメンバー指定手段を有することを特徴とする電子回路装置。 - 請求項1乃至請求項3記載の電子回路装置であって、
前記制御要素と前記制御要素から最も離れた位置に積層されている構成要素と通信する第2の通信路を有することを特徴とする電子回路装置。 - 請求項1乃至請求項3記載の電子回路装置であって、
前記通信手段は、コイルによる誘導結合を用いた無線接続手段であることを特徴とする電子回路装置。 - 請求項1乃至請求項3記載の電子回路装置であって、
前記構成要素は着脱可能な電子回路基板であることを特徴とする電子回路装置。 - 請求項1乃至請求項3記載の電子回路装置であって、
前記構成要素は半導体チップであることを特徴とする電子回路装置。 - 請求項8記載の電子回路装置であって、
前記半導体チップはメモリチップであることを特徴とする電子回路装置。 - 請求項1乃至請求項3記載の電子回路装置であって、
前記構成要素は同一機能であり且つ同一構造であることを特徴とする電子回路装置。
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KR20110027722A (ko) | 2011-03-16 |
JP2010015654A (ja) | 2010-01-21 |
US20110102015A1 (en) | 2011-05-05 |
US8283944B2 (en) | 2012-10-09 |
KR101833545B1 (ko) | 2018-02-28 |
JP4982778B2 (ja) | 2012-07-25 |
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