WO2009145111A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2009145111A1
WO2009145111A1 PCT/JP2009/059369 JP2009059369W WO2009145111A1 WO 2009145111 A1 WO2009145111 A1 WO 2009145111A1 JP 2009059369 W JP2009059369 W JP 2009059369W WO 2009145111 A1 WO2009145111 A1 WO 2009145111A1
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WIPO (PCT)
Prior art keywords
substrate
via hole
semiconductor device
finger
source
Prior art date
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PCT/JP2009/059369
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English (en)
French (fr)
Inventor
河阪俊行
Original Assignee
ユーディナデバイス株式会社
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Publication date
Application filed by ユーディナデバイス株式会社 filed Critical ユーディナデバイス株式会社
Publication of WO2009145111A1 publication Critical patent/WO2009145111A1/ja
Priority to US12/950,493 priority Critical patent/US8455951B2/en

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Definitions

  • the present invention relates to a semiconductor device, and more particularly to a semiconductor device including a substrate having a via hole.
  • a via hole penetrating from the front surface to the back surface may be formed on a substrate on which a semiconductor element such as an FET (Field Effect Transistor) is formed.
  • the inner surface of the via hole is covered with a metal layer, and can be electrically connected to the semiconductor element from the back surface of the substrate through the via hole. This can reduce parasitic impedance and the like when electrically connected to the semiconductor element.
  • Patent Document 1 discloses a substrate having an elliptical via hole.
  • a substrate having a via hole may be cracked by stress applied to the substrate due to temperature cycling or warping of the mounting substrate on which the substrate is mounted.
  • the via hole is enlarged in order to suppress cracks generated in the substrate, the chip area is increased.
  • the present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device capable of suppressing cracks generated in a substrate due to via holes and reducing the chip area.
  • the present invention comprises a rectangular substrate and a via hole having an elliptical shape or a track shape having a straight portion in its long axis direction, the long axis being arranged along the long side direction of the substrate.
  • a plurality of the via holes may be provided along the long side direction of the substrate.
  • the semiconductor element formed on the surface of the substrate has a plurality of unit FETs having a source finger, a drain finger, and a gate finger, and the plurality of unit FETs are connected in parallel, and the source finger, the drain At least one of the finger and the gate finger may be connected to the via hole, and the source finger, the drain finger, and the gate finger may be provided along the short side direction of the substrate.
  • a plurality of the source fingers may be provided in one source pad, and the via hole may be provided in a lower portion of the source pad.
  • the ratio of the long axis to the short axis of the via hole may be 1.1 or more. According to this structure, the crack which arises in a board
  • the ratio of the long axis to the short axis of the via hole may be 1.5 or more. According to this structure, the crack which arises in a board
  • the substrate may be configured of any one of SiC, Si, sapphire, GaN, GaAs, and InP.
  • the substrate may be provided with a mounting surface on which the substrate is mounted via a bonding metal made of any of AuSn, Ag paste, and solder.
  • the mounting surface can be configured by any member of Cu, CuMo, CuW, a stack of Cu and Mo, and a stack of Cu and CuMo.
  • FIG. 1A is a top view of a chip used in the experiment
  • FIG. 1B is a schematic top view showing a crack that has occurred.
  • FIG. 2 is a diagram showing the defect rate with respect to the diameter of the via hole.
  • FIG. 3A and FIG. 3B are examples of shapes viewed from the surface of the via hole.
  • 4A is a top view of the semiconductor device according to the first embodiment
  • FIG. 4B is a bottom view
  • FIG. 4C is a cross-sectional view along AA ′.
  • FIG. 5 is a cross-sectional view of the second embodiment.
  • 6A is a top view of the second embodiment
  • FIG. 6B is a top view when the second embodiment is screwed to the substrate.
  • FIG. 7 is a diagram showing the defect rate with respect to the elliptical axis ratio of the via hole.
  • FIG. 1A is a top view of the chip used in the experiment.
  • Fifteen via holes 12b are arranged along the long side 41 of the SiC substrate 10 having a thickness of about 100 ⁇ m, a length L1 of the long side 41 of about 5 mm, and a length L2 of the short side 42 of about 1 mm.
  • the shape seen from the surface of the via hole 12b is circular.
  • the via hole 12 is provided in contact with a pad 13 made of Ni provided on the surface of the substrate 10.
  • the back surface of the substrate 10 and the inner surface of the via hole 12 are covered with a metal film (not shown) having a thickness of about 10 ⁇ m.
  • Table 1 shows the results of a temperature cycle test of a sample having a circular via hole 12b. Each of the 100 samples was tested, and a sample having a crack in the substrate 10 was regarded as defective. The number of defects indicates the number of defective samples, and the defect rate indicates the number of defects / number of tests ⁇ 100%.
  • FIG. 2 is a diagram showing a defect rate with respect to the diameter of the via hole 12b. Black circles indicate experimental values, and solid lines indicate approximate values.
  • Defectiveness due to the temperature cycle test is considered to be caused by thermal stress or warpage of the mounting board due to the thermal expansion coefficient between the board 10 and the mounting board. From Table 1 and FIG. 2, the via hole with a larger diameter has a lower defect rate. This indicates that the larger the curvature of the via hole 12, the less likely the substrate 10 is to crack. However, if the via hole 12 having a large diameter is used, the chip area becomes large.
  • FIG. 1B is a schematic top view of an example of a cracked sample.
  • the inventor has paid attention to the fact that a crack 45 generated in the rectangular substrate 10 occurs in the direction of the short side 42 from the via hole 12. This is presumably because the short side 42 is more stressed than the long side 41.
  • it is considered that cracks in the substrate 10 can be suppressed by making the cracked region of the via hole 12 easy to generate a curve or straight line having a large curvature, and the chip area can be reduced by reducing the curvature of the region in which the crack is difficult to occur. It was.
  • 3 (a) and 3 (b) are diagrams showing examples of via holes for suppressing cracks generated in the substrate.
  • the via hole 12 has an elliptical shape.
  • An elliptical long axis AL is arranged along the long side direction of the rectangular substrate.
  • the via hole 12 has a boundary region of the via hole 12 facing the short side where the substrate is liable to be cracked and has a large curvature, and the region of the boundary of the via hole 12 facing the long side where the crack is difficult to occur is Consists of curves with small curvature. Therefore, the crack of the substrate 10 is hardly generated and the chip area can be reduced.
  • the via hole 12a has, for example, a track shape.
  • the boundary region of the via hole 12a facing in the short side direction where a crack of the substrate is likely to occur is constituted by a straight line (that is, it has a straight part in its long axis direction), and in the long side direction where the crack is difficult to occur.
  • the boundary region of the opposing via hole 12a is configured by a curve.
  • the substrate 10 has a via hole 12 or 12a having a horizontally long shape when viewed from the surface, and the long axis of the via hole 12 or 12a is in the direction of the long side of the substrate 10 Arrange along.
  • substrate resulting from the via hole 12 or 12a can be suppressed, and a chip area can be reduced.
  • Example 1 is an example having an FET as a semiconductor element.
  • 4A is a top view of the semiconductor device according to the first embodiment
  • FIG. 4B is a bottom view
  • FIG. 4C is a cross-sectional view taken along line AA ′ in FIGS. 4A and 4B. It is.
  • the chip 100 has a SiC substrate 10.
  • the SiC substrate 10 is rectangular when viewed from the surface.
  • a semiconductor element 18 is formed on the surface of the substrate 10.
  • the semiconductor element 18 includes a unit FET 20 having a source finger 22, a drain finger 26, and a gate finger 24, and a plurality of unit FETs 20 are connected in parallel.
  • the source finger 22, the drain finger 26, and the gate finger 24 are provided along the direction (short side direction) in which the short side 42 of the substrate 10 extends.
  • Source finger 22, drain finger 26 and gate finger 24 are connected to source pad 23, drain pad 27 and gate bus bar 28, respectively.
  • the source pad 23, the drain pad 27, and the gate bus bar 28 are disposed on the extending direction of the source finger 22, the drain finger 26, and the gate finger 24, respectively.
  • the source fingers 22 cross over the gate bus bar 28 via a gap. That is, it has an air bridge structure.
  • a gate pad 25 is connected to the gate bus bar 28.
  • the drain pad 27 and the gate pad 25 are regions for bonding bonding wires.
  • the source finger 22 is connected to one source pad 23, and a via hole 12 is provided below the source pad 23. As a result, the source finger 22 is connected to the via hole 12 via the source pad 23.
  • the via hole 12 has an elliptical shape, and the long axis is provided along the direction in which the long side 41 of the rectangular substrate 10 extends (long side direction).
  • the FET 20 includes, for example, a GaN traveling layer, an AlGaN electron supply layer, and a GaN cap layer that are sequentially formed on the SiC substrate 10.
  • the source finger 22 and the drain finger 26 are made of a metal such as Ti / Al from the bottom formed on the GaN cap running layer.
  • the gate finger 24 is made of a metal such as Ni / Au from the bottom formed on the GaN cap layer.
  • a metal film 14 made of, for example, Ti / Au is formed on the back surface of the substrate 10 from the substrate side.
  • the via hole 12 penetrates the front surface and the back surface of the substrate 10, and the inner surface of the via hole 12 is covered with a metal film 14.
  • the shape of the substrate becomes a strip shape when an attempt is made to increase the gate width.
  • the FET 10 having a large gate width has a thin substrate 10 for heat dissipation. Therefore, cracks are likely to occur in the substrate 10 and it is effective to use the laterally long via holes 12.
  • the example in which the via hole 12 is connected to the source finger 22 has been described.
  • the source impedance can be reduced.
  • the via hole 12 only needs to be connected to at least one of the source finger 22, the drain finger 26, and the gate finger 24.
  • an FET is described as an example of the semiconductor element 18, but the via hole 12 only needs to be connected to the semiconductor element 18.
  • a single via hole 12 may be used instead of a plurality.
  • Example 2 is an example in which the chip of Example 1 is mounted on a mounting substrate.
  • FIG. 5 is a cross-sectional view of the second embodiment.
  • FIG. 6A is a top view of the second embodiment
  • FIG. 6B is a top view when the electronic component according to the second embodiment is screwed to the substrate.
  • the chip 100 according to the first embodiment is mounted on a mounting surface 31 of a mounting substrate 30 made of Cu, for example, using a bonding metal 32 made of AuSn.
  • the bonding metal 32 for example, Ag paste, solder, or the like may be used in addition to AuSn.
  • the mounting substrate 30 in addition to a mounting substrate made of Cu, for example, a single layer of an alloy of Cu and Mo (CoMo), a single layer of an alloy of Cu and W (CoW), and a plurality of layers of Cu and Mo are stacked.
  • a mounting substrate in which a plurality of Cu and CuMo are stacked, or the like can be used.
  • a frame 34 for hermetically sealing the chip 100 and a transmission path 36 for inputting / outputting signals to / from the chip 100 from the outside of the frame 34 are provided on the mounting substrate 30, a frame 34 for hermetically sealing the chip 100 and a transmission path 36 for inputting / outputting signals to / from the chip 100 from the outside of the frame 34 are provided. Yes.
  • the transmission path 36 and the gate pad and drain pad of the chip 100 are connected by bonding wires 40.
  • the source pad of the chip 100 is connected to the surface of the mounting substrate 30 by a bonding wire 40.
  • concave portions 38 for screwing are provided at both ends of the mounting substrate 30, concave portions 38 for screwing are provided.
  • the electronic component according to the second embodiment is screwed to a substrate 50 made of a metal such as Cu using a screw 52, for example. Thereby, the mounting substrate 30 is electrically and thermally connected to the substrate 50.
  • the mounting substrate 30 is made of a metal (particularly a metal containing Cu), the difference in linear thermal expansion coefficient between the mounting substrate 30 and the substrate 10 is large. Therefore, cracks are likely to occur in the substrate 10 due to thermal stress, and it is effective to use a laterally long via hole.
  • the substrate 10 is easily cracked due to distortion of the mounting substrate 30, and it is effective to use a horizontally long via hole. .
  • FIG. 1 a plurality of samples with elliptical via holes were manufactured and a temperature cycle test was conducted in the same manner as in Table 1.
  • the prototype sample has a major axis length / short axis length (ratio of major axis to minor axis) of an elliptical shape of 80 ⁇ m / 70 ⁇ m, 90 ⁇ m / 60 ⁇ m, 100 ⁇ m / 55 ⁇ m, 110 ⁇ m / 50 ⁇ m, or 130 ⁇ m / 40 ⁇ m.
  • Table 2 is a table showing the results of a temperature cycle test of a sample having an elliptical via hole.
  • FIG. 7 is a diagram showing a defect rate with respect to the elliptical axis ratio (major axis length / minor axis length) of the via hole 12. Black circles indicate experimental values, and solid lines indicate approximate values.
  • the defect rate is 58%. However, from Table 2 and FIG. 7, the defect rate is drastically reduced to 37% when the elliptical axis ratio having the same size is 1.14. It becomes. Thus, when the elliptical axis ratio is 1.1 or more, the defect rate decreases. If it is 1.5 or more, the defect rate further decreases, and if it is 1.8 or more, the defect rate is zero. From the above, the major axis / minor axis of the via hole 12 is preferably 1.1 or more. Furthermore, 1.5 or more is preferable and 1.8 or more is more preferable. Considering the manufacturing variation of the via hole 12, 2.2 or more is more preferable. In addition, the elliptical axis ratio of the track-shaped via hole 12a shown in FIG.
  • Example 1 and Example 2 the example in which the semiconductor element is formed on the SiC substrate 10 has been described.
  • the substrate 10 for example, a substrate made of any one of SiC, Si, sapphire, GaN, GaAs, and InP can be used.
  • the substrate made of SiC, sapphire, or GaN has a high hardness, the substrate 10 is likely to be cracked, and it is effective to use a laterally long via hole.

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Abstract

　本発明は、長方形の基板１０と、楕円形状または直線部分をその長軸方向に有するトラック形状からなり、その長軸が基板１０の長辺方向に沿って配置されてなるビアホール１２と、を具備することを特徴とするである。本発明によれば、ビアホールに起因した基板に生じる亀裂を抑制し、かつチップ面積を削減することができる。

Description

半導体装置
　本発明は半導体装置に関し、特に、ビアホールを有する基板を具備する半導体装置に関する。
　ＦＥＴ（Field Effect Transistor）等の半導体素子が形成された基板に、表面から裏面に貫通するビアホールを形成する場合がある。ビアホールの内面は金属層で被覆され、基板の裏面からビアホールを介し半導体素子と電気的に接続することができる。これにより、半導体素子と電気的に接続する際に寄生インピーダンス等を低減させることができる。
　特許文献１には、楕円形状のビアホールを有する基板が開示されている。
特開２０００－１３８２３６号公報
　しかしながら、ビアホールを有する基板は、温度サイクルや基板を実装する実装基板の反りに起因し基板に加わるストレスにより亀裂が生じる場合がある。一方、基板に生じる亀裂を抑制するためにビアホールを大きくするとチップ面積が大きくなってしまう。
　本発明は、上記課題に鑑みなされたものであり、ビアホールに起因し基板に生じる亀裂を抑制し、かつチップ面積を削減することが可能な半導体装置を提供することを目的とする。
　本発明は、長方形の基板と、楕円形状または直線部分をその長軸方向に有するトラック形状からなり、その長軸が前記基板の長辺方向に沿って配置されてなるビアホールと、を具備することを特徴とする半導体装置である。本発明によれば、ビアホールに起因した基板に生じる亀裂を抑制し、かつチップ面積を削減することができる。
　上記構成において、前記ビアホールは前記基板の長辺方向に沿って複数設けられている構成とすることができる。
　上記構成において、前記基板の表面に形成された半導体素子は、ソースフィンガー、ドレインフィンガーおよびゲートフィンガーを有する複数の単位ＦＥＴを有し、前記複数の単位ＦＥＴは並列に接続され、前記ソースフィンガー、ドレインフィンガーおよびゲートフィンガーの少なくとも１つが前記ビアホールに接続され、前記ソースフィンガー、ドレインフィンガーおよびゲートフィンガーは前記基板の短辺方向に沿って設けられている構成とすることができる。
　上記構成において、複数の前記ソースフィンガーが一つのソースパッドに設けられ、前記ソースパッドの下部に前記ビアホールが設けられている構成とすることができる。
　上記構成において、前記ビアホールの短軸に対する長軸の比は１．１以上である構成とすることができる。この構成によれば、ビアホールに起因し基板に生じる亀裂をより抑制することができる。
　　上記構成において、前記ビアホールの短軸に対する長軸の比は１．５以上である構成とすることができる。この構成によれば、ビアホールに起因し基板に生じる亀裂をより抑制することができる。
　上記構成において、前記基板は、ＳｉＣ、Ｓｉ、サファイア、ＧａＮ、ＧａＡｓおよびＩｎＰのいずれかからなる構成とすることができる。
　上記構成において、前記基板をＡｕＳｎ、Ａｇペーストおよび半田のいずれかからなる接合金属を介し実装する実装面を具備する構成とすることができる。
　上記構成において、前記実装面は、Ｃｕ、ＣｕＭｏ、ＣｕＷ、ＣｕとＭｏとの積層、およびＣｕとＣｕＭｏとの積層のいずれかの部材からなる構成とすることができる。
　本発明によれば、ビアホールに起因した基板に生じる亀裂を抑制し、かつチップ面積を削減することができる。
図１（ａ）は、実験に用いたチップの上面図、図１（ｂ）は、発生した亀裂を示す上面模式図である。 図２は、ビアホールの直径に対する不良率を示した図である。 図３（ａ）および図３（ｂ）はビアホールの表面から見た形状の例である。 図４（ａ）は実施例１に係る半導体装置の上面図、図４（ｂ）は下面図、図４（ｃ）は、Ａ－Ａ´断面図である。 図５は、実施例２の断面図である。 図６（ａ）は実施例２の上面図であり、図６（ｂ）は実施例２を基板にねじ止めをした際の上面図である。 図７は、ビアホールの楕円軸比に対する不良率を示す図である。
　まず、本発明の原理を説明するために行った実験について説明する。図１（ａ）は、実験に用いたチップの上面図である。厚さが約１００μｍ、長辺４１の長さＬ１が約５ｍｍ、短辺４２の長さＬ２が約１ｍｍのＳｉＣ基板１０の長辺４１に沿って１５個のビアホール１２ｂが配列されている。ビアホール１２ｂの表面から見た形状は円形状である。ビアホール１２は基板１０の表面に設けられたＮｉからなるパッド１３に接触するように設けられている。基板１０の裏面およびビアホール１２の内面には膜厚が約１０μｍの金属膜（不図示）が被覆している。
　ビアホール１２ｂの大きさが異なるサンプルを１００個ずつ試作した。試作した各チップをＣｕからなる実装基板にＡｕＳｎを用い実装した。各チップを実装した実装基板に対し温度サイクル試験を行った。温度サイクル試験は、－６５℃と１５０℃との間の温度サイクルを５００回行った。
　表１は円形状のビアホール１２ｂを有するサンプルの温度サイクル試験の結果である。各１００個のサンプルについて試験し、基板１０に亀裂が生じたサンプルを不良とした。不良数は不良となったサンプル数、不良率は、不良数／試験数×１００％を示している。図２は、ビアホール１２ｂの直径に対する不良率を示した図である。黒丸は実験値、実線は近似値を示している。
Figure JPOXMLDOC01-appb-T000001
　温度サイクル試験による不良は、基板１０と実装基板との間の熱膨張係数に起因する熱ストレスや実装基板の反りが原因と考えられる。表１および図２より、直径の大きなビアホールほど不良率が小さい。これは、ビアホール１２の曲率が大きいほど基板１０に亀裂が生じにくいことを示している。しかしながら、直径の大きなビアホール１２を用いるとチップ面積が大きくなってしまう。
　図１（ｂ）は亀裂が生じたサンプルの一例の上面模式図である。本発明者は、図１（ｂ）のように、長方形の基板１０に生じる亀裂４５がビアホール１２から短辺４２方向に生じることに着目した。これは、短辺４２の方が長辺４１よりも大きなストレスが働くためと考えられる。そこで、ビアホール１２の亀裂の生じやすい領域を曲率の大きな曲線または直線とすることで、基板１０に生じる亀裂が抑制でき、亀裂の生じにくい領域の曲率を小さくすることでチップ面積を削減できると考えた。
　図３（ａ）および図３（ｂ）は、基板に生じる亀裂を抑制するビアホールの例を示した図である。図３（ａ）を参照に、ビアホール１２は楕円形状を有している。楕円形状の長軸ＡＬを長方形基板の長辺方向に沿って配置する。これにより、ビアホール１２は、基板の亀裂が生じやすい短辺方向に相対するビアホール１２の境界領域は曲率の大きな曲線で構成され、亀裂が生じにくい長辺方向に相対するビアホール１２の境界の領域は曲率の小さな曲線で構成される。よって、基板１０の亀裂が生じにくく、かつチップ面積を削減することができる。
　図３（ｂ）を参照に、ビアホール１２ａは例えばトラック（ｔｒａｃｋ）形状を有している。このトラック形状とは、基板の亀裂が生じやすい短辺方向に相対するビアホール１２ａの境界領域は直線で構成され（つまり、直線部分をその長軸方向に有する）、亀裂が生じにくい長辺方向に相対するビアホール１２ａの境界領域は曲線で構成される。
　図３（ａ）および図３（ｂ）のように、基板１０は、表面から見た形状が横長形状のビアホール１２または１２ａを有し、ビアホール１２または１２ａの長軸は基板１０の長辺方向に沿って配置する。これにより、ビアホール１２または１２ａに起因し基板に生じる亀裂を抑制し、かつチップ面積を削減することができる。
　以下、図面を参照に本発明の実施例について説明する。
　実施例１は、半導体素子としてＦＥＴを有する例である。図４（ａ）は実施例１に係る半導体装置の上面図、図４（ｂ）は下面図、図４（ｃ）は図４（ａ）および図４（ｂ）のＡ－Ａ´断面図である。
　図４（ａ）を参照に、チップ１００はＳｉＣ基板１０を有している。ＳｉＣ基板１０は表面から見た形状が長方形である。基板１０の表面に半導体素子１８が形成されている。半導体素子１８は、ソースフィンガー２２、ドレインフィンガー２６およびゲートフィンガー２４を有する単位ＦＥＴ２０を有し、複数の単位ＦＥＴ２０が並列に接続されている。
　ソースフィンガー２２、ドレインフィンガー２６およびゲートフィンガー２４は、基板１０の短辺４２の延伸する方向（短辺方向）に沿って設けられている。ソースフィンガー２２、ドレインフィンガー２６およびゲートフィンガー２４は、それぞれ、ソースパッド２３、ドレインパッド２７およびゲートバスバー２８に接続されている。ソースパッド２３、ドレインパッド２７およびゲートバスバー２８は、それぞれソースフィンガー２２、ドレインフィンガー２６およびゲートフィンガー２４の延伸方向上に配置されている。ソースフィンガー２２はゲートバスバー２８上を空隙を介し交差している。すなわちエアーブリッジ構造となっている。ゲートバスバー２８にはゲートパッド２５が接続されている。ドレインパッド２７およびゲートパッド２５は、ボンディングワイヤをボンディングするための領域である。
　ソースフィンガー２２は一つのソースパッド２３に接続され、ソースパッド２３の下部にビアホール１２が設けられている。これにより、ソースフィンガー２２は、ソースパッド２３を介しビアホール１２に接続されている。ビアホール１２の形状は楕円形状であり、長軸が長方形基板１０の長辺４１の延伸する方向（長辺方向）に沿って設けられている。ＦＥＴ２０は、例えばＳｉＣ基板１０上に順次形成されたＧａＮ走行層、ＡｌＧａＮ電子供給層およびＧａＮキャップ層を有している。ソースフィンガー２２およびドレインフィンガー２６は、ＧａＮキャップ走行層上に形成された下からＴｉ／Ａｌ等の金属からなる。ゲートフィンガー２４はＧａＮキャップ層上に形成された下からＮｉ／Ａｕ等の金属からなる。
　図４（ｂ）を参照に、基板１０の裏面には例えば基板側からＴｉ／Ａｕ等からなる金属膜１４が形成されている。図４（ｃ）を参照に、ビアホール１２は基板１０の表面と裏面とを貫通しており、ビアホール１２の内面は金属膜１４で被覆されている。
　実施例１のように、単位ＦＥＴ２０を複数並列に接続したＦＥＴにおいては、ゲート幅を大きくしようとすると基板の形状が短冊型になる。また、ゲート幅の大きいＦＥＴは放熱のため基板１０が薄い。よって、基板１０に亀裂が発生しやすく、横長形状のビアホール１２を用いることが有効である。
　実施例１では、ビアホール１２がソースフィンガー２２に接続される例を説明した。ビアホール１２がソースフィンガー２２に接続されることにより、ソースインピーダンスを低減することができる。ビアホール１２は、ソースフィンガー２２、ドレインフィンガー２６およびゲートフィンガー２４の少なくとも１つに接続されていればよい。実施例１では、半導体素子１８としてＦＥＴを例に説明したが、ビアホール１２は半導体素子１８に接続されていればよい。また、ビアホール１２は複数用いられなくとも１つでもよい。
　実施例２は、実施例１のチップを実装基板に実装した例である。図５は、実施例２の断面図である。図６（ａ）は実施例２の上面図であり、図６（ｂ）は実施例２に係る電子部品を基板にねじ止めした際の上面図である。図５を参照に、実施例１のチップ１００は、例えばＣｕからなる実装基板３０の実装面３１にＡｕＳｎからなる接合金属３２を用い実装されている。接合金属３２は、ＡｕＳｎ以外にも、例えばＡｇペースト、半田等を用いてもよい。実装基板３０としては、Ｃｕからなる実装基板以外にも、例えば、ＣｕとＭｏとの合金（ＣｏＭｏ）の単層、ＣｕとＷとの合金（ＣｏＷ）の単層、ＣｕとＭｏとが複数積層された実装基板、またはＣｕとＣｕＭｏとが複数積層された実装基板等を用いることができる。
　図６（ａ）を参照に、実装基板３０上には、チップ１００を気密封止するためのフレーム３４、チップ１００に信号をフレーム３４の外から入出力するための伝送路３６が設けられている。伝送路３６とチップ１００のゲートパッドおよびドレインパッドは、それぞれボンディングワイヤ４０で接続される。チップ１００のソースパッドは実装基板３０表面とボンディングワイヤ４０で接続される。実装基板３０の両端には、ねじ止めのための凹部３８が設けられている。図６（ｂ）を参照に、実施例２に係る電子部品は例えば、Ｃｕ等の金属からなる基板５０にねじ５２を用いねじ止めされている。これにより、実装基板３０は基板５０と電気的かつ熱的に接続される。
　図５および図６（ａ）のように、実装基板３０が金属（特にＣｕを含む金属）からなる場合、実装基板３０と基板１０との線熱膨張係数の差が大きい。よって、熱ストレスに起因し基板１０に亀裂が生じ易く、横長形状のビアホールを用いることが有効である。
　また、図６（ｂ）のように、実装基板３０を基板５０にねじ止めする場合、実装基板３０の歪等により、基板１０に亀裂が生じ易く、横長形状のビアホールを用いることが有効である。
　図１と同様に、ビアホールが楕円形状のサンプルを複数試作し、表１と同様に温度サイクル試験を行った。試作したサンプルは、楕円形状の長軸長／短軸長（短軸に対する長軸の比）が８０μｍ／７０μｍ、９０μｍ／６０μｍ、１００μｍ／５５μｍ、１１０μｍ／５０μｍ、または１３０μｍ／４０μｍである。表２は楕円形状のビアホールを有するサンプルの温度サイクル試験の結果を示す表である。図７は、ビアホール１２の楕円軸比（長軸長／短軸長）に対する不良率を示した図である。黒丸は実験値、実線は近似値を示している。
Figure JPOXMLDOC01-appb-T000002
　表１の直径が７５μｍのビアホールでは、不良率は５８％であるが、表２および図７より、ほぼ同じ大きさの楕円軸比が１．１４のものでは不良率が急激に低減し３７％となる。このように、楕円軸比が１．１以上では、不良率が減少する。１．５以上ではさらに不良率が減少し、１．８以上では不良率は０である。以上より、ビアホール１２の長軸／短軸は１．１以上が好ましい。さらに、１．５以上が好ましく、１．８以上がより好ましい。このビアホール１２の製造バラツキを考慮すると、２．２以上がさらに好ましい。また、図３（ｂ）で示したトラック形状のビアホール１２ａの楕円軸比もビアホール１２と同様に１．１以上が好ましい。
　実施例１および実施例２においては、半導体素子がＳｉＣ基板１０に形成される例について説明した。基板１０としては、例えば、ＳｉＣ、Ｓｉ、サファイア、ＧａＮ、ＧａＡｓおよびＩｎＰのいずれかからなる基板とすることができる。特に、ＳｉＣ，サファイアまたはＧａＮからなる基板は硬度が大きいため、基板１０に亀裂が生じやすく、横長形状のビアホールを用いることが有効である。
　以上、発明の好ましい実施例について詳述したが、本発明は係る特定の実施例に限定されるものではなく、特許請求の範囲に記載された本発明の要旨の範囲内において、種々の変形・変更が可能である。

Claims (9)

  1. 　長方形の基板と、
    　楕円形状または直線部分をその長軸方向に有するトラック形状からなり、その長軸が前記基板の長辺方向に沿って配置されてなるビアホールと、を具備することを特徴とする半導体装置。
  2. 　前記ビアホールは前記基板の長辺方向に沿って複数設けられていることを特徴とする請求項１記載の半導体装置。
  3. 　前記基板の表面に形成された半導体素子は、ソースフィンガー、ドレインフィンガーおよびゲートフィンガーを有する複数の単位ＦＥＴを有し、前記複数の単位ＦＥＴは並列に接続され、
    　前記ソースフィンガー、ドレインフィンガーおよびゲートフィンガーの少なくとも１つが前記ビアホールに接続され、
    　前記ソースフィンガー、ドレインフィンガーおよびゲートフィンガーは前記基板の短辺方向に沿って設けられていることを特徴とする請求項１記載の半導体装置。
  4. 　複数の前記ソースフィンガーが一つのソースパッドに設けられ、
    　前記ソースパッドの下部に前記ビアホールが設けられていることを特徴とする請求項３記載の半導体装置。
  5. 　前記ビアホールの短軸に対する長軸の比は１．１以上であることを特徴とする請求項１記載の半導体装置。
  6. 　前記ビアホールの短軸に対する長軸の比は１．５以上であることを特徴とする請求項５記載の半導体装置。
  7. 　前記基板は、ＳｉＣ、Ｓｉ、サファイア、ＧａＮ、ＧａＡｓおよびＩｎＰのいずれかからなることを特徴とする請求項１記載の半導体装置。
  8. 　前記基板をＡｕＳｎ、Ａｇペーストおよび半田のいずれかからなる接合金属を介し実装する実装面を具備することを特徴とする請求項１記載の半導体装置。
  9. 　前記実装面は、Ｃｕ、ＣｕＭｏ、ＣｕＷ、ＣｕとＭｏとの積層、およびＣｕとＣｕＭｏとの積層のいずれかの部材からなることを特徴とする請求項８記載の半導体装置。
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