WO2013172139A1 - 半導体デバイス - Google Patents

半導体デバイス Download PDF

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Publication number
WO2013172139A1
WO2013172139A1 PCT/JP2013/061305 JP2013061305W WO2013172139A1 WO 2013172139 A1 WO2013172139 A1 WO 2013172139A1 JP 2013061305 W JP2013061305 W JP 2013061305W WO 2013172139 A1 WO2013172139 A1 WO 2013172139A1
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WO
WIPO (PCT)
Prior art keywords
lead
semiconductor chip
semiconductor device
semiconductor
wiring
Prior art date
Application number
PCT/JP2013/061305
Other languages
English (en)
French (fr)
Inventor
吉純 川端
Original Assignee
住友電気工業株式会社
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Filing date
Publication date
Application filed by 住友電気工業株式会社 filed Critical 住友電気工業株式会社
Publication of WO2013172139A1 publication Critical patent/WO2013172139A1/ja

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    • H01L23/495—Lead-frames or other flat leads
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Definitions

  • the present invention relates to a semiconductor device.
  • Non-Patent Document 1 As examples of semiconductor devices, case-type semiconductor devices and resin-encapsulated semiconductor devices are known (see Non-Patent Document 1).
  • a resin-encapsulated semiconductor device a semiconductor chip mounted on a die pad is connected to a lead via a wire.
  • An object of the present invention is to provide a semiconductor device having a short wiring between a semiconductor chip and a lead.
  • a semiconductor device includes: at least one semiconductor chip; and a lead having a first portion connected to the at least one semiconductor chip via a wiring, the first of the leads The portion extends along the first direction and is disposed opposite to the at least one semiconductor chip.
  • the semiconductor device may further include a die pad having a chip mounting surface on which the at least one semiconductor chip is mounted.
  • the at least one semiconductor chip may be a plurality of semiconductor chips, and the plurality of semiconductor chips may be arranged along the first direction. In this case, even if the number of semiconductor chips increases, the wiring between the semiconductor chip and the leads does not intersect.
  • the surface of the first portion of the lead may be disposed on the same plane as the surface of the at least one semiconductor chip. In this case, the wiring between the semiconductor chip and the lead is further shortened.
  • the material of the at least one semiconductor chip may include a wide band gap semiconductor. In this case, a larger current can be passed through the wiring than a semiconductor chip made of silicon.
  • the lead has a second portion connected to the first portion and extending along the first direction, and the second direction intersects the first direction, and the first portion The portion may protrude toward the at least one semiconductor chip from the second portion. In this case, since the distance between the semiconductor chip and the lead is shortened, the wiring is further shortened.
  • the semiconductor device may further include a resin portion that covers the at least one semiconductor chip and the first portion of the lead. Thereby, the semiconductor chip and the lead can be fixed to the resin portion.
  • a semiconductor device having a short wiring between a semiconductor chip and a lead can be provided.
  • FIG. 1 is a plan view schematically showing a semiconductor device according to a first embodiment.
  • FIG. 2 is a cross-sectional view of the semiconductor device taken along line II-II in FIG.
  • FIG. 3 is a cross-sectional view of the semiconductor device taken along line III-III in FIG. 1. It is a top view which shows typically the semiconductor device which concerns on 2nd Embodiment.
  • FIG. 5 is a cross-sectional view of the semiconductor device along the line VV in FIG. 4.
  • FIG. 5 is a cross-sectional view of the semiconductor device taken along line VI-VI in FIG. 4. It is a top view which shows typically the semiconductor device which concerns on 3rd Embodiment. It is a top view which shows typically the semiconductor device which concerns on 4th Embodiment. It is a top view which shows typically the semiconductor device which concerns on 5th Embodiment.
  • FIG. 1 is a plan view schematically showing the semiconductor device according to the first embodiment.
  • FIG. 2 is a cross-sectional view of the semiconductor device taken along line II-II in FIG.
  • FIG. 3 is a cross-sectional view of the semiconductor device taken along line III-III in FIG.
  • a semiconductor device 10 shown in FIGS. 1 to 3 is a resin-encapsulated semiconductor device.
  • the semiconductor device 10 includes a plurality of semiconductor chips 14 and first leads 18.
  • the semiconductor device 10 may include a die pad 12 having a chip mounting surface 12a on which a semiconductor chip 14 is mounted.
  • the die pad 12 can be electrically connected to the semiconductor chip 14.
  • the die pad 12 has a plate shape, for example.
  • the chip mounting surface 12a is, for example, a rectangle.
  • Examples of the material of the die pad 12 include metals such as copper (Cu) and a copper alloy.
  • a through-hole 26 that penetrates the die pad 12 in the thickness direction can be formed in the die pad 12.
  • the through hole 26 is a hole through which a screw is passed when the semiconductor device 10 is fixed to another member (for example, a heat sink or the like) by, for example, a screw.
  • the semiconductor device 10 may include a second lead 16 and a third lead 20.
  • the leads 16, 18, and 20 extend along the Y direction (first direction) and are arranged along the X direction (second direction intersecting the first direction).
  • the lead 16 is located between the leads 18 and 20.
  • the leads 16, 18, 20 and the die pad 12 may constitute a lead frame.
  • the semiconductor device 10 is a power semiconductor device used for a power source or the like, for example.
  • An example of the package form of the semiconductor device 10 is a general TO series. Examples of TO series include TO-247, TO-220, TO-263 (D2-PAK), and TO-252 (D-PAK).
  • the lead 18 has a first portion 18a connected to the semiconductor chip 14 via a wiring 22a.
  • the first portion 18a extends along the Y direction and is disposed opposite to the semiconductor chip 14.
  • the first portion 18a can be disposed to face the side surface of the semiconductor chip 14 along the Y direction.
  • the lead 18 may have a second portion 18b connected to the first portion 18a.
  • the second portion 18b extends along the Y direction.
  • the width of the first portion 18a may be wider than the width of the second portion 18b.
  • the first portion 18a may protrude toward the semiconductor chip 14 more than the second portion 18b in the X direction.
  • the lead 20 has a first portion 20a connected to the semiconductor chip 14 via a plurality of wirings 22b.
  • the semiconductor chip 14 may be connected to the first portion 20a through a single wiring 22b.
  • the first portion 20a extends along the Y direction and is disposed to face the semiconductor chip 14.
  • the first portion 20a may be disposed to face the side surface of the semiconductor chip 14 along the Y direction.
  • the lead 20 may have a second portion 20b connected to the first portion 20a.
  • the second portion 20b extends along the Y direction.
  • the width of the first portion 20a may be wider than the width of the second portion 20b.
  • the first portion 20a may protrude toward the semiconductor chip 14 more than the second portion 20b in the X direction.
  • the first portion 18 a of the lead 18 is disposed opposite to the first portion 20 a of the lead 20.
  • the semiconductor chip 14 is disposed between the first portion 18 a of the lead 18 and the first portion 20 a of the lead 20.
  • the semiconductor chips 14 can be arranged along the Y direction.
  • the second portion 18 b of the lead 18 can be disposed opposite to the second portion 20 b of the lead 20.
  • the wirings 22a and 22b may extend along the X direction.
  • the semiconductor chip 14 is mounted at a predetermined position on the chip mounting surface 12a.
  • the semiconductor chip 14 include a transistor such as a MOS-FET and an insulated gate bipolar transistor (IGBT), a diode such as a PN junction diode, and a Schottky barrier diode.
  • the semiconductor chip 14 can be mounted on the chip mounting surface 12a via an adhesive layer 40 made of a material containing lead-containing metal solder, lead-free metal solder, conductive resin, or the like.
  • Examples of the material of the semiconductor chip 14 include a wide band gap semiconductor, silicon and other semiconductors. A wide band gap semiconductor has a band gap larger than that of silicon. Examples of wide band gap semiconductors include silicon carbide (SiC), gallium nitride (GaN), and diamond.
  • the semiconductor chip 14 may have electrode pads GP and SP.
  • the electrode pad GP is connected to the lead 18 through the wiring 22a.
  • the electrode pad SP is connected to the lead 20 via the wiring 22b.
  • the electrode pad GP corresponds to the gate electrode pad
  • the electrode pad SP corresponds to the source electrode pad.
  • the electrode pad GP corresponds to a gate electrode pad
  • the electrode pad SP corresponds to an emitter electrode pad.
  • Further electrode pads such as a drain electrode pad or a collector electrode pad can be formed on the entire back surface of the semiconductor chip 14.
  • the semiconductor device 10 may include an insulating member 38 disposed between the die pad 12 and the leads 18 and 20.
  • the insulating member 38 is located between the die pad 12 and the first portion 18a of the lead 18 and the first portion 20a of the lead 20 in the Z direction (a third direction intersecting the first direction and the second direction). Intervene.
  • the insulating member 38 is, for example, an insulating substrate or an insulating layer. Examples of the material of the insulating member 38 include a resin such as an epoxy resin or ceramics.
  • the die pad 12, the insulating member 38, and the leads 18 and 20 can be connected to each other by an adhesive.
  • the inner end of the lead 16 is mechanically and integrally connected to the die pad 12. Since the die pad 12 has conductivity, the lead 16 and the die pad 12 are electrically connected. Examples of the material of the lead 16 include the same material as that of the die pad 12.
  • the lead 16 corresponds to the drain electrode terminal
  • the lead 18 corresponds to the gate electrode terminal
  • the lead 20 corresponds to the source electrode terminal.
  • the semiconductor chip 14 includes an IGBT
  • the lead 16 corresponds to a collector electrode terminal
  • the lead 18 corresponds to a gate electrode terminal
  • the lead 20 corresponds to an emitter electrode terminal.
  • the material of the leads 18 and 20 include metals such as copper and copper alloys.
  • the wires 22a and 22b may be wires or bonding ribbons. Examples of the material of the wirings 22a and 22b include metals such as aluminum, gold, and copper.
  • the wirings 22a and 22b are connected to the leads 18 and 20 and the semiconductor chip 14 by wire bonding using, for example, ultrasonic waves or pressure.
  • the die pad 12, the semiconductor chip 14, the first portion 18 a of the lead 18, and the first portion 20 a of the lead 20 can be covered with the resin portion 24. Inner ends of the leads 16, 18, and 20 are inserted into the resin portion 24. Of the leads 16, 18, and 20, the portion inside the resin portion 24 is a so-called inner lead portion. Of the leads 16, 18, and 20, the portion outside the resin portion 24 is an outer lead portion. An example of the outer shape of the resin portion 24 is a substantially rectangular parallelepiped. Examples of the material of the resin portion 24 include thermoplastic resins such as polyphenylene sulfide resin (PPS resin) and liquid crystal polymer.
  • the resin portion 24 can be formed by molding the die pad 12 and the semiconductor chip 14 with a thermoplastic resin.
  • a through hole 28 is formed in the resin portion 24 with the central axis of the through hole 26 of the die pad 12 as the central axis.
  • the through hole 28 is a hole through which a screw is passed in the case of screwing or the like, like the through hole 26.
  • the diameter of the through hole 28 is smaller than the diameter of the through hole 26.
  • the wiring 22 a between the semiconductor chip 14 and the lead 18 is shortened.
  • the semiconductor chip 14 and the first portion 20a of the lead 20 are disposed to face each other, the wiring 22b between the semiconductor chip 14 and the lead 20 is shortened.
  • the lengths of the wirings 22a and 22b are shortened, the heat dissipation of the wirings 22a and 22b is improved, so that the fusing current is increased. Therefore, even if a large current flows, the wirings 22a and 22b are difficult to cut. Therefore, a large current can flow even if the number of the wirings 22a and 22b is small, and the manufacturing cost of the semiconductor device 10 is reduced.
  • Table 1 shows the relationship between the planar distance of the wiring and the fusing current value in the example.
  • the plane distance of the wiring corresponds to the length of the wiring when the wiring is projected onto the plane.
  • the presence of gel corresponds to the case where the wiring is covered with gel. No gel corresponds to the case where the wiring is not covered with gel.
  • the wiring 22a is less likely to be concentrated in the first portion 18a of the lead 18 even if the number of the wirings 22a increases.
  • the wires 22b are less likely to be densely packed in the first portion 20a of the lead 20 even if the number of the wires 22b is increased. For this reason, possibility that wiring 22a and 22b will contact is reduced.
  • a larger current can be passed. Furthermore, a decrease in manufacturing yield of the semiconductor device 10 due to a mistake during bonding and poor adhesion can be suppressed.
  • the material of the semiconductor chip 14 includes a wide band gap semiconductor, it is possible to pass a larger current through the wirings 22a and 22b than the semiconductor chip 14 made of silicon. Therefore, effects such as avoidance of contact between the wirings and shortening of the wirings become remarkable.
  • the leads 18 and 20 are insulated from the die pad 12 by the insulating member 38.
  • the leads 18 and 20 can be supported by the die pad 12 via the insulating member 38. As a result, the structure of the semiconductor device 10 is stabilized.
  • a plurality of semiconductor chips are connected to a gate lead and a source lead via wires.
  • the wiring between one semiconductor chip and the source lead may cross the wiring between the other semiconductor chip and the gate lead.
  • the wirings 22a and 22b between the semiconductor chip 14 and the leads 18 and 20 are Do not cross.
  • the wirings 22a and 22b extend along the X direction, the wiring 22a and the wiring 22b are most separated from each other. As a result, the possibility of contact between the wiring 22a and the wiring 22b can be further reduced. The length of the wirings 22a and 22b can be minimized.
  • the distance between the semiconductor chip 14 and the lead 18 is shortened, so that the wiring 22a is It becomes even shorter.
  • the first portion 20a of the lead 20 protrudes toward the semiconductor chip 14 rather than the second portion 20b in the X direction, the distance between the semiconductor chip 14 and the lead 20 becomes short.
  • the wiring 22b is further shortened.
  • the semiconductor chip 14 When the semiconductor chip 14, the first portion 18 a of the lead 18, and the first portion 20 a of the lead 20 are covered with the resin portion 24, the semiconductor chip 14 and the leads 18 and 20 can be fixed to the resin portion 24.
  • FIG. 4 is a plan view schematically showing the semiconductor device according to the second embodiment.
  • FIG. 5 is a cross-sectional view of the semiconductor device taken along line VV in FIG.
  • FIG. 6 is a cross-sectional view of the semiconductor device taken along line VI-VI in FIG.
  • the semiconductor device 10a shown in FIGS. 4 to 6 includes a die pad 112 instead of the die pad 12, and has the same configuration as the semiconductor device 10 except that the insulating member 38 is not provided.
  • the die pad 112 has a chip mounting surface 112a on which the semiconductor chip 14 is mounted.
  • the die pad 112 has a notch 112 b corresponding to the shape of the first portion 18 a of the lead 18 and the first portion 20 a of the lead 20.
  • a gap is formed between the notch 112b, the first portion 18a of the lead 18, and the first portion 20a of the lead 20.
  • the surfaces of the first portion 18 a of the lead 18 and the first portion 20 a of the lead 20 are arranged on the same plane S as the surface of the semiconductor chip 14.
  • the same effect as the semiconductor device 10 can be obtained. Further, in the semiconductor device 10 a, the surfaces of the first portion 18 a of the lead 18 and the first portion 20 a of the lead 20 are arranged on the same plane S as the surface of the semiconductor chip 14. As a result, compared to the case where the surfaces of the leads 18 and 20 are arranged on a different plane from the surface of the semiconductor chip 14, the wiring 22 a between the semiconductor chip 14 and the lead 18 and the space between the semiconductor chip 14 and the lead 20 The wiring 22b becomes shorter.
  • FIG. 7 is a plan view schematically showing a semiconductor device according to the third embodiment.
  • the semiconductor device 10b shown in FIG. 7 has the same configuration as that of the semiconductor device 10 except that the number of semiconductor chips 14 is large.
  • the plurality of semiconductor chips 14 are arranged along the extending direction of the first portion 18 a of the lead 18 and the first portion 20 a of the lead 20.
  • the same effects as the semiconductor device 10 can be obtained.
  • the number of semiconductor chips 14 can be increased.
  • FIG. 8 is a plan view schematically showing a semiconductor device according to the fourth embodiment.
  • a semiconductor device 10c shown in FIG. 8 has a configuration similar to that of the semiconductor device 10b except that a wiring 122b is provided instead of the wiring 22b.
  • the wiring 122b is a bonding ribbon.
  • the semiconductor device 10c the same effect as the semiconductor device 10b is obtained.
  • FIG. 9 is a plan view schematically showing a semiconductor device according to the fifth embodiment.
  • a semiconductor device 10d shown in FIG. 9 includes a semiconductor chip 114 instead of the semiconductor chip 14, and has the same configuration as that of the semiconductor device 10 except that the lead 20 and the wiring 22b are not included.
  • the semiconductor chip 114 is a diode.
  • the semiconductor chip 114 has a front electrode and a back electrode.
  • the surface electrode of the semiconductor chip 114 is connected to the lead 18 through the wiring 22a.
  • the back electrode of the semiconductor chip 114 is connected to the lead 16 via the die pad 12.
  • the semiconductor device 10d the same effect as the semiconductor device 10 can be obtained.
  • the semiconductor devices 10, 10a to 10d include one or more semiconductor chips 14, one or more semiconductor chips 114, one or more wirings 22a, one or more wirings 22b, one or more The wiring 122b may be included.
  • the semiconductor chip 14 may include a horizontal transistor instead of the vertical transistor. In this case, no electrode pad is formed on the back surface of the semiconductor chip 14, and a further electrode pad such as a drain electrode pad or a collector electrode pad is formed on the surface of the semiconductor chip 14. Therefore, the semiconductor devices 10 and 10a to 10c do not need to include the die pad 12.
  • the semiconductor chip 14 is connected to the leads 16 through wiring.

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Abstract

　半導体デバイスは、少なくとも１つの半導体チップと、リードとを備える。リードは、半導体チップに配線を介して接続される第１の部分を有する。リードの第１の部分は、第１の方向に沿って延びており、半導体チップに対向配置される。

Description

半導体デバイス
　本発明は、半導体デバイスに関する。
　半導体デバイスの例として、ケース型の半導体デバイス及び樹脂封止型の半導体デバイスが知られている（非特許文献１参照）。樹脂封止型の半導体デバイスでは、ダイパッドに搭載された半導体チップが、ワイヤを介してリードに接続される。
「Ｃｕワイヤを中心としたワイヤボンディングの不良原因と信頼性向上・評価技術」株式会社技術情報協会出版、２０１１年７月２９日、ｐ．１６３、ｐ．２６３
　しかし、上記半導体デバイスでは、半導体チップがリードから遠いので、ワイヤが長くなる。ワイヤが長くなると、ワイヤの放熱性が低下するため、溶断電流が小さくなる。そのため、ワイヤに大きな電流を流すことができない。
　本発明は、半導体チップとリードとの間の配線が短い半導体デバイスを提供することを目的とする。
　本発明の一側面に係る半導体デバイスは、少なくとも１つの半導体チップと、前記少なくとも１つの半導体チップに配線を介して接続される第１の部分を有するリードと、を備え、前記リードの前記第１の部分が、第１の方向に沿って延びており、前記少なくとも１つの半導体チップに対向配置される。
　この半導体デバイスでは、半導体チップとリードの第１の部分とが対向配置されるので、半導体チップとリードとの間の配線が短くなる。
　上記半導体デバイスは、前記少なくとも１つの半導体チップが搭載されるチップ搭載面を有するダイパッドを更に備えてもよい。
　前記少なくとも１つの半導体チップが複数の半導体チップであり、前記複数の半導体チップが、前記第１の方向に沿って配列されてもよい。この場合、半導体チップの個数が増えても、半導体チップとリードとの間の配線同士が交差しない。
　前記リードの前記第１の部分の表面が、前記少なくとも１つの半導体チップの表面と同一平面上に配置されてもよい。この場合、半導体チップとリードとの間の配線が更に短くなる。
　前記少なくとも１つの半導体チップの材料が、ワイドバンドギャップ半導体を含んでもよい。この場合、シリコンからなる半導体チップに比べて大きな電流を配線に流すことが可能になる。
　前記リードが、前記第１の部分に接続されると共に前記第１の方向に沿って延びる第２の部分を有しており、前記第１の方向と交差する第２の方向において、前記第１の部分が、前記第２の部分よりも前記少なくとも１つの半導体チップに向かって突出してもよい。この場合、半導体チップとリードとの間の距離が短くなるので、配線が更に短くなる。
　上記半導体デバイスは、前記少なくとも１つの半導体チップ及び前記リードの前記第１の部分を覆う樹脂部を更に備えてもよい。これにより、半導体チップとリードとが樹脂部に固定され得る。
　本発明によれば、半導体チップとリードとの間の配線が短い半導体デバイスが提供され得る。
第１実施形態に係る半導体デバイスを模式的に示す平面図である。 図１のＩＩ－ＩＩ線に沿った半導体デバイスの断面図である。 図１のＩＩＩ－ＩＩＩ線に沿った半導体デバイスの断面図である。 第２実施形態に係る半導体デバイスを模式的に示す平面図である。 図４のＶ－Ｖ線に沿った半導体デバイスの断面図である。 図４のＶＩ－ＶＩ線に沿った半導体デバイスの断面図である。 第３実施形態に係る半導体デバイスを模式的に示す平面図である。 第４実施形態に係る半導体デバイスを模式的に示す平面図である。 第５実施形態に係る半導体デバイスを模式的に示す平面図である。
　以下、添付図面を参照しながら本発明の実施形態を詳細に説明する。なお、図面の説明において、同一又は同等の要素には同一符号を用い、重複する説明を省略する。図１～図９にはＸＹＺ直交座標系が示されている。
（第１実施形態）
　図１は、第１実施形態に係る半導体デバイスを模式的に示す平面図である。図２は、図１のＩＩ－ＩＩ線に沿った半導体デバイスの断面図である。図３は、図１のＩＩＩ－ＩＩＩ線に沿った半導体デバイスの断面図である。図１～図３に示される半導体デバイス１０は、樹脂封止型の半導体デバイスである。半導体デバイス１０は、複数の半導体チップ１４と、第１のリード１８とを備える。
　半導体デバイス１０は、半導体チップ１４が搭載されるチップ搭載面１２ａを有するダイパッド１２を備え得る。ダイパッド１２は、半導体チップ１４と電気的に接続され得る。ダイパッド１２は例えば板状を呈している。チップ搭載面１２ａは、例えば長方形である。ダイパッド１２の材料の例は、銅（Ｃｕ）及び銅合金等の金属を含む。ダイパッド１２には、板厚方向にダイパッド１２を貫通する貫通孔２６が形成され得る。貫通孔２６は、例えば螺子によって半導体デバイス１０を他の部材（例えばヒートシンク等）に固定する際に、螺子を通すための孔である。
　半導体デバイス１０は、第２のリード１６及び第３のリード２０を備えてもよい。リード１６，１８，２０は、Ｙ方向（第１の方向）に沿って延びており、Ｘ方向（第１の方向に交差する第２の方向）に沿って配列される。リード１６は、リード１８，２０の間に位置する。リード１６，１８、２０及びダイパッド１２は、リードフレームを構成し得る。半導体デバイス１０は、例えば電源等に使用されるパワー半導体デバイスである。半導体デバイス１０のパッケージ形態の例は一般的なＴＯシリーズである。ＴＯシリーズの例はＴＯ－２４７、ＴＯ－２２０、ＴＯ－２６３（Ｄ２―ＰＡＫ）、ＴＯ－２５２（Ｄ－ＰＡＫ）を含む。
　リード１８は、半導体チップ１４に配線２２ａを介して接続される第１の部分１８ａを有する。第１の部分１８ａは、Ｙ方向に沿って延びており、半導体チップ１４に対向配置される。第１の部分１８ａは、Ｙ方向に沿った半導体チップ１４の側面に対向配置され得る。リード１８は、第１の部分１８ａに接続される第２の部分１８ｂを有してもよい。第２の部分１８ｂはＹ方向に沿って延びている。第１の部分１８ａの幅は第２の部分１８ｂの幅よりも広くなっていてもよい。第１の部分１８ａは、Ｘ方向において、第２の部分１８ｂよりも半導体チップ１４に向かって突出してもよい。
　リード２０は、半導体チップ１４に複数の配線２２ｂを介して接続される第１の部分２０ａを有する。半導体チップ１４は、単一の配線２２ｂを介して第１の部分２０ａに接続されてもよい。第１の部分２０ａは、Ｙ方向に沿って延びており、半導体チップ１４に対向配置される。第１の部分２０ａは、Ｙ方向に沿った半導体チップ１４の側面に対向配置され得る。リード２０は、第１の部分２０ａに接続される第２の部分２０ｂを有してもよい。第２の部分２０ｂはＹ方向に沿って延びている。第１の部分２０ａの幅は第２の部分２０ｂの幅よりも広くなっていてもよい。第１の部分２０ａは、Ｘ方向において、第２の部分２０ｂよりも半導体チップ１４に向かって突出してもよい。
　リード１８の第１の部分１８ａは、リード２０の第１の部分２０ａに対向配置される。半導体チップ１４は、リード１８の第１の部分１８ａとリード２０の第１の部分２０ａとの間に配置される。半導体チップ１４は、Ｙ方向に沿って配列され得る。リード１８の第２の部分１８ｂは、リード２０の第２の部分２０ｂに対向配置され得る。配線２２ａ及び２２ｂはＸ方向に沿って延びてもよい。
　半導体チップ１４は、チップ搭載面１２ａの所定位置に搭載される。半導体チップ１４の例は、ＭＯＳ－ＦＥＴ、絶縁ゲートバイポーラトランジスタ（ＩＧＢＴ）等のトランジスタ、ＰＮ接合ダイオード、ショットキーバリアダイオード等のダイオードを含む。半導体チップ１４は、鉛入り金属半田、鉛を含まない金属半田又は導電性樹脂等を含む材料から構成される接着層４０を介してチップ搭載面１２ａに実装され得る。半導体チップ１４の材料の例は、ワイドバンドギャップ半導体、シリコンその他の半導体を含む。ワイドバンドギャップ半導体は、シリコンのバンドギャップよりも大きいバンドギャップを有する。ワイドバンドギャップ半導体の例は、シリコンカーバイド（ＳｉＣ）、窒化ガリウム（ＧａＮ）、ダイヤモンドを含む。
　半導体チップ１４は、電極パッドＧＰ及びＳＰを有し得る。電極パッドＧＰは、配線２２ａを介してリード１８に接続される。電極パッドＳＰは、配線２２ｂを介してリード２０に接続される。半導体チップ１４がＭＯＳ－ＦＥＴを含む場合、電極パッドＧＰはゲート電極パッドに対応し、電極パッドＳＰはソース電極パッドに対応する。半導体チップ１４がＩＧＢＴを含む場合、電極パッドＧＰはゲート電極パッドに対応し、電極パッドＳＰはエミッタ電極パッドに対応する。半導体チップ１４の裏面全体には、例えばドレイン電極パッド又はコレクタ電極パッド等の更なる電極パッドが形成され得る。
　半導体デバイス１０は、ダイパッド１２とリード１８及び２０との間に配置された絶縁部材３８を備え得る。絶縁部材３８は、Ｚ方向（第１の方向及び第２の方向と交差する第３の方向）においてダイパッド１２とリード１８の第１の部分１８ａ及びリード２０の第１の部分２０ａとの間に介在する。絶縁部材３８は、例えば絶縁基板又は絶縁層である。絶縁部材３８の材料の例は、エポキシ樹脂等の樹脂又はセラミックスを含む。ダイパッド１２と絶縁部材３８とリード１８及び２０とは互いに接着剤により接続され得る。
　リード１６の内側端部は、ダイパッド１２に機械的に一体的に連結されている。ダイパッド１２は導電性を有するので、リード１６とダイパッド１２とは電気的に接続されている。リード１６の材料の例はダイパッド１２の材料と同じ材料を含む。
　半導体チップ１４がＭＯＳ－ＦＥＴを含む場合、リード１６はドレイン電極端子に対応し、リード１８はゲート電極端子に対応し、リード２０はソース電極端子に対応する。半導体チップ１４がＩＧＢＴを含む場合、リード１６はコレクタ電極端子に対応し、リード１８はゲート電極端子に対応し、リード２０はエミッタ電極端子に対応する。リード１８，２０の材料の例は、銅及び銅合金等の金属を含む。配線２２ａ及び２２ｂは、ワイヤ又はボンディングリボンであってもよい。配線２２ａ及び２２ｂの材料の例は、アルミニウム、金、銅等の金属を含む。配線２２ａ及び２２ｂは、例えば超音波又は加圧等を用いたワイヤボンディングによりリード１８，２０及び半導体チップ１４に接続される。
　ダイパッド１２、半導体チップ１４、リード１８の第１の部分１８ａ及びリード２０の第１の部分２０ａは、樹脂部２４によって覆われ得る。リード１６，１８，２０の内側端部は、樹脂部２４に挿入される。リード１６，１８，２０のうち樹脂部２４の内側の部分は、いわゆるインナーリード部である。リード１６，１８，２０のうち樹脂部２４の外側の部分は、アウターリード部である。樹脂部２４の外形形状の一例は、略直方体である。樹脂部２４の材料の例は、ポリフェニレンサルファイド樹脂（ＰＰＳ樹脂）、液晶ポリマー等の熱可塑性樹脂を含む。樹脂部２４は、ダイパッド１２及び半導体チップ１４を熱可塑性樹脂でモールドすることによって形成され得る。樹脂部２４には、ダイパッド１２の貫通孔２６の中心軸線を中心軸線とする貫通孔２８が形成されている。貫通孔２８は、貫通孔２６と同様に螺子止めなどの際などに螺子が通される孔である。貫通孔２８の直径は、貫通孔２６の直径より小さい。
　半導体デバイス１０では、半導体チップ１４とリード１８の第１の部分１８ａとが対向配置されるので、半導体チップ１４とリード１８との間の配線２２ａが短くなる。同様に、半導体チップ１４とリード２０の第１の部分２０ａとが対向配置されるので、半導体チップ１４とリード２０との間の配線２２ｂが短くなる。配線２２ａ及び２２ｂの長さが短くなると、配線２２ａ及び２２ｂの放熱性が向上するため、溶断電流が大きくなる。よって、大きな電流が流れても配線２２ａ及び２２ｂが切れ難くなる。そのため、配線２２ａ及び２２ｂの本数が少なくても大きな電流を流すことが可能になるので、半導体デバイス１０の製造コストが低減される。
　表１は、実施例における配線の平面距離と溶断電流値との関係を示す。配線の平面距離は、配線を平面に投影した場合の配線の長さに対応する。ゲル有は配線がゲルで覆われている場合に対応する。ゲル無は配線がゲルで覆われていない場合に対応する。
Figure JPOXMLDOC01-appb-T000001
　表１に示されるように、配線の長さが長くなるに連れて溶断電流が徐々に小さくなる傾向があることが分かる。
　さらに、リード１８の第１の部分１８ａの長さを長くすると、配線２２ａの本数が多くなっても、リード１８の第１の部分１８ａにおいて配線２２ａが密集し難い。リード２０の第１の部分２０ａの長さを長くすると、配線２２ｂの本数が多くなっても、リード２０の第１の部分２０ａにおいて配線２２ｂが密集し難い。このため、配線２２ａ及び２２ｂ同士が接触する可能性が低減される。配線２２ａ及び２２ｂの本数を増やすことによって、より大きな電流を流すことが可能になる。さらに、ボンディング時のミス及び接着不良に起因する半導体デバイス１０の製造歩留まりの低下が抑制され得る。
　半導体チップ１４の材料がワイドバンドギャップ半導体を含む場合、シリコンからなる半導体チップ１４に比べて大きな電流を配線２２ａ及び２２ｂに流すことが可能になる。そのため、配線同士の接触の回避、配線を短くすること等の効果が顕著になる。
　半導体デバイス１０が絶縁部材３８を備える場合、リード１８，２０が絶縁部材３８によってダイパッド１２から絶縁される。リード１８，２０は、絶縁部材３８を介してダイパッド１２により支持され得る。その結果、半導体デバイス１０の構造が安定化される。
　通常、複数の半導体チップは、ゲート用のリードとソース用のリードにワイヤを介して接続される。この場合、１つの半導体チップとソース用のリードとの間の配線が、もう１つの半導体チップとゲート用のリードとの間の配線と交差するおそれがある。一方、半導体デバイス１０では、複数の半導体チップ１４がＹ方向に沿って配列される場合、半導体チップ１４の個数が増えても、半導体チップ１４とリード１８及び２０との間の配線２２ａ及び２２ｂ同士が交差しない。
　配線２２ａ及び２２ｂがＸ方向に沿って延びると、配線２２ａと配線２２ｂとが互いに最も離間する。その結果、配線２２ａと配線２２ｂとが接触する可能性を更に低減できる。配線２２ａ及び２２ｂの長さは最小化され得る。
　リード１８の第１の部分１８ａが、Ｘ方向において、第２の部分１８ｂよりも半導体チップ１４に向かって突出する場合、半導体チップ１４とリード１８との間の距離が短くなるので、配線２２ａが更に短くなる。同様に、リード２０の第１の部分２０ａが、Ｘ方向において、第２の部分２０ｂよりも半導体チップ１４に向かって突出する場合、半導体チップ１４とリード２０との間の距離が短くなるので、配線２２ｂが更に短くなる。
　半導体チップ１４、リード１８の第１の部分１８ａ及びリード２０の第１の部分２０ａが樹脂部２４によって覆われると、半導体チップ１４とリード１８，２０とが樹脂部２４に固定され得る。
（第２実施形態）
　図４は、第２実施形態に係る半導体デバイスを模式的に示す平面図である。図５は、図４のＶ－Ｖ線に沿った半導体デバイスの断面図である。図６は、図４のＶＩ－ＶＩ線に沿った半導体デバイスの断面図である。図４～図６に示される半導体デバイス１０ａは、ダイパッド１２に代えてダイパッド１１２を備え、絶縁部材３８を備えないこと以外は半導体デバイス１０と同様の構成を備える。
　ダイパッド１１２は半導体チップ１４が搭載されるチップ搭載面１１２ａを有する。ダイパッド１１２は、リード１８の第１の部分１８ａ及びリード２０の第１の部分２０ａの形状に対応する切欠き部１１２ｂを有する。切欠き部１１２ｂとリード１８の第１の部分１８ａ及びリード２０の第１の部分２０ａとの間には、隙間が形成される。リード１８の第１の部分１８ａ及びリード２０の第１の部分２０ａの表面は、半導体チップ１４の表面と同一平面Ｓ上に配置される。
　半導体デバイス１０ａでは半導体デバイス１０と同様の作用効果が得られる。さらに、半導体デバイス１０ａでは、リード１８の第１の部分１８ａ及びリード２０の第１の部分２０ａの表面が、半導体チップ１４の表面と同一平面Ｓ上に配置される。その結果、リード１８，２０の表面が半導体チップ１４の表面と異なる平面上に配置される場合に比べて、半導体チップ１４とリード１８との間の配線２２ａ、半導体チップ１４とリード２０との間の配線２２ｂが短くなる。
（第３実施形態）
　図７は、第３実施形態に係る半導体デバイスを模式的に示す平面図である。図７に示される半導体デバイス１０ｂは、半導体チップ１４の個数が多いこと以外は半導体デバイス１０と同様の構成を備える。複数の半導体チップ１４は、リード１８の第１の部分１８ａ及びリード２０の第１の部分２０ａの延在方向に沿って配列される。半導体デバイス１０ｂでは半導体デバイス１０と同様の作用効果が得られる。さらに、リード１８の第１の部分１８ａ及びリード２０の第１の部分２０ａの長さを長くすることによって、半導体チップ１４の個数を増やすことが可能になる。
（第４実施形態）
　図８は、第４実施形態に係る半導体デバイスを模式的に示す平面図である。図８に示される半導体デバイス１０ｃは、配線２２ｂに代えて配線１２２ｂを備えること以外は半導体デバイス１０ｂと同様の構成を備える。配線１２２ｂはボンディングリボンである。半導体デバイス１０ｃでは半導体デバイス１０ｂと同様の作用効果が得られる。
（第５実施形態）
　図９は、第５実施形態に係る半導体デバイスを模式的に示す平面図である。図９に示される半導体デバイス１０ｄは、半導体チップ１４に代えて半導体チップ１１４を備え、リード２０及び配線２２ｂを備えないこと以外は半導体デバイス１０と同様の構成を備える。半導体チップ１１４はダイオードである。半導体チップ１１４は、表面電極及び裏面電極を有する。半導体チップ１１４の表面電極は、配線２２ａを介してリード１８に接続される。半導体チップ１１４の裏面電極は、ダイパッド１２を介してリード１６に接続される。半導体デバイス１０ｄでは半導体デバイス１０と同様の作用効果が得られる。
　以上、本発明の好適な実施形態について詳細に説明したが、本発明は上記実施形態に限定されない。
　例えば、半導体デバイス１０，１０ａ～１０ｄは、１つ又は複数の半導体チップ１４、１つ又は複数の半導体チップ１１４、１つ又は複数の配線２２ａ、１つ又は複数の配線２２ｂ、１つ又は複数の配線１２２ｂを含んでもよい。
　半導体チップ１４は、縦型トランジスタに代えて横型トランジスタを含んでもよい。この場合、半導体チップ１４の裏面には電極パッドが形成されず、半導体チップ１４の表面に例えばドレイン電極パッド又はコレクタ電極パッド等の更なる電極パッドが形成される。そのため、半導体デバイス１０，１０ａ～１０ｃは、ダイパッド１２を備えなくてもよい。半導体チップ１４は、配線を介してリード１６に接続される。
　１０，１０ａ，１０ｂ，１０ｃ，１０ｄ…半導体デバイス、１２，１１２…ダイパッド、１２ａ，１１２ａ…チップ搭載面、１４，１１４…半導体チップ、１８…リード、１８ａ…リードの第１の部分、１８ｂ…リードの第２の部分、２２ａ…配線、２４…樹脂部。

Claims (7)

  1. 　少なくとも１つの半導体チップと、
    　前記少なくとも１つの半導体チップに配線を介して接続される第１の部分を有するリードと、
    を備え、
    　前記リードの前記第１の部分が、第１の方向に沿って延びており、前記少なくとも１つの半導体チップに対向配置される、半導体デバイス。
  2. 　前記少なくとも１つの半導体チップが搭載されるチップ搭載面を有するダイパッドを更に備える、請求項１に記載の半導体デバイス。
  3. 　前記少なくとも１つの半導体チップが複数の半導体チップであり、
    　前記複数の半導体チップが、前記第１の方向に沿って配列される、請求項１又は２に記載の半導体デバイス。
  4. 　前記リードの前記第１の部分の表面が、前記少なくとも１つの半導体チップの表面と同一平面上に配置される、請求項１～３のいずれか一項に記載の半導体デバイス。
  5. 　前記少なくとも１つの半導体チップの材料が、ワイドバンドギャップ半導体を含む、請求項１～４のいずれか一項に記載の半導体デバイス。
  6. 　前記リードが、前記第１の部分に接続されると共に前記第１の方向に沿って延びる第２の部分を有しており、
    　前記第１の方向と交差する第２の方向において、前記第１の部分が、前記第２の部分よりも前記少なくとも１つの半導体チップに向かって突出している、請求項１～５のいずれか一項に記載の半導体デバイス。
  7. 　前記少なくとも１つの半導体チップ及び前記リードの前記第１の部分を覆う樹脂部を更に備える、請求項１～６のいずれか一項に記載の半導体デバイス。
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