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  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
  • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
  • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
  • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
• • H—ELECTRICITY
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  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D8/00—Diodes
  • H10D8/60—Schottky-barrier diodes 
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
  • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
  • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
  • H10D62/109—Reduced surface field [RESURF] PN junction structures
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
  • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
  • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
  • H10D62/8325—Silicon carbide
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/60—Electrodes characterised by their materials
  • H10D64/64—Electrodes comprising a Schottky barrier to a semiconductor
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D8/00—Diodes

Definitions

• the present invention relates microelectronic devices and more particularly to edge termination for silicon carbide devices.
• High voltage silicon carbide (SiC) Schottky diodes which can handle voltages between, for example, about 600V and about 2.5 kV, are expected to compete with silicon PIN diodes fabricated with similar voltage ratings. Such diodes may handle as much as about 100 amps or more of current, depending on their active area. High voltage Schottky diodes have a number of important applications, particularly in the field of power conditioning, distribution and control.
• SiC Schottky diode An important characteristic of a SiC Schottky diode in such applications is its switching speed. Silicon-based PIN devices typically exhibit relatively poor switching speeds. A silicon PIN diode may have a maximum switching speed of approximately 20 kHz, depending on its voltage rating. In contrast, silicon carbide-based devices are theoretically capable of much higher switching speeds, for example, in excess of about 100 times better than silicon, hi addition, silicon carbide devices may be capable of handling a higher current density than silicon devices.
• a conventional SiC Schottky diode structure has an n-type SiC substrate on which an n " epitaxial layer, which functions as a drift region, is formed.
• the device typically includes a Schottky contact formed directly on the n " layer.
• a p- type JTE (junction termination extension) region Surrounding the Schottky contact is a p- type JTE (junction termination extension) region that is typically formed by ion implantation.
• the implants may be aluminum, boron, or any other suitable p-type dopant.
• the purpose of the JTE region is to reduce or prevent the electric field crowding at the edges, and to reduce or prevent the depletion region from interacting with the surface of the device. Surface effects may cause the depletion region to spread unevenly, which may adversely affect the breakdown voltage of the device.
• a channel stop region may also be formed by implantation of n-type dopants such as Nitrogen or Phosphorus in order to prevent the depletion region from extending to the edge of the device.
• a p-type epitaxy guard ring termination for a SiC Schottky Barrier Diode is described in "The Guard-Ring Termination for High- Voltage SiC Schottky Barrier Diodes" by Ueno et al, IEEE Electron Device Letters, Vol. 16, No. 7, July, 1995, pp. 331-332. Additionally, other termination techniques are described in published PCT Application No. WO 97/08754 entitled "SiC Semiconductor Device Comprising A PN Junction With A Voltage Absorbing Edge.”
• JTE junction termination extension
• MFGR floating guard rings
• FP field plates
• FP is also a conventional technique for edge termination of a device and may be cost- effective.
• conventional FP devices high fields are supported by the oxide layer under the metal field plate. This technique performs well for silicon devices where the highest field in the semiconductor is relatively low.
• the electric fields in the blocking state may be very high ( ⁇ 2 MV/cm) which multiplies by a factor of 2.5 at the oxide- semiconductor interface. This leads to very high oxide fields and may result in long-term reliability problems. Thus, FP may be unsuitable for use in SiC devices.
• Multiple floating guard rings in addition to JTE has been proposed as a technique for reducing the sensitivity of the JTE to implant dose variation.
• MFGR may also be a cost-effective method of edge termination because it may use fewer fabrication steps than JTE. However, MFGR may be very sensitive to surface charges in the oxide-semiconductor interface.
• Figure IA illustrates a conventional MFGR device where the spacing between the p-type SiC guard rings is illustrated as constant for simplicity.
• the depletion region starts at the main junction and expands both laterally and vertically.
• the potential of the first guard ring gets pinned to that of the main junction.
• the punch-through side of the guard ring injects a small amount of holes into the n-region. This lost charge is replaced by the depletion of the n charge from the outer edge of the guard ring.
• each floating guard ring supports the same electric fields, the spacing between the guard rings may vary.
• the spacing between the main junction and the inner-most guard ring may be the smallest, and the spacing at the outer-most guarding may be the largest.
• MOS metal-oxide- semiconductor
• field oxides often typically have lower quality when compared to thermally grown gate oxides and plasma processing steps may result in higher oxide charges.
• the surface of the lightly doped n- layer turns into n + regions, which compresses the equi-potential lines. This results in a very high field at the oxide-semiconductor interface and, therefore, reduces the effectiveness of the floating guard rings that may result in a reduction of blocking voltage for the devices.
• Breakdown walk-out refers to a phenomenon where the breakdown voltage starts at a first value and increases with time and bias. This problem may be even greater in silicon carbide devices because the field oxides are generally deposited. Deposited oxides, typically, have inferior characteristics to those of thermally grown layers, and the oxide-semiconductor interface in a silicon carbide device has much greater charge density compared to that of a silicon device.
• n-type semiconductor layer 10 has a main junction 12 and a series of floating guard rings 14 formed therein.
• An oxide layer 16 is provided on the semiconductor layer 10 and openings are provided in the oxide layer 16.
• the offset field plates 18 are provided in the openings to contact the floating guard rings 14 and to extend onto the oxide layer 16.
• Offset Field Plate-Floating Guard Ring structure has each field plate contacting each guard ring separately and the edge of the guard ring should not overlap with the edge of the next guard ring.
• each guard ring may need to be enlarged, and the alignment tolerance of the guard rings should be less than 0.25 ⁇ m.
• Step coverage may also be another issue with the Offset Field Plate-Floating Guard Ring structure because the thickness of the oxide that may be needed.
• the quality of the oxide may be important in achieving acceptable results as it is the oxide that supports the field or voltages. Oxides in silicon carbide devices, generally have lower quality than that available in silicon devices. Accordingly, the Offset Field Plate-Floating Guard Ring structure may not be practical for silicon carbide devices.
• Guard ring edge termination structures suitable for use in silicon carbide devices are discussed in commonly assigned United States Patent No. 7,026,650 issued on April 11, 2006 to Ryu et al. entitled Multiple floating guard ring edge termination for silicon carbide devices, the disclosure of which is hereby incorporated herein by reference in its entirety.
• a surface charge compensation layer such as a thin p-type layer, is provided in addition to the multiple floating guard rings.
• the surface charge compensation layer may be used to at least partially neutralize the effects of charges at oxide-semiconductor interfaces in the silicon carbide devices.
• Some embodiments of the present invention provide edge termination structures for semiconductor devices including a plurality of spaced apart concentric floating guard rings in a semiconductor layer that at least partially surround a semiconductor junction.
• the spaced apart concentric floating guard rings have a highly doped portion and a lightly doped portion.
• the semiconductor device may be a silicon carbide semiconductor device
• the semiconductor layer may be a silicon carbide layer
• the semiconductor junction may be a silicon carbide-based semiconductor junction.
• the highly doped portion of the floating guard rings extend a first distance into the silicon carbide layer and the lightly doped portion of the floating guard rings extend a second distance into the silicon carbide layer.
• the first and second distances may be the same.
• the first distance may be less than the second distance.
• the first distance may be about 0.5 ⁇ m and the second distance is about 0.8 ⁇ m.
• the lightly doped portion of the floating guard rings may have a first doping concentration in a portion adjacent the highly doped portion of the floating guard rings and a second doping concentration, greater than the first doping concentration, beneath the highly doped portion of the floating guard rings.
• the first doping concentration may be about 1.0 X IO 17 and the second doping concentration may be about 1.4x 10 ⁇ .
• the second doping concentration may be retrograde profile toward the SiO 2 /SiC interface.
• the highly doped portion of the floating guard rings may have a dopant concentration of from about 5.0xl0 18 cm "3 to about
• 1.0x10 20 cm "3 and the lightly doped portions of the floating guard rings may have a dopant concentration of from about 5.OxIO 16 cm '3 to about 5.0xl0 17 cm '3 .
• the dopant concentrations may decrease from a main junction of the device to a periphery of the device.
• the dopant concentration of the lightly doped portion of the guard rings may decrease from the main junction of the device to the periphery of the device providing a gradient in the lightly doped portions of the guard rings.
• the highly doped portions and the lightly doped portions extend a distance of from about 0.3 ⁇ m to about 0.8 ⁇ m into the silicon carbide layer.
• the floating guard rings may be uniformly spaced, non-uniformly spaced and/or combinations of uniformly and non- uniformly spaced.
• the plurality of floating guard rings may include from about 2 to about 100 guard rings.
• the silicon carbide layer may be an n- type silicon carbide layer and the plurality of spaced apart guard rings may be p-type silicon carbide.
• the silicon carbide layer may be a p- type silicon carbide layer and the plurality of spaced apart guard rings may be n-type silicon carbide.
• Figure 1 is a diagram of a conventional MFGR structure and the ideal field profile of that structure.
• Figure 2 is a diagram of a conventional MFGR structure with offset field plates.
• Figure 3 is a cross section of an edge termination structure according to some embodiments of the present invention.
• Figures 4A through 4D are cross sections illustrating processing steps in the fabrication of edge termination structures according to some embodiments of the present invention.
• Figure 5 is a plan view of a double guard ring mask for ion implantation according to some embodiments of the present invention.
• Figure 6 is a blocking histogram for diodes with robust guard ring termination
• Figure 7 is a graph illustrating representative reverse IV curves for diodes with robust guard ring termination and double guard ring termination according to some embodiments of the present invention.
• Figure 8 is a graph illustrating simulations of SiC JBS diode blocking characteristics for diodes with robust guard ring termination and double guard ring termination according to some embodiments of the present invention.
• Figures 9 and 10 are graphs illustrating potential distribution of JBS with double guard ring termination and robust guard ring termination at 680V, respectively, according to some embodiments of the present invention.
• Figures 11 and 12 are graphs illustrating electrical field distribution comparisons underneath termination junctions, and at the SiO 2 /SiC interface, respectively, according to some embodiments of the present invention.
• Figure 13 is a cross section illustrating an edge termination structure according to some embodiments of the present invention.
• Figure 14 is a graph illustrating electric field characteristics in accordance with some embodiments of the present invention illustrated in Figure 13.
• Figure 15 is a graph illustrating electric field characteristics in accordance with some embodiments of the present invention illustrated in Figure 13.
• relative terms such as “lower” or “bottom” and “upper” or “top,” may be used herein to describe one element's relationship to another elements as illustrated in the Figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. For example, if the device in one of the figures is turned over, elements described as being on the “lower” side of other elements would then be oriented on “upper” sides of the other elements. The exemplary term “lower”, can therefore, encompasses both an orientation of “lower” and “upper,” depending of the particular orientation of the figure.
• Example embodiments of the invention are described herein with reference to cross- section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, may be expected.
• the disclosed example embodiments of the invention should not be construed as limited to the particular shapes of regions illustrated herein unless expressly so defined herein, but are to include deviations in shapes that result, for example, from manufacturing.
• an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region.
• a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place.
• the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the invention, unless expressly so defined herein.
• embodiments of the present invention may provide improved edge termination of semiconductor devices, such as P-N, Schottky, PiN or other such semiconductor devices.
• semiconductor devices such as P-N, Schottky, PiN or other such semiconductor devices.
• Particular embodiments of the present invention provide edge termination for silicon carbide (SiC) devices.
• SiC silicon carbide
• embodiments of the present invention may be utilized as edge termination for SiC Schottky diodes, junction barrier Schottky (JBS) diodes, PiN diodes, thyristors, transistors, or other such SiC devices without departing from the scope of the present invention.
• JBS junction barrier Schottky
• some embodiments of the present invention provide an improved edge termination for high voltage silicon carbide devices using double guard ring termination ("double GR termination”) as will be discussed in detail below with respect to Figures 3 through 15.
• Double GR termination double guard ring termination
• Commonly assigned United States Patent No. 7,026,650 to Ryu et al. (hereinafter "the '650 patent), which has been incorporated herein by reference above, discusses robust guard ring termination ("robust GR termination”) used in conjuction with SiC power devices.
• a surface charge compensation layer such as a thin p-type layer, is provided in addition to the multiple floating guard rings.
• the guard ring termination structure discussed in the '650 patent has shown higher blocking capabilities than the conventional guard ring termination, including junction termination extension (JTE). However, the maximum breakdown voltage may still be less than the value predicted in theory.
• some embodiments of the present invention provide double guard ring (DGR) termination structures for highly doped and lightly doped implantations, respectively.
• the highly doped portion of the guard ring may be achieved by Aluminum (Al) implants, while the lightly doped portion of the guard ring may be achieved by Boron (B) implant.
• Providing both highly doped and lightly doped implants in accordance with some embodiments of the present invention may provide a doping gradient from the main junction to the termination edge such that the electrical field can be further reduced in devices according to some embodiments of the present invention.
• the mean doping concentration of the guard ring is greater at the main junction of the device and decreases toward the periphery of the device.
• the doping gradient in accordance with some embodiments of the present invention is especially useful for Boron in SiC, which can diffuse during a high temperature activation process. Details with respect to some embodiments of the present invention will be discussed further herein with respect to Figures 3 through 15. [0048] Referring now to Figure 3, a cross section of a silicon carbide semiconductor device 20 illustrating some embodiments of the present invention will be discussed.
• a silicon carbide layer 30 such as a lightly doped n-type silicon carbide layer, has formed therein a main junction 32, for example, of p-type silicon carbide, and a plurality of double guard rings DGRl, DGR2, DGR3 and DGR4, such as p-type silicon carbide floating guard rings, in accordance with some embodiments of the present invention.
• a main junction 32 for example, of p-type silicon carbide
• a plurality of double guard rings DGRl, DGR2, DGR3 and DGR4 such as p-type silicon carbide floating guard rings, in accordance with some embodiments of the present invention.
• four double guard rings DGRl, DGR2, DGR3 and DGR4 are illustrated in Figure 3, embodiments of the present invention are not limited to this configuration. Any number of double guard rings may be included without departing from the scope of the present invention.
• an insulating layer 26 such as an oxide layer, is provided on the silicon carbide layer 30.
• the insulating layer 26 may be a deposited or grown oxide and may be fabricated utilizing techniques known to those of skill in the art.
• the insulating layer 26 may be an oxide, such as SiO 2 , a nitride, such as Si 3 N 4 , an oxide-nitride-oxide structure and/or an oxynitride or organic films such as a polyimide layer.
• the double guard rings DGRl, DGR2, DGR3 and DGR4 each include first and second portions 34 and 36, respectively.
• the first and second portions 34 and 36 of the double guard rings DGRl, DGR2, DGR3 and DGR4 may be p-type silicon carbide.
• the first and second guard rings DGRl and DGR2 are illustrated as having a distance Dl between them equal to zero, embodiments of the present invention are not limited to this configuration. The distance between the first and second guard rings DGRl and DGR2 can be greater than zero without departing from the scope of the present application.
• the distances Dl, D2 and D3 may all be different distances without departing from the scope of the present invention.
• the lightly doped portion (p " ) 36 may be from about 5.0X10 16 to about 5.OxIO 17 cm “3 .
• n + " or "p + " refer to regions that are defined by higher carrier concentrations than are present in adjacent or other regions of the same or another layer or substrate.
• the highly doped portions 34 and the lightly doped portions 36 of the double guard rings DGRl, DGR2, DGR3 and DGR4 may extend a distance D4 from about 0.3 to about 0.8 ⁇ m into the silicon carbide layer 30.
• Figure 1 illustrates that the highly doped portion 34 and the lightly doped portion 36 extend into the substrate a same distance D4, embodiments of the present invention are not limited to this configuration. Alternative embodiments will be discussed further below with respect to Figure 13.
• the highly doped 34 and/or lightly doped 36 portions of the double guard rings DGRl, DGR2, DGR3 and DGR4 may have higher doping concentrations closer to the main junction 32 of the device 20 and lower doping concentrations at the periphery of the device 20.
• Aluminum ions are implanted to achieve the highly doped portions 34 and Boron ions are implanted to achieve the lightly doped portions 36.
• Providing the lightly doped portions 36 in a second guard ring adjacent the highly doped guard ring allows a doping gradient from the main junction 32 to the termination edge to be provided, especially for Boron in SiC which can diffuse during high temperature activation process. Thus, the electric field may be further reduced in accordance with some embodiments of the present invention.
• the oxide-semiconductor interface is expected to have from about 1.OxIO 12 to about 2.OxIO 12 cm "3 of positive charge.
• the surface of the surface low does portions 36 of the double guard rings DGRl, DGR2, DGR3 and DGR4 will, typically, be depleted by the positive surface charges, and the negative charges in the depletion region low does portions 36 of the double guard rings DGRl, DGR2, DGR3 and DGR4 will reduce the E-field lines originating from the oxide interface charges, and possibly neutralize the negative effects of the positive interface charges.
• the double guard rings 34/36 maybe uniformly spaced, non-uniformly spaced or combinations of uniformly and non-uniformly spaced.
• the lengths of Dl, D2, D3 and the like may vary and may not be constant.
• from about 1 to about 100 guard rings 34/36 may be provided.
• the guard rings 34/36 may extend a distance of from about lO ⁇ m to about lOOO ⁇ m from the main junction of the device.
• the lightly doped portions 36 may be formed before or after formation of the highly doped portions 34.
• Both the highly doped portion 34 and the lightly doped portion 36 may be provided by, for example, ion implantation, or other techniques known to those of skill in the art.
• the lightly doped portion 34 or the highly doped portion 36 may be an epitaxially grown layer of SiC or deposited layer of SiC that is formed on the layer 30 and, in the case of the regions, patterned to provide the desired surface charge compensation regions and/or layers.
• the guard rings may be formed prior to formation of the SiC layer or after formation of the SiC layer.
• edge termination techniques may be utilized with other devices and/or junction types, such as Schottky junctions.
• some embodiments of the present invention provide a novel edge termination structure including double guard rings for the high and low implant doses to further reduce the electrical field.
• some embodiments of the present invention provide a gradient of the lightly doped portion 34 of the guard ring, which can further improve the blocking capability of power devices.
• the lightly doped portion 34 may have a wide range of tolerance in processing such as misalignment, opening definition, and the like.
• Double guard ring termination structures according to some embodiments of the present invention maybe processed using existing processes and, therefore, may not increase the processing steps and difficulty of processing these devices.
• a higher blocking capability provided by devices according to some embodiments of the present invention may result in the improvement in other parameters of power devices, such as reducing on-resistance by a thinner drift layer.
• a thinner drift layer may reduce the power device die size further to achieve a higher die yield.
• a silicon carbide layer 30 has formed in it a junction 32 and spaced apart highly doped portions 34 of the double guard ring structure.
• Such regions may be formed, for example, by ion implantation into a silicon carbide substrate and/or epitaxial layer.
• aluminum ions having a doping concentration of from about 5.OxIO 18 to about 1.OxIO 2 cm "3 may be implanted into the silicon carbide layer 30 to provide the highly doped portions 34 illustrated in Figure 4A.
• a mask layer 100 may be formed and patterned on the silicon carbide layer 30 and may correspond to the junction 32 and highly doped portions of the guard ring 34.
• the mask layer 100 may be made of conventional mask materials and may, for example, be patterned using conventional photolithography or other such techniques known to those of skill in the art.
• the mask layer 100 opens windows adjacent the junction 32 and the highly doped portions of the guard rings 34.
• the lightly doped portions 36 of the guard rings may be formed through ion implantation using the mask layer 100 as an ion implantation mask.
• boron ions having a doping concentration of from about 5.0x 10 16 to about 5.OxIO 17 cm “3 may be implanted into the silicon carbide layer 30 to provide the lightly doped portions 34 illustrated in Figure 4C.
• the mask layer 100 may then be removed and the insulating layer 26 may be formed on the resulting structure as illustrated in Figure 4D.
• the insulating layer 26 may, for example, be formed by thermal oxidation and/or depositing an oxide on the resulting structure.
• double guard ring termination in accordance with some embodiments of the present invention may allow the dose of the lightly doped guard ring (B) to be gradually reduced from the main junction of the device to the periphery using one time implantation.
• FIG. 6 a blocking histogram for diodes with robust guard ring termination and double guard ring termination according to some embodiments of the present invention will be discussed. As illustrated by the histogram, a blocking voltage of about 130 V higher was achieved using the double guard ring termination structure in accordance with some embodiments of the present invention.
• Figure 7 is a graph illustrating representative reverse IV curves for diodes with robust guard ring termination and double guard ring termination according to some embodiments of the present invention.
• Figure 8 is a graph illustrating simulations of SiC JBS diode blocking characteristics for diodes with robust guard ring termination and double guard ring termination according to some embodiments of the present invention. The devices were fabricated using the same wafer.
• Figures 9 and 10 are graphs illustrating potential distribution of JBS with double guard ring termination and robust guard ring termination at 680V, respectively, according to some embodiments of the present invention.
• Figures 11 and 12 are graphs illustrating electrical field distribution comparisons underneath termination junctions, and at the SiO 2 /SiC interface, respectively, according to some embodiments of the present invention. It will be understood that a lower electric field yields a lower leakage current.
• Figure 13 a cross section illustrating an edge termination structure 20' according to some embodiments of the present invention.
• Like reference numerals refer to like elements throughout, accordingly details with respect to like numbered elements discussed above with respect to Figure 3 will not be repeated herein in the interest of brevity.
• the lightly doped portion of the double guard ring structure has first and second portions 46 and 47.
• the first portion of the lightly doped portion 46 may be a p " " layer and may have a doping concentration of about 1.0 x 10 17 cm “3 .
• the first portion of the lightly doped portion may extend about 0.5 ⁇ m into the semiconductor layer 30.
• the second portion of the lightly doped portion 47 may be a p " layer and have a doping concentration of about 1.4 xl O 17 cm “3 .
• the second portion of the lightly dopes portion 47 may extend about 0.8 ⁇ m into the semiconductor layer 30 and may extend beneath the highly doped portion 36.
• Embodiments of the present invention illustrated in Figure 13 may exhibit improvement in electric field characteristics as illustrated in Figures 14 and 15 discussed below.
• Figure 14 is a graph illustrating electric field characteristics in accordance with some embodiments of the present invention illustrated in Figure 13.
• Figure 15 is a graph illustrating electric field characteristics in accordance with some embodiments of the present invention illustrated in Figure 13.
• Figure 15 is a graph illustrating robust GR termination and double guard ring termination with a retrograde profile of the second doping concentration.
• embodiments of the present invention are discussed above primarily with respect to silicon carbide semiconductor devices, embodiments of the present invention are not limited to silicon carbide devices.
• devices according to some embodiments of the present invention may be silicon (Si), gallium nitride (GaN) or gallium arsenide (GaAs) without departing from the scope of the present invention.
• Si silicon
• GaN gallium nitride
• GaAs gallium arsenide

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