JP4777699B2 - バイポーラ型半導体装置およびその製造方法 - Google Patents
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
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- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
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- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/732—Vertical transistors
Description
J. Zhang他著「High Power(500V-70A) and High Gain(44-47) 4H-SiC Bipolar Junction Transistors」Materials Science Forum Vols. 457-460 (2004) pp. 1149-1152.
11 コレクタ領域
12 n型高抵抗層
13 ベース領域
14 エミッタ領域
15 n型高抵抗層
16 ベースコンタクト領域
17 再結合抑制半導体層
18 再結合抑制膜
19 コレクタ電極
20 エミッタ電極
21 ベース電極
22 上層電極
Claims (8)
- 半導体結晶の一方の面に形成された第1の導電型の低抵抗層からなるコレクタ領域と、前記コレクタ領域上に設けられた第1の導電型の第1の高抵抗層と、前記第1の導電型の第1の高抵抗層上に設けられた第2の導電型のベース領域と、前記半導体結晶の他方の面に形成された第1の導電型の低抵抗のエミッタ領域と、前記エミッタ領域の周囲に前記第1の導電型の第2の高抵抗層を挟んで設けられた、前記ベース領域に接合する第2の導電型の低抵抗のベースコンタクト領域を有するバイポーラ型半導体装置であって、
前記ベースコンタクト領域と前記エミッタ領域の間の前記半導体結晶の表面に第2の導電型の再結合抑制半導体層を有し、
この再結合抑制半導体層は、
前記ベース領域に接合されておらず、かつ、その不純物濃度は、前記ベース領域の不純物濃度よりも低いことを特徴とするバイポーラ型半導体装置。 - 半導体結晶の一方の面に形成された第1の導電型の低抵抗層からなるコレクタ領域と、前記コレクタ領域上に設けられた第1の導電型の第1の高抵抗層と、前記第1の導電型の第1の高抵抗層上に設けられた第2の導電型のベース領域と、前記半導体結晶の他方の面に形成された第1の導電型の低抵抗のエミッタ領域と、前記エミッタ領域の周囲に前記第1の導電型の第2の高抵抗層を挟んで設けられた、前記ベース領域に接合する第2の導電型の低抵抗のベースコンタクト領域を有するバイポーラ型半導体装置であって、
前記ベースコンタクト領域と前記エミッタ領域の間の前記半導体結晶の表面に第1の導電型の再結合抑制半導体層を有し、
この再結合抑制半導体層は、
前記ベース領域に接合されておらず、かつ、その不純物濃度は、前記ベース領域の不純物濃度よりも低いことを特徴とするバイポーラ型半導体装置。 - 前記ベースコンタクト領域と前記エミッタ領域の間の前記半導体の表面は、一部分に傾斜を有することを特徴とする請求項1または2記載のバイポーラ型半導体装置。
- 前記ベースコンタクト領域と前記エミッタ領域の間の前記半導体の表面は、段差がないことを特徴とする請求項1または2記載のバイポーラ型半導体装置。
- 前記ベースコンタクト領域と前記エミッタ領域の間の前記半導体結晶の表面上に、熱酸化膜を形成し、前記熱酸化膜上に酸化膜あるいは窒化膜を形成して構成される再結合抑制膜を有することを特徴とする請求項1〜4のいずれか1項に記載のバイポーラ型半導体装置。
- 前記半導体結晶が炭化珪素であることを特徴とする請求項1〜5のいずれか1項に記載のバイポーラ型半導体装置。
- 第1の導電型の半導体基板に第1導電型の第1の高抵抗層を形成する第1高抵抗層形成工程と、
第2の導電型のベース領域を形成するベース領域形成工程と、
第1の導電型の第2の高抵抗層を形成する第2高抵抗層形成工程と、
第1の導電型の低抵抗層を形成する低抵抗層形成工程と、
前記低抵抗層と前記第2の高抵抗層の一部を部分的にエッチングしてエミッタ領域を形成するエミッタ領域形成工程と、
前記エッチングにより露出した第2の高抵抗層の表面に第2の導電型の再結合抑制半導体層を形成する再結合抑制半導体層形成工程と、
前記ベース領域に接合するベースコンタクト領域を形成するベースコンタクト領域形成工程と、
ベース電極とエミッタ電極とコレクタ電極を形成する電極形成工程と、
ベース電極とエミッタ電極側に上層電極を形成する上層電極形成工程と、
を有し、
前記再結合抑制半導体層は、前記ベース領域に接合されておらず、前記ベースコンタクト領域と前記エミッタ領域の間に配置され、
前記再結合抑制半導体層の不純物濃度は、前記ベース領域の不純物濃度よりも低いことを特徴とするバイポーラ型半導体装置の製造方法。 - 第1の導電型の半導体基板に第1導電型の第1の高抵抗層を形成する第1高抵抗層形成工程と、
第2の導電型のベース領域を形成するベース領域形成工程と、
第1の導電型の第2の高抵抗層を形成する第2高抵抗層形成工程と、
第1の導電型の低抵抗層を形成する低抵抗層形成工程と、
前記低抵抗層と前記第2の高抵抗層の一部を部分的にエッチングしてエミッタ領域を形成するエミッタ領域形成工程と、
前記エッチングにより露出した第2の高抵抗層の表面に第2の導電型の再結合抑制半導体層を形成する再結合抑制半導体層形成工程と、
前記ベース領域に接合するベースコンタクト領域を形成するベースコンタクト領域形成工程と、
前記ベースコンタクト領域と前記エミッタ領域の間の半導体結晶表面上に、熱酸化膜を形成し、前記熱酸化膜上に酸化膜あるいは窒化膜を形成して構成される再結合抑制膜を形成する再結合抑制膜形成工程と、
ベース電極とエミッタ電極とコレクタ電極を形成する電極形成工程と、
ベース電極とエミッタ電極側に上層電極を形成する上層電極形成工程と、
を有し、
前記再結合抑制半導体層は、前記ベース領域に接合されておらず、前記ベースコンタクト領域と前記エミッタ領域の間に配置され、
前記再結合抑制半導体層の不純物濃度は、前記ベース領域の不純物濃度よりも低いことを特徴とするバイポーラ型半導体装置の製造方法。
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JP2005172620A JP4777699B2 (ja) | 2005-06-13 | 2005-06-13 | バイポーラ型半導体装置およびその製造方法 |
CNB2006800211881A CN100544023C (zh) | 2005-06-13 | 2006-06-09 | 双极半导体器件及其制造方法 |
KR1020077027677A KR100972217B1 (ko) | 2005-06-13 | 2006-06-09 | 바이폴라 반도체 소자 및 그 제조 방법 |
US11/919,350 US8460994B2 (en) | 2005-06-13 | 2006-06-09 | Bipolar semiconductor device and manufacturing method thereof |
PCT/JP2006/312077 WO2006135031A2 (en) | 2005-06-13 | 2006-06-09 | Bipolar semiconductor device and manufacturing method thereof |
EP06757370.9A EP1878056B1 (en) | 2005-06-13 | 2006-06-09 | Bipolar semiconductor device and manufacturing method thereof |
US13/887,935 US8653627B2 (en) | 2005-06-13 | 2013-05-06 | Bipolar semiconductor device and manufacturing method thereof |
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WO2008020911A2 (en) | 2006-08-17 | 2008-02-21 | Cree, Inc. | High power insulated gate bipolar transistors |
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US9640609B2 (en) | 2008-02-26 | 2017-05-02 | Cree, Inc. | Double guard ring edge termination for silicon carbide devices |
US8232558B2 (en) | 2008-05-21 | 2012-07-31 | Cree, Inc. | Junction barrier Schottky diodes with current surge capability |
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JP5514726B2 (ja) * | 2008-08-26 | 2014-06-04 | 本田技研工業株式会社 | 接合型半導体装置およびその製造方法 |
WO2010024239A1 (ja) * | 2008-08-26 | 2010-03-04 | 本田技研工業株式会社 | 接合型半導体装置およびその製造方法 |
JPWO2010024243A1 (ja) * | 2008-08-26 | 2012-01-26 | 本田技研工業株式会社 | バイポーラ型半導体装置およびその製造方法 |
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EP1878056A2 (en) | 2008-01-16 |
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US20130240910A1 (en) | 2013-09-19 |
KR100972217B1 (ko) | 2010-07-26 |
US8460994B2 (en) | 2013-06-11 |
US8653627B2 (en) | 2014-02-18 |
CN100544023C (zh) | 2009-09-23 |
CN101199058A (zh) | 2008-06-11 |
US20100001290A1 (en) | 2010-01-07 |
WO2006135031A2 (en) | 2006-12-21 |
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