WO2008114806A1 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
- Publication number
- WO2008114806A1 WO2008114806A1 PCT/JP2008/055027 JP2008055027W WO2008114806A1 WO 2008114806 A1 WO2008114806 A1 WO 2008114806A1 JP 2008055027 W JP2008055027 W JP 2008055027W WO 2008114806 A1 WO2008114806 A1 WO 2008114806A1
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- Prior art keywords
- wafer
- chip
- semiconductor device
- manufacturing
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 50
- 238000000034 method Methods 0.000 title claims description 40
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- 239000012790 adhesive layer Substances 0.000 claims description 39
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- 229910052751 metal Inorganic materials 0.000 claims description 3
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 claims description 2
- 239000000919 ceramic Substances 0.000 claims description 2
- 239000003822 epoxy resin Substances 0.000 claims description 2
- 239000011521 glass Substances 0.000 claims description 2
- 239000004033 plastic Substances 0.000 claims description 2
- 229920000647 polyepoxide Polymers 0.000 claims description 2
- 239000010453 quartz Substances 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 2
- 239000000853 adhesive Substances 0.000 claims 1
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- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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Definitions
- the present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor device having a thin substrate and a manufacturing method thereof.
- a wafer 10 2 a having an element region 1 0 1 formed on the main surface is prepared, and a protective tape 1 0 5 a is attached to the surface of the wafer 1 0 2 a.
- the wafer 10 0 2 a is thinned by grinding from the back surface to a desired thickness. Specifically, in the case of discrete devices, the wafer 10 2 a is ground to a film of about 100 to 200 ⁇ m, and in the case of LSI, the wafer 10 2 a is 1 5 0 to 3 3 It is ground to a film of about 0 / im. After grinding, the protective tape 10 5 a is peeled off from the wafer 10 2 a.
- each chip 2 b is picked up from fixing tape 1 0 5 b, and conductive material 1 1 3 is applied onto island 1 1 2 a, and chip 1 0 2 Mount b. Then, the element region 1 0 1 and the lead 1 1 2 b are connected by, for example, a wire 1 1 4.
- the chip 1 0 2 b, the island 1 1 2 a, and the wire 1 1 4 are sealed with, for example, resin.
- the wafer 10 2 a when the wafer 10 2 a is ground to the thickness of the chip, the wafer 10 2 a is greatly warped. Particularly in recent years, the diameter of the wafer 10 2 a has been increasing, and this warpage cannot be ignored.
- a wafer 2 0 2 a having an element region 2 0 1 formed on the front surface side is prepared, and the back surface of the wafer 2 0 2 a is adsorbed to the dicing table 2 3 by vacuum or the like And fix. Then, the surface of the wafer 20 2 a is half-diced to form the groove 204.
- a flat ring 2 0 5 b with a protective tape 2 0 5 a attached thereto is prepared. Then, the element region 2 0 1 is fixed to the protective tape 2 0 5 a exposed from the flat ring 2 0 5 b.
- the flat ring 2 0 5 b is adsorbed and fixed to the grinding fixing base 2 0 7 of the grinding apparatus. Then, the wafer 2 0 2 a reaches the groove 2 0 4 from the back surface side. Grind until thin. At this time, the wafer 2 a is divided into individual chips 2 0 2 b.
- each chip 2 b is picked up from the fixed tape 10 5 b, and a semiconductor device as shown in FIG. 15 is obtained as in the first prior art.
- the wafer 2 0 2 a is divided into individual chips 2 0 2 b, so that warpage of the wafer 2 0 2 a is suppressed.
- wafers 1 0 2 a and 2 0 2 a are separated into chips 1 0 2 b and 2 0 2 b, and then chips 1 0 2 b and 2 0 2 b We had to pick up and transport it to the next process. This is because the mechanical strength of the fixing tape 1 0 5 b and the protective tape 2 0 5 a is weak.
- the back electrode is not formed on each of the chips 10 2 b and 2 0 2 b, and is mounted on the island 1 1 2 a with the conductive material 1 1 3.
- the fixing tape 10 0 5 b and the protective tape 2 0 5 a cannot withstand the processing temperature when forming the back electrode, so that each chip 1 0 2 This is because it is difficult to form the back electrode together with b and 2 0 2 b attached to the fixed tape 1 0 5 b and the protective tape 2 0 5 a.
- the wafer 2 0 2 a was separated into individual chips 2 0 2 b at the same time as grinding, but the mechanical strength of the protective tape 2 0 5 b was weak, so 0 It was difficult to make 2 b thinner than 80 ⁇ m.
- a method of manufacturing a semiconductor device includes a step of preparing a wafer having an element region formed on a surface, forming a groove so as to surround the element region, and an adhesive layer on the surface of the wafer A step of attaching a rigid support through the step, a step of thinning the wafer from the back surface until it reaches the groove and separating it into a plurality of chips, and affixing the plurality of chips to the support And a step of performing back surface processing with heat treatment in a state where the heat treatment is performed, and a step of dissolving the adhesive layer and separating the plurality of chips, respectively, and the adhesive layer is applied so as to enter the groove It is characterized by.
- a semiconductor device comprising: a semiconductor chip; an element region formed on a surface of the semiconductor chip; and a back electrode formed on a back surface of the chip.
- the back electrode includes the semiconductor chip. It is formed to extend to the middle of the side wall, and a mouth material is formed to the middle of the side wall.
- backside processing with heat treatment of the backside electrode and the like can be performed in a lump in a state where each chip is attached to the support.
- the height of the side fillet can be controlled by the amount of adhesive layer entering the groove.
- FIG. 1 is a cross-sectional view of a process of a method for manufacturing a semiconductor device according to the present invention
- FIG. 2 is a cross-sectional view of a process of a method of manufacturing a semiconductor device according to the present invention
- FIG. FIG. 4 is a cross-sectional view of one process of a semiconductor device manufacturing method according to the present invention
- FIG. 4 is a cross-sectional view of one process of a semiconductor device manufacturing method according to the present invention
- FIG. Manufacturing method FIG. 6 is a cross-sectional view of a semiconductor device according to the present invention
- FIG. 7 is a cross-sectional view of a process of manufacturing a semiconductor device according to the present invention
- FIG. 9 is a cross-sectional view of one step of a method for manufacturing a semiconductor device according to the present invention
- FIG. 9 is a cross-sectional view of one step of a method for manufacturing a semiconductor device according to the present invention
- FIG. 10 is a semiconductor according to the present invention.
- FIG. 11 is a cross-sectional view of a process of a semiconductor device manufacturing method according to the present invention
- FIG. 11 is a cross-sectional view of a process of a semiconductor device manufacturing method according to the present invention.
- FIG. 13 is a cross-sectional view of one process of the method of manufacturing a semiconductor device according to the prior art
- FIG. 14 is a cross-sectional view of the method of manufacturing the semiconductor device according to the prior art.
- FIG. 15 is a cross-sectional view of a conventional semiconductor device
- Fig. 16 is a cross-sectional view of the prior art
- FIG. 17 is a cross-sectional view of one process of a method for manufacturing a semiconductor device according to the prior art
- FIG. 18 is a diagram of a method for manufacturing a semiconductor device according to the prior art. It is sectional drawing of a process.
- a wafer 2 a having an element region 1 formed on the surface side is prepared, and a groove 4 is formed so as to surround the element region 1.
- the groove 4 is formed to be deeper than at least the thickness of the chip after completion.
- the wafer 2 a is bonded to the support 5 with the adhesive layer 6 with the element region 1 facing down.
- the adhesive layer 6 is made of a viscous material such as epoxy resin, resist, or acrylic.
- the support 5 is made of a rigid material such as glass, quartz, ceramic, plastic, metal, or resin.
- the adhesive layer 6 is The groove 4 is not completely embedded, and is formed to be slightly shallower than the chip thickness after completion.
- a BG tape 7 is attached to the support 5, and the wafer 2a is ground and thinned from the back side to a desired film thickness (corresponding to the chip film thickness after completion).
- the wafer 7 a is ground up to the groove portion 4 and separated into individual chips 2 b, and the wafer 2 a is firmly supported by the rigid support 5. Therefore, in this embodiment, the wafer 2a can be ground to 80 ⁇ m or less. Note that when the wafer 2 a is separated into chips 2 b, the groove 4 is exposed, but since the adhesive layer 6 has entered the groove 4, polishing impurities enter the element region 1 from the groove 4. Can be suppressed.
- electrode materials 4 such as Al and Cu are deposited from the back side of each chip 2b by using methods such as CVD, PVD, sputtering, and plating. Then, the back electrode 9a is formed.
- the chips 2 b are supported by the support 5 having high heat resistance, the chips 2 b can be added to the back surface together without being separated from the support 5.
- each chip 2 b is affixed to the fixing tape 16 and the adhesive layer 6 is dissolved, each chip 2 b is separated from the support 5.
- each chip 2 b is picked up from the fixing tape 16 and mounted on the island 1 2 a.
- the electrodes (not shown) formed in the element region 1 are connected to the leads 1 2 b by wires 14 such as force metal and copper. Further, if necessary, the chip 2b, the island 12a, and the lead 12b are molded with resin to complete the semiconductor device.
- the groove 4 may be formed by half dicing.
- half dicing is performed by a blade, a laser, or the like.
- a layer having low mechanical strength such as a low wk (low dielectric constant) material is formed on the wafer 2a, peeling of this layer can be prevented.
- the groove portion 4 may be formed by etching such as isotropic etching or anisotropic etching.
- the groove 4 can be formed in such a shape that the electrode material 8 does not easily adhere to the side wall of the groove.
- the groove 4a can be formed with a curved upper end. .
- the electrode material 8 is difficult to adhere to the side wall of the groove 4a.
- a method of alternately repeating a plasma etching process using mainly SF 6 gas and a plasma deposition process using mainly C 4 F 8 gas as anisotropic etching is performed.
- the groove 4 b can be formed so that the inner wall is roughened in a wave shape.
- the electrode material is attached so as to be interrupted on the inner wall of the groove 4b.
- the back electrode 9 a is formed with each chip 2 b attached to the support 5 (FIG. 4).
- the electrode material 8 is formed without interruption between the chip 9 a and the adhesive layer 6 exposed in the groove 4.
- tip 2b remains connected by electrode material 8 and cannot be melted.
- the thickness of the chip 2 b after completion of the adhesive layer 6 It is necessary to form so that it may become low.
- the adhesive layer 6 it is preferable to first apply the adhesive layer 6 to the support 5 and then attach the wafer 2a. As a result, the adhesive layer 6 is pushed out by the air accumulated in the groove 4, and therefore the adhesive layer 6 is difficult to completely enter the groove 4.
- the adhesive layer 6 enters the groove 4 when it is applied to the adhesive layer 6. Therefore, the adhesive layer 6 is easier to fill the groove 4 than the above-described method. As a result, the above-described method is effective when the wettability of the groove 4 is large, such as when the diameter of the groove 4 is small.
- the wafer 2 a is ground and simultaneously separated into chips 2 b. Thereafter, each chip 2 b is transported to the next process while being attached to the support 5, but at this time, the end of the back surface of the chip 2 b is easily chipped. In order to prevent this, a step of forming a roundness at the end of the chip 2b may be added. Specifically, after the wafer 2 a is ground, the back surface of the wafer 2 a may be slightly etched using, for example, an acid (for example, a mixed solution of HF and nitric acid) as an etchant.
- an acid for example, a mixed solution of HF and nitric acid
- each chip 2 b is separated from the support 5 (FIG. 5). This is because the electrode material 8 is discontinuous between the chip 2 b and the adhesive layer. This is because it is formed.
- the discontinuity of the electrode material 8 will be described in detail.
- FIGS. 8 (a) and 8 (b) are enlarged sectional views of the vicinity of the groove 4.
- the back surface electrode 9a is formed not only on the back surface of the chip 2b but also on the upper end of the side wall portion thereof. 2 b side wall 4 a, 4 Difficult to adhere to b.
- the electrode material 8 is not formed at all on the side wall 4a as shown in FIG. 8 (a), or is thinly formed on the side wall 4b as shown in FIG. 8 (b).
- the electrode material 8 is formed so as not to extend to the element region 1, and a defective product such as a short circuit is less likely to occur.
- the support 5 shown in FIG. 9 (a) has a dissolution hole 11a for supplying the dissolution agent 17.
- the fixing tape 16 is attached to the back surface of each chip 2b, and the dissolving agent 1 7 is supplied from the dissolving hole 1 1a.
- Layer 6 can be dissolved to separate each chip 2b from support 5.
- each chip 2 b can be peeled from the support 5 by supplying the dissolving agent 17 from the dissolving hole 1 1 b of the fixing tape 16.
- each chip 2b is fixed by being sucked by a suction machine 18.
- the dissolving agent 17 is sucked, it is supplied to the adhesive layer 6 from a gap in the side wall of the groove 4, for example.
- the back surface electrode 9 b is formed not only on the back surface of the chip 2 b but also on the side wall.
- the conductive material 1 3 a such as solder and the reflow process is performed
- the conductive material 1 3 a flows toward the outside of the chip 2 b.
- the conductive material 1 3 a is used for the side fillet 1 3 b. Then, the chip 2 b and the island 1 2 a are firmly connected.
- the pre-process is performed in Japan and the post-process is performed in Asia.
- the process of processing the wafer 2a and the process of mounting the chip 2b are often performed at different locations.
- the chip 2 b after processing the wafer 2 a, the chip 2 b can be transported while being attached to the support 5.
- the adhesive layer 6 is covered with the electrode material 8. For this reason, moisture in the air is less likely to be mixed into the adhesive layer 6 during transportation, and problems do not occur when each chip 2 b is peeled off during transportation.
- the transport case 15 various things such as a laminate bag and a solid box can be used. Then, if a drying agent 19 that absorbs moisture in the air is placed in the transport case 15, peeling of the adhesive layer 6 can be prevented more firmly.
- the present invention is not limited by the type of the chip 2b, and the MOS transistor This is applied to various semiconductor devices such as LSIs, as well as discrete devices such as ICs, IGBTs, and diodes.
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
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Abstract
Description
Claims
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US12/530,829 US8187949B2 (en) | 2007-03-14 | 2008-03-12 | Semiconductor device and method of manufacturing the same |
CN2008800082593A CN101632155B (zh) | 2007-03-14 | 2008-03-12 | 半导体装置及其制造方法 |
US12/570,209 US8907407B2 (en) | 2008-03-12 | 2009-09-30 | Semiconductor device covered by front electrode layer and back electrode layer |
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JP2007065353A JP5238927B2 (ja) | 2007-03-14 | 2007-03-14 | 半導体装置の製造方法 |
JP2007-065353 | 2007-03-14 |
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US (1) | US8187949B2 (ja) |
JP (1) | JP5238927B2 (ja) |
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KR102259185B1 (ko) | 2016-08-02 | 2021-06-01 | 누보톤 테크놀로지 재팬 가부시키가이샤 | 반도체 장치, 반도체 모듈, 및 반도체 패키지 장치 |
JP6794896B2 (ja) * | 2017-03-29 | 2020-12-02 | Tdk株式会社 | 酸化ガリウム半導体装置の製造方法 |
US11791212B2 (en) * | 2019-12-13 | 2023-10-17 | Micron Technology, Inc. | Thin die release for semiconductor device assembly |
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CN101632155B (zh) | 2011-06-22 |
CN101632155A (zh) | 2010-01-20 |
JP5238927B2 (ja) | 2013-07-17 |
JP2008227284A (ja) | 2008-09-25 |
US20100044873A1 (en) | 2010-02-25 |
US8187949B2 (en) | 2012-05-29 |
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