Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
  • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
  • H10F39/80—Constructional details of image sensors
  • H10F39/803—Pixels having integrated switching, control, storage or amplification elements
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
  • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
  • H04N25/62—Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
  • H04N25/70—SSIS architectures; Circuits associated therewith
  • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
  • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
  • H10F39/10—Integrated devices
  • H10F39/12—Image sensors
  • H10F39/18—Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
  • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
  • H10F39/80—Constructional details of image sensors
  • H10F39/807—Pixel isolation structures
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
  • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
  • H10F39/10—Integrated devices
  • H10F39/12—Image sensors
  • H10F39/18—Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors
  • H10F39/186—Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors having arrangements for blooming suppression
  • H10F39/1865—Overflow drain structures

Definitions

• the invention relates generally to the field of image sensors, and in particular to active pixel image sensors having an n-type pinning layer and a p- type collection region in an n-type well for reducing cross talk.
• Active pixel sensors refer to sensors having an active circuit element such as an amplifier in, or associated with, each pixel.
• CMOS refers to "complimentary metal oxide silicon" transistors in which two transistors composed of opposite dopants (one of p-type and one of n-type) are wired together in a complimentary fashion. Active pixel sensors also typically use CMOS transistors, and as such, are used interchangeably.
• CMOS sensors built on p-type substrates typically contain a higher level of circuit integration on chip due to the fact that the process is derived from standard CMOS, which is already fully developed and contains all the necessary devices and circuit libraries to support this high level of integration.
• these sensors suffer from high levels of pixel-to-pixel cross talk that results from the lateral diffusion of minority carriers within the p-type substrates on which they are built.
• VOD vertical- overflow drain
• color cross talk is primarily optical as limited by the transmission of the overlying CFAs.
• the present invention is directed to overcoming one or more of the problems set forth above.
• the present invention resides in an image sensor with an image area having a plurality of pixels each having a photodetector of a first conductivity type, the image sensor comprising a substrate of the first conductivity type; a first layer of the second conductivity type between the substrate and the photodetectors, spanning the image area and biased at predetermined potential with respect to the substrate for driving excess carriers into the substrate to reduce cross talk; one or more adjacent active electronic components disposed in the first layer within each pixel; and electronic circuitry disposed in the substrate outside of the image area.
• the present invention has the advantage of reducing cross talk and the bulk-diffusion component of dark current while retaining all the advantages of using mainstream standard CMOS integrated on a p-type substrate.
• Fig. 1 shows the top view of an image-area pixel used in a typical prior art CMOS image sensor
• Fig. 2a shows a schematic view of a two-dimensional doping structure taken through a cross section through the transfer gate and floating diffusion of a typical prior art pinned photodiode detector
• Fig. 2b shows the 1 -D doping profile vs. depth into the silicon through the middle of the prior art photodiode
• Fig. 2c shows the 1-D potential profile vs. depth into the silicon through the middle of the prior art photodiode
• Fig. 3 illustrates example results of a 2-D calculation of pixel-to- pixel cross talk vs. depletion depth of a prior art CMOS active pixel image sensor pixel
• Fig. 4a shows a schematic view of a two-dimensional doping structure for the PMOS pixel structure of the present invention taken through a cross section through the transfer gate, floating diffusion, and reset gate;
• Fig. 4b shows a top view of an exemplary layout for the image sensor of Fig. 4a
• Fig. 4c shows the 1-D doping profile vs. depth into the silicon through the middle of the PMOS pixel structure of the present invention
• Fig. 4d shows the 1-D potential profile vs. depth into the silicon through the middle of the PMOS pixel structure of the present invention
• Fig. 5 shows the results of a 2-D calculation of pixel-to-pixel cross talk vs. overflow or sink depth for various photodiode depletion depths for the PMOS pixel structure of the present invention built in a well;
• Fig. 6 is an illustration of a digital camera for illustrating a typical commercial embodiment of the present invention to which the ordinary consumer is accustomed.
• CCD charge-coupled device
• CCD imagers are also typically built in a well, or vertical-overflow drain (VOD) structure (see for example US Patent 4,527,182). Therefore, building a VOD structure along with the requirement for an n-channel requires that a p-well be formed in an n-type substrate.
• CMOS-based image sensors .have since become more readily available. Current day CMOS image sensors are typically built on either p- or n- type silicon substrates.
• CMOS image sensors have only one transfer, i.e., from the photodiode to the floating diffusion.
• a CMOS image sensor does not require as high a charge carrier mobility.
• the lower mobility of holes would not be a deficiency for a CMOS image sensor. It is therefore one object of the present invention to disclose a CMOS image sensor employing a PMOS (p-channel) pixel structure using holes as the signal-charge carrier.
• PMOS p-channel
• This PMOS structure of the present invention allows the pixel to be built in an n-well on p-type epi to reduce pixel-to-pixel cross talk.
• this well is only used underneath (or spanning) the imaging section of the sensor.
• CMOS support circuitry integrated on the chip is formed in the p-type epi (see Fig. 4b, i.e., analog or digital circuits 80, digital logic 90, row decoder 100, and column decoder 110). This means that all of the physical aspects of the devices in the standard CMOS circuitry portion of the chip are retained. Additionally, unlike the CCD image sensors built in a well wherein this well is biased at ground and the substrate at some positive potential, by biasing the n-well of the present invention structure at VDD 3 the ground plane (i.e., the p-type epitaxial substrate) for the CMOS circuitry can be maintained at 0 V.
• the top view of a typical prior art CMOS image sensor pixel is shown in Fig. 1.
• the typical pixel consists of a photodiode (PD); a transfer gate (TG) for reading charge out of the photodiode; a floating diffusion (FD) for converting the signal charge into a voltage signal; a source-follower transistor (SF) which acts as a signal buffer whose gate is electrically connected to FD; a row- select transistor (RS) that selectively connects the outputs of the source-follower transistors to the column output circuits (not shown in Fig. 1); and a reset gate (RG) for resetting the potential of the floating diffusion.
• a power supply voltage (VDD) is used to power the source follower and drain off signal charge from the floating diffusion during its reset operation.
• a typical prior art CMOS image sensor pixel contains a pinned photodiode with a p+ type pinning layer and an n-type storage region built on p- /p++ epitaxial silicon wafers as illustrated by way of example in Figs. 2a-2c.
• the depletion region depth (shown in Figs. 2a and 2c) defines the collecting boundary of the photodiode.
• An example doping profile down through the center of the prior art photodiode is shown in Fig. 2b.
• Charge carriers (electrons) generated from shorter wavelength light that are created within the collecting region (i.e., depletion region boundary) are captured and stored as signal charge.
• Charge carriers generated from longer wavelengths that are created past this depletion depth are free to diffuse in any direction via thermal diffusion. Any charge that diffuses laterally and .gets collected by adjacent pixels is called electrical cross talk.
• Cross talk can be quantified by defining it as the ratio of the signal in the non-illuminated to the illuminated pixel(s), and can be expressed as either a fraction or percentage. Therefore, cross talk represents the relative amount of signal that does not get collected by the pixel(s) under which it was generated.
• the dependence of cross-talk on depletion depth for the example prior-art pixel is illustrated in Fig. 3.
• the cross-talk calculation assumes that every other pixel along a line is illuminated (and the alternating, interleaved pixels are not).
• a wavelength of 650 ran is assumed, because cross talk is more of a problem at longer wavelengths because the optical absorption coefficient is lower at longer wavelengths, (i.e., the photons are absorbed deeper). It can be seen from this figure that although increasing the depletion depth can reduce cross talk, it does not go to zero even for depletion depths up to 3um, which is approximately one over the absorption coefficient for silicon at 650 nm.
• FIG. 4a A cross section of the PMOS pixel architecture of the present invention is shown in Fig. 4a.
• the top view of an example CMOS image sensor containing this pixel structure is shown in Fig. 4b.
• An example doping profile down through the center of the photodiode is shown in Fig. 4c.
• An example potential profile down through the center of the empty photodiode is shown in Fig. 4d.
• the pinned photodiode 10 of the present invention embodies an n+ pinning layer 20 and p-type buried storage region 30 built within an n-type well 40 on a p-/ ⁇ ++ epitaxial substrate 50.
• the photodiode's surface pinning layer 20 of the present invention is n-type, arsenic can be used. This makes it easier to create a shallow pinning layer due to the shorter implant range of arsenic compared to that of boron. (The prior art structure has a p-type pinning layer for which boron is typically used). Also, because the photodiode's storage region 30 is now p-type instead of n-type, boron can be used, (which has ' a longer implant range than phosphorous or arsenic as required for the storage region of the prior art structure), thereby making it easier to make this implant deep.
• the n+ pinning layer 20 is electrically connected to the n-well 40 via the n+ type isolation implant 60 around the typical shallow trench isolation (STI) region as can be seen in Fig. 4a.
• This pinning layer 20 maintains the surface of the diode in accumulation (of electrons).
• Signal charge is stored in the form of holes in the p-type buried storage region 30 of the pinned photodiode 10.
• the n-type well 40 is only formed in the image area 70 having a plurality of pixel as illustrated by the top view shown in Fig. 4b.
• the image sensor 75 uses standard mainstream CMOS devices and circuitry in the analog or digital circuits 80, digital logic 90, row decoder 100, and column decoder 110 while retaining all the benefits of a p-type substrate. It is preferable to form this n-well 40 at the beginning of the process so that its formation does not affect other device structures. For example, if it is formed via an implant and thermal drive, by doing this prior to the standard CMOS processing, the thermal drive step will not cause diffusion of shallow junction regions as required by the devices used in the CMOS support circuitry surrounding the image area.
• the pixel's transfer gate (TG), reset gate (RG), and source follower (SF) transistors are all preferably p-type metal oxide silicon (note that the gate is not usually metal; it is polysilicon, and sometimes the dielectric is not solely oxide), field effect transistors (PMOS FETs).
• a row select transistor (RS not shown) in series with the output of the source follower amplifier (SF) would also be a PMOS device.
• All of the peripheral supporting CMOS circuitry 80, 90, 100 and 110 is formed within the p- /p++ epitaxial substrate. The substrate is at ground and the n-well 40 is biased at a convenient positive bias, such as VDD.
• the floating diffusion (FD) is reset with a negative going pulse on the reset gate (RG) prior to signal transfer from the photodiode.
• a convenient FD reset voltage level is ground.
• VDD clock voltages
• Fig. 4a An example of convenient clock voltages (VDD) used for these pulses are shown in Fig. 4a. Other voltages may be possible without departing from the scope of the invention. Since the signal charge is holes for the present invention structure, the signal swing on the floating diffusion and source follower (SF) output will be positive going.
• any photosignal (holes) that is generated within the n-well 40 beneath the photodiodes collecting region 30 is swept into the substrate 50 before it can diffuse to neighboring pinned photodiodes 10, thereby eliminating electrical cross talk.
• the signal would be read out from the chip in the usual manner as would be well known by those working in the art.
• the potential barrier between the substrate and photodiode that results from this structure also eliminates the diffusion component of dark current from the substrate (bulk) into the photodiode. Electrical cross talk for the pixel structure of the present invention with a pinned photodiode built in an n-well on a p-type substrate is greatly reduced as shown in Fig. 5.
• a digital camera 120 having an image sensor 75 of the present invention disposed therein for illustrating a typical commercial embodiment to which the ordinary consumer is accustomed.
• the preferred embodiment of the present invention shown incorporates a pinned photodiode consisting of an n+ pinning (top surface) layer and a p-type buried collecting region within an n-well on a p-type epi substrate, it will be understood the those skilled in the art that other structures can be used without departing from the scope of the invention.
• a simple unpinned p-type diode formed in an n-type well could be used, if desired.
• a simple non-shared pixel architecture is shown, a shared architecture. (such as US Patent 6,107,655 for example), could also be used without departing from the scope of the invention.

Landscapes

• Engineering & Computer Science (AREA)
• Multimedia (AREA)
• Signal Processing (AREA)
• Solid State Image Pick-Up Elements (AREA)
• Transforming Light Signals Into Electric Signals (AREA)

Priority Applications (4)

Applications Claiming Priority (2)

Publications (1)

Family

ID=38255775

Family Applications (1)

Country Status (7)

Cited By (1)

Families Citing this family (78)

Citations (4)

Family Cites Families (31)

• 2006
  • 2006-06-20 US US11/455,985 patent/US7728277B2/en active Active
• 2007
  • 2007-03-23 CN CN2007800230656A patent/CN101473441B/zh active Active
  • 2007-03-23 JP JP2009516479A patent/JP5295105B2/ja active Active
  • 2007-03-23 EP EP07753971.6A patent/EP2030240B1/en active Active
  • 2007-03-23 KR KR1020087030965A patent/KR101329432B1/ko active Active
  • 2007-03-23 WO PCT/US2007/007388 patent/WO2007149137A1/en not_active Ceased
  • 2007-04-27 TW TW096114906A patent/TWI427763B/zh active
• 2010
  • 2010-04-01 US US12/752,279 patent/US20100188545A1/en not_active Abandoned

Patent Citations (4)

Non-Patent Citations (1)

Also Published As

Similar Documents

Legal Events