Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
  • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
  • H10P32/16—Diffusion of dopants within, into or out of semiconductor bodies or layers between a solid phase and a liquid phase
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
  • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
  • H10P32/12—Diffusion of dopants within, into or out of semiconductor bodies or layers between a solid phase and a gaseous phase
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
  • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
  • H10P32/14—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
  • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
  • H10P32/17—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material
  • H10P32/171—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material being group IV material
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
  • H10P95/90—Thermal treatments, e.g. annealing or sintering
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
  • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
  • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
  • H10P14/2901—Materials
  • H10P14/2902—Materials being Group IVA materials
  • H10P14/2904—Silicon carbide
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
  • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
  • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
  • H10P14/2901—Materials
  • H10P14/2902—Materials being Group IVA materials
  • H10P14/2905—Silicon, silicon germanium or germanium
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
  • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
  • H10P14/34—Deposited materials, e.g. layers
  • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
  • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
  • H10P14/3411—Silicon, silicon germanium or germanium
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
  • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
  • H10P14/36—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done before the formation of the materials
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
  • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
  • H10P14/38—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done after the formation of the materials
  • H10P14/3802—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth

Definitions

• the present invention relates to a method for producing a semiconductor structure and a corresponding semiconductor structure.
• the present invention relates to a change in the material properties of a semiconductor substrate, for example of silicon or silicon carbide, starting from a surface of the semiconductor substrate.
• Such changes may, for example, consist in the setting of a specific conductivity or conductivity type (p or n doping).
• reference numeral 1 denotes a silicon semiconductor substrate of, for example, p-type, and reference numerals
• doping regions 5 are caused by diffusion of impurities into the semiconductor substrate 1 starting from the surface OF.
• a source of dopants is deposited on the wafer surface (eg phosphorus glass for p-doping or boron glass for p-doping) and then thermally driven at high temperature, ie the dopants for diffusion into the silicon Semiconductor substrate 1 excited starting from the surface OF.
• the dopants may be incorporated into the wafer surface in a layer of typically 1 to 2 microns thickness are implanted, which is subsequently thermally diffused deeper into the silicon semiconductor substrate 1.
• Such diffusion processes are generally limited to a relatively small layer thickness starting from the surface OF of the semiconductor substrate 1, since foreign substances, such as. B. dopant atoms, diffuse only slowly in silicon, even at very high temperatures and therefore can reach in practice only depths of typically 20 to 25 microns in silicon, at least within economically acceptable diffusion times. There are also foreign atoms such. As antimony (Sb) or germanium (Ge), etc., which diffuse only extremely slowly due to their large atomic diameter, s that the specified limit of typically 20 to 25 microns in silicon can not even be achieved with these impurities, but the Diffusion depths within reasonable times, on the other hand, remain significantly lower.
• Sb antimony
• Ge germanium
• thicker layers of e.g. Silicon or silicon carbide with altered layer properties e.g. As a change in electrical conductivity or an altered electrical conductivity type required, so that the specified limits of thermal diffusion processes in the bulk material disturb.
• thick n-type monocrystalline silicon layers of, for example, 100 to 200 ⁇ m in thickness on a p-type semiconductor substrate may be mentioned, which would be used advantageously for high-pressure sensors in silicon in conjunction with an electrochemical etch stop from p to n-type silicon.
• the problem on which the present invention is based therefore consists in the provision of a method for producing a semiconductor structure and a corresponding semiconductor structure which enable a process-technically simple production of deep doping regions in a semiconductor substrate.
• the inventive method for producing a semiconductor structure according to claim 1 or the corresponding semiconductor structure according to claim 11 have the advantage that they are the production of thick layers of crystalline semiconductor material, such as. As silicon or silicon carbide, with altered properties by introducing foreign atoms or foreign substances allow.
• the layers can alternatively also be made polycrystalline. It can on the one hand modified
• Layers are produced in such a large thickness, which are not economically producible in these large layer thicknesses otherwise.
• foreign atoms can be introduced, which diffuse only very slowly and therefore can not be introduced in layers according to the prior art in a practical manner, for.
• antimony or germanium or other atoms with a large atomic radius As antimony or germanium or other atoms with a large atomic radius.
• modified layers can be produced, for example, in silicon carbide, where otherwise the diffusion-inhibiting base material SiC would render layer modification impossible or virtually impossible.
• SiC diffusion-inhibiting base material
• porous silicon or porous silicon carbide can be produced nanoporous or mesoporous by selecting appropriate anodization conditions, essentially current density and hydrofluoric acid concentration.
• the dopants can be supplied either in the form of a carrier gas (eg, diborane, arsine, phosphine, etc.), which penetrates into the structure.
• a carrier gas eg, diborane, arsine, phosphine, etc.
• a glass, z. B. boron glass or phosphorus glass are deposited on the surface or a dissolved in liquid precursor be impregnated into the porous structure.
• Suitable precursors are organic and inorganic compounds of boron, phosphorus (eg trimethyl phosphite, phosphorus pentaxyde), arsenic (vinyl arsine), antimony, germanium (tetraethylgerman), aluminum, iron, lead, etc. or their soluble salts (eg.
• the dopants are supplied in the form of a carrier gas, wherein the gas passes homogeneously through the porous region at high temperature of, for example, 900 ° C. and the impurities simultaneously diffuse out of the gas phase into the nanostructure.
• the temperature treatment for deposition and the temperature treatment for driving in the dopant coincide in time.
• impregnation of the porous region with a solution of impurities in a liquid, especially in supercritical CO 2 may take place at room temperature, followed immediately by a temperature step at 900 ° C. for driving in and another at 950 ° C. for recrystallization and Driving in take place.
• the step of driving the foreign atoms thermally is carried out separately at a temperature at which no structural rearrangement can take place yet.
• the foreign atoms diffuse into the filigree nanostructures in the entire volume of the porous structure at a temperature of, for example, 900 ° C. in silicon and penetrate them almost homogeneously.
• the stability of the nanostructure is additionally supported by the fact that natural oxides on the structural surfaces additionally stabilize them and prevent thermal rearrangement. In the case of silicon, such oxides decompose only above 950 ° C., in the case of silicon carbide only above 1.200 ° C.
• the porous region is thermally collapsed at high temperatures, for example from above 950 ° C. in the case of silicon and above 1200 ° C. in the case of silicon carbide, a monocrystalline massive layer again being formed by rearrangement of the silicon atoms or silicon carbide Meaning of bulk material. This rearrangement was initially undesirable, so that the foreign atoms could still reach the nanostructure anywhere and there was no injury to individual areas of the structure.
• the native oxide layers supporting the nanostructures are now evaporated, which can be additionally supported by the addition of hydrogen gas. Without the stabilization by the surface oxides, the thermal charge-order of the structure can quickly begin and continue until a complete compaction into a monocrystalline material.
• FIG. 1 ad show schematic cross-sectional views of the essential manufacturing steps of a
• FIG. 2 is a flowchart for explaining the procedure of the essential manufacturing steps of the method for manufacturing a semiconductor structure according to the embodiment of the present invention.
• FIG. 3 shows a schematic cross-sectional view of a known semiconductor structure, essential manufacturing steps of a method for producing a semiconductor structure according to an embodiment of the present invention
• FIG. 1 a-d show schematic cross-sectional views of the essential manufacturing steps of a method for manufacturing a semiconductor structure according to an embodiment of the present invention
• FIG. 2 is a flowchart for explaining the flow of the essential manufacturing steps of the method for manufacturing a semiconductor structure according to the embodiment of the present invention.
• reference numeral 1 denotes a p-type silicon semiconductor substrate having a surface OF.
• a mask 2 made of silicon nitride is applied to the surface OF (step S 1) and subsequently a nanoporous area 10 having a depth t of 100 ⁇ m is introduced by an electrochemical anodization (step S 2), which has a mesh of pores 10 a, which form an interconnected skeleton.
• a glass is initially 12, for example, incorporated phosphorus glass into the porous portion 10 at a temperature of 900 0 C, immediately at the same time at this temperature, a diffusion of the phosphorus in the Skeleton made of nanoscale silicon and the latter is thus penetrated homogeneously by the phosphorus.
• a thermal step is then carried on with reference to FIG. Id S4 at a temperature of more than 950 0 C, which results by rearrangement of the silicon atoms, a thermal recrystallizing the porous region 10 in a crystalline impurity region 10 'of the semiconductor substrate 1, the doping type, doping concentration and doping distribution differs from that or those of the semiconductor substrate 1.
• the dopants may be either in the form of a carrier gas or in the form of a liquid solution which penetrates into the porous structure.
• the semiconductor structure has been formed using the silicon nitride mask in the above example, it is also possible to provide edge doping in the semiconductor substrate which laterally surrounds the porosified region and serves as an etching mask. Also, for the anodic process, a doping of the back of the substrate can be provided.
• micromechanical pressure sensor is purely exemplary and can be modified as desired.

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• Recrystallisation Techniques (AREA)
• Pressure Sensors (AREA)
• Weting (AREA)

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Citations (4)

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• 2006
  • 2006-03-21 DE DE102006012857A patent/DE102006012857A1/de not_active Withdrawn
• 2007
  • 2007-03-09 WO PCT/EP2007/052227 patent/WO2007107461A1/de not_active Ceased
  • 2007-03-09 JP JP2009500813A patent/JP5080555B2/ja not_active Expired - Fee Related
  • 2007-03-09 DE DE502007006500T patent/DE502007006500D1/de active Active
  • 2007-03-09 US US12/282,842 patent/US8148234B2/en not_active Expired - Fee Related
  • 2007-03-09 EP EP07726749A patent/EP1999783B1/de not_active Not-in-force
• 2012
  • 2012-02-03 US US13/366,067 patent/US20120132925A1/en not_active Abandoned

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Non-Patent Citations (7)

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