Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
  • H01L21/3105—After-treatment
  • H01L21/311—Etching the insulating layers by chemical or physical means
  • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
  • H01L21/28008—Making conductor-insulator-semiconductor electrodes
  • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
  • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
  • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
  • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
  • H01L21/321—After treatment
  • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
  • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/0221—Manufacture or treatment of FETs having insulated gates [IGFET] having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
  • H10D30/0275—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions
• • H10D64/01326—
• • H10D64/01328—
• • H10D64/01354—
• • H10P50/71—
• • H10P50/73—

Definitions

• the present invention relates to a method of manufacturing semiconductor devices, and more particularly, to the formation of spacers of specific dimensions
• CMOS complementary metal oxide semiconductor
• ULSI ultra-large scale integrated
• a ULSI circuit can include CMOS field effect transistors (FETs) which have semiconductor gates disposed between drain and source regions.
• the drain and source regions are typically heavily doped with a P-type dopant (boron) or an N-type dopant (phosphorous).
• the drain and the source regions generally include thin extensions (shallow source and drain extensions) that are disposed partially underneath the gate to enhance transistor performance. Shallow source and drain extensions help to achieve immunity to short-channel effects which degrade transistor performance for both n- channel and p-channel transistors. Short-channel effects can cause threshold voltage roll-off and drain-induced barrier-lowering. Shallow source and drain extensions and, hence, controlling short-channel effects, are particularly important as transistors become smaller.
• the source and drain extensions are formed by providing a transistor gate structure without sidewall spacers on a top surface of a silicon substrate.
• the silicon substrate is doped on both sides of the gate structure via a conventional doping process, such as a diffusion process or an ion implantation process. Without the sidewall spacers, the doping process introduces dopants into a thin region just below the top surface of the substrate to form the source and drain extensions as well as to partially form the drain and source regions.
• sidewall spacers which abut the lateral sides of the gate structure, are provided over the source and drain extensions. With the sidewall spacers in place, the substrate is doped a second time to form deep source and drain regions. During formation of the deep source and drain regions, further doping of the source and drain extensions is inhibited due to the blocking capability of the sidewall spacers.
• transistors having shallow and ultra-shallow source/drain extensions become more difficult to manufacture.
• a transistor may require ultra- shallow source and drain extensions with a junction depth of less than 30 nanometers (nm). Forming source and drain extensions with junctions depths of less than 30 nm is very difficult using conventional fabrication techniques.
• Conventional ion implantation techniques for example, have difficulty maintaining shallow source and drain extensions because point defects generated in the bulk semiconductor substrate during ion implantation can cause the dopant to more easily diffuse (transient enhanced diffusion, TED). The diffusion often extends the source and drain extensions vertically downward into the bulk semiconductor substrate.
• conventional ion implantation and diffusion dopant techniques make transistors on the IC susceptible to short-channel effects, which result in a dopant profile tail distribution that extends deep into the substrate.
• the source and drain regions can be raised by selective silicon epitaxial growth (SEG) to make connections to source and drain contacts less difficult.
• SEG selective silicon epitaxial growth
• the raised source and drain regions provide additional material for contact silicidation processes and reduce deep source/drain junction resistance and source/drain series resistance.
• embodiments of the present invention which provide a method of forming a semiconductor arrangement, comprising the steps of forming a gate electrode having sidewalls, employing an exposure tool to define the gate electrode. Sidewall spacers are formed in the sidewalls of the gate electrode by employing the same exposure tool to define the sidewall spacers.
• a pattern spacer may be formed with very tight alignment specifications.
• the resulting pattern spacer can encapsulate the pattern polysilicon gate structures and protect the sidewalls of the polysilicon gate during selective epitaxial growth to prevent unwanted selective epitaxial growth.
• the width of the spacer pattern is controlled by the photolithography process parameters, as well as etch process parameters.
• the spacer pattern may be purposefully aligned with an offset to create asymmetric spacers, allowing for enhanced device performance that is achievable with asymmetric spacers.
• This method comprises the steps of forming a gate electrode having sidewalls, and forming sidewall spacers on the sidewalls by: deposing a spacer layer over the gate electrode; forming a patterned resist mask over the spacer layer; and etching a spacer layer in accordance with the patterned resist mask.
• Figure 1 is a schematic depiction of a portion of a semiconductor wafer during one phase of manufacturing in accordance with embodiments of the present invention.
• Figure 2 depicts a structure of Figure 1 following the formation of a gate electrode in accordance with embodiments of the present invention.
• Figure 3 shows the structure of Figure 2 following the deposition of a spacer layer in accordance with embodiments of the present invention.
• Figure 4 depicts the structure of Figure 3 after definition of a resist pattern in accordance with embodiments of the present invention.
• Figure 5 shows the structure of Figure 4 following etching of the spacer layer in accordance with embodiments of the present invention.
• Figure 6 depicts the structure of Figure 5 after the resist has been removed in accordance with embodiments of the present invention.
• Figure 7 shows the structure of Figure 6 following selective epitaxial growth in accordance with embodiments of the present invention.
• Figure 8 depicts formation of an asymmetrical spacer arrangement in accordance with embodiments of the present invention.
• Figure 9 is a schematic depiction of a side view of a conventional exposure tool that can be used to perform the methods of the present invention.
• the present invention addresses and solves problems related to the protection of polysilicon gate electrodes during a selective epitaxial growth process, and the formation of raised source drains and their separation from the polysilicon gate electrode sidewalls.
• the present invention achieves precise spacing of the raised source and drains and ensures protection of the sidewalls of the polysilicon gate electrode by employing the same specific exposure tool used to define the polysilicon gate pattern to define the patterned spacer with very tight alignment specifications.
• the resulting patterned spacer encapsulates the patterned polysilicon gate electrode structures and protects the polysilicon gate sidewalls during selective epitaxial growth. This prevents unwanted selective epitaxial growth of silicon at the gate electrode.
• the width of the spacer pattern is precisely controlled by the photolithography process parameters and the etch process parameters.
• the spacer pattern is purposefully aligned with an offset to create asymmetric spacers, allowing for enhancement of device performance through the implantation process.
• FIG. 1 schematically depicts a portion of a semiconductor device, in cross-section, formed in accordance with embodiments of the present invention.
• a substrate 10 is provided that may be any suitable substrate, but in an exemplary embodiment, is a silicon substrate.
• the gate layer 12 is formed by a conventional deposition technique on the substrate 10.
• a gate layer 12 may be made of polysilicon, for example.
• the depth of the gate layer 12 should be equal to the preferred depth of the final gate electrode structure that is desired.
• a cap layer 14 is formed on the gate layer 12 and maybe any suitable depth to provide protection to the top of the polysilicon gate electrode during certain stages of processing. In certain embodiments, the cap layer 14 is made of silicon nitride, for example.
• Figure 2 depicts the structure of Figure 1 following an etching process to form a gate electrode 20.
• the etching process employs a specific exposure tool to define the polysilicon gate electrode pattern.
• a conventional exposure tool may be employed, such as that shown in Figure 9 and briefly described later.
• a conventional 193 nm wavelength step and scan exposure tool may be employed, using a specific pattern reticle to form a mask. The mask is then used in the etching of the polysilicon gate electrode.
• a spacer layer 16 is deposited, as is depicted in Figure 3.
• a conventional blanket deposition process such as chemical vapor deposition (CVD) or other suitable methodology, may be employed to form the spacer layer 16.
• Conventional spacer materials such as silicon oxide or silicon nitride, or other suitable material, forms the spacer layer 16.
• spacers are then defined and patterned.
• the semiconductor wafer is provided in the same, specific exposure tool as employed to form the polysilicon gate electrode.
• the same pattern reticle that was used to define the polysilicon gate electrode pattern is now used to define the patterned spacer.
• the same specific exposure tool such as that used in Figure 9, is also used to form a photoresist mask 18 over the polysilicon gate electrode 20, as depicted in Figure 4. This approach takes advantage of advances in exposure tool lens performance and overlay registration (alignment) performance, as well as advances in reticle manufacturing tolerances.
• a selective epitaxial growth process is performed to create regions of selective epitaxial growth 26. These regions are provided at specific distances from the polysilicon gate electrode by the spacers 22 having a precise width W. The entirety of the polysilicon gate electrode 20 is protected from unwanted selective epitaxial growth by the spacers 22 during this process. At this stage, the spacer layer 16 may be etched or removed completely for further processing.
• spacers 22 in Figure 6 and Figure 7 depicts spacers that have a symmetrical width.
• asymmetric spacers are formed that have different widths. This is depicted in Figure 8.
• Asymmetrical widths of spacers provide enhancement to device performance, by allowing asymmetrical doping to achieve improved performance for individual transistors.
• asymmetrical spacers allow decoupling of the optimum characteristic of an n-channel transistor from a p-channel transistor, as well as decoupling performance of similarly doped n-type transistors or p-type transistors depending upon the function, such as maximizing drive current or optimizing short channel effects.
• the asymmetrical spacers are achieved in accordance with embodiments of the present invention by purposefully aligning the spacer pattern with an offset.
• an offset value may be placed in the alignment parameters of the exposure tool.
• the photoresist 18 will not be aligned in a centered manner over the polysilicon gate electrode 20, but rather in an offset manner by a desired amount.
• Etching of the spacer layer 16 then produces the structure of
• an exemplary step and scan exposure tool is depicted schematically in Figure 9, and includes an illumination system 30 that provides illumination to the arrangement.
• a pattern reticle 32 is held by a reticle platen 34.
• the same specific reticle 32 is employed in both the patterning of the polysilicon gate electrode 20 and the spacers 22.
• a lens arrangement 36 focuses the light from the illumination system 30 onto a semiconductor wafer 38 held by a chuck 40.
• a controller 42 controls the operation of the step and scan exposure tool.
• spacers of precisely controlled specific dimensions can be created to protect the polysilicon sidewalls during selective epitaxial silicon growth, thereby preventing unwanted selective epitaxial growth from occurring at the exposed areas of the polysilicon gate electrode.

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• Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Manufacturing & Machinery (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Insulated Gate Type Field-Effect Transistor (AREA)
• Electrodes Of Semiconductors (AREA)
• Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
• Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

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Publications (2)

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• 2004
  • 2004-12-03 US US11/002,586 patent/US7279386B2/en not_active Expired - Fee Related
• 2005
  • 2005-11-24 TW TW094141232A patent/TWI397107B/zh not_active IP Right Cessation
  • 2005-11-29 JP JP2007544490A patent/JP2008522441A/ja active Pending
  • 2005-11-29 CN CNB2005800392172A patent/CN100459052C/zh not_active Expired - Fee Related
  • 2005-11-29 EP EP05852586A patent/EP1829092B1/en not_active Expired - Lifetime
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  • 2005-11-29 DE DE602005011483T patent/DE602005011483D1/de not_active Expired - Lifetime
  • 2005-11-29 KR KR1020077012157A patent/KR101142992B1/ko not_active Expired - Fee Related

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