Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
  • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
  • H01L21/3065—Plasma etching; Reactive-ion etching
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
  • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices

Definitions

• This invention relates to increasing die strength by etching during or after dicing a semiconductor wafer.
• Etching of semiconductors such as silicon with spontaneous etchants is known with a high etch selectivity to a majority of capping, or encapsulation, layers used in the semiconductor industry.
• spontaneous etchants will be understood etchants which etch without a need for an external energy source such as electricity, kinetic energy or thermal activation. Such etching is exothermic so that more energy is released during the reaction than is used to break and reform inter-atomic bonds of the reactants.
• US 6,498,074 discloses a method of dicing a semiconductor wafer part way through with a saw, laser or masked etch from an upper side of the wafer to form grooves at least as deep as an intended thickness of die to be singulated from the wafer.
• a backside of the wafer, opposed to the upper side is dry etched, for example with an atmospheric pressure plasma etch of CF 4 , past a point at which the grooves are exposed to remove damage and resultant stress from sidewalls and bottom edges and corners of the die, resulting in rounded edges and corners.
• a protective layer such as a polyimide, is used after grooving to hold the die together after singulation and during etching and to protect the circuitry on the top surface of the wafer from etchant passing through the grooves.
• a method of dicing a semiconductor wafer having an active layer comprising the steps of: mounting the semiconductor wafer on a carrier with the active layer away from the carrier; at least partially dicing the semiconductor wafer on the carrier from a major surface of the semiconductor wafer to form an at least partially diced semiconductor wafer; and etching the at least partially diced semiconductor wafer on the carrier from the said major surface with a spontaneous etchant to remove sufficient semiconductor material from a die produced from the at least partially diced semiconductor wafer to improve flexural bend strength of the die.
• the step of at least partially dicing the semiconductor wafer comprises dicing the semiconductor wafer completely through the semiconductor wafer; and the step of etching the semiconductor wafer comprises etching sidewalls of the die, remaining portions of the die being masked from the spontaneous etchant by portions of the active layer on the die.
• the step of at least partially dicing the semiconductor wafer comprises partially dicing the semiconductor wafer along dicing lanes to leave portions of semiconductor material bridging the dicing lanes; and the step of etching the semiconductor wafer comprises etching sidewalls of the dicing lanes and etching away the portions of semiconductor material bridging the dicing lanes to singulate the die.
• the semiconductor wafer is a silicon wafer.
• the step of etching with a spontaneous etchant comprises etching with xenon difluoride.
• the step of etching with a spontaneous etchant comprises providing an etching chamber and etching the semiconductor wafer within the etching chamber.
• the step of etching with a spontaneous etchant within the etching chamber comprises cyclically supplying the chamber with spontaneous etchant and purging the etching chamber of spontaneous etchant for a plurality of cycles.
• a dicing apparatus for dicing a semiconductor wafer having an active layer comprising: carrier means on which the semiconductor wafer is mountable with the active layer away from the carrier; laser or mechanical sawing means arranged for at least partially dicing the semiconductor wafer on the carrier from a major surface of the semiconductor wafer to form an at least partially diced semiconductor wafer; and etching means arranged for etching the at least partially diced semiconductor wafer on the carrier from the said major surface with a spontaneous etchant to remove sufficient semiconductor material from a die produced from the at least partially diced semiconductor wafer to improve flexural bend strength of the die.
• the dicing apparatus is arranged for dicing a silicon wafer.
• the etching means is arranged to etch with xenon difluoride.
• the dicing apparatus further comprises an etching chamber arranged for etching the semiconductor wafer mounted on the carrier means within the etching chamber.
• the etching chamber is arranged for cyclically supplying the chamber with spontaneous etchant and purging the etching chamber of spontaneous etchant for a plurality of cycles.
• Figure 1 is a schematic flow diagram of a first embodiment of the invention comprising active side up dicing followed by spontaneous etching;
• Figure 2 is a schematic flow diagram of a second embodiment of the invention comprising active face up partial dicing followed by die release by spontaneous etching;
• Figure 3 is a graph of survival probability as ordinates versus die strength as abscissa of a laser-cut control wafer and wafers etched to various extents according to the invention as measured by a 3 -point test;
• Figure 4 is a graph of survival probability as ordinates versus die strength as abscissa of a saw-cut control wafer and wafers etched to various extents according to the invention as measured by a 3-point test
• Figure 5 is a graph of survival probability as ordinates versus die strength as abscissa of a laser-cut control wafer and wafers etched to various extents according to the invention as measured by a 4-point test;
• Figure 6 is a graph of survival probability as ordinates versus die strength as abscissa of a saw-cut control wafer and wafers etched to various extents according to the invention as measured by a 4-point test;
• Figure 7 shows micrographs of sidewalls of a laser-cut control wafer and of laser-cut wafers etched to various extents according to the invention.
• Figure 8 is of micrographs of sidewalls of a saw-cut control wafer and of saw-cut wafers etched to various extents according to the invention.
• a silicon wafer 11 on a standard dicing tape 12 and tape frame 13 is mounted on a carrier, not shown.
• the wafer is diced using a laser or a mechanical saw on the carrier to produce a diced wafer 111.
• the laser may be a diode-pumped solid-state laser, a mode-locked laser or any other laser suitable for machining the semiconductor and other materials of the wafer. Suitable laser wavelengths may be selected from infrared to ultraviolet wavelengths.
• the diced wafer 111 is placed on the carrier in a chamber 14, the chamber having an inlet port 141 and an outlet port 142.
• Cycles of xenon difluoride (XeF 2 ), or any other spontaneous etchant of silicon, are input through the inlet port 141 and purged through the outlet port 142 for a predetermined number of cycles each of a predetermined duration.
• the etching may be carried out as a continuous process, but this has been found to be less efficient in terms of etch rate and etchant usage.
• the dies are then released from the tape 12 and mounted onto a die pad 15 or another die to form a mounted die 16.
• a wafer 11, with an active layer uppermost, is diced followed by spontaneous etching.
• the wafer 11 is mounted active face up on a wafer carrier on a tape 12 and a tape frame 13, that is, with the active layer away from the carrier.
• the wafer is diced with a mechanical dicing saw or a laser dicing saw on the carrier to form an active side up, diced wafer 111.
• the diced wafer 111 is placed face up in an etching chamber 14 and a spontaneous etchant 140 of silicon is input into the chamber 14 through the inlet port 141 to come in contact with the diced wafer 111 for a pre ⁇ defined period.
• the etchant can be, but is not limited to, XeF 2 and can be either a gas or liquid.
• the diced wafer 111 is held in place in the chamber 14 by the wafer carrier, not shown, which can be made of any flexible or inflexible material that holds the wafer in place either through the use of an adhesive layer or by mechanical means such as physical, electrical or vacuum clamping.
• the wafer carrier can be opaque or optically transparent.
• singulated etched dies 16 are removed from the carrier and mounted onto a die pad 15 or another die.
• the active layer acts as a mask to the spontaneous etchant and only the sidewalls of the dies are etched to remove a layer of silicon. The etching of the sidewall changes the physical nature of the sidewall thereby increasing the average die strength, as measured to destruction with a three-point or four-point test.
• a wafer 11, with an active layer uppermost is mounted active side up on a tape 12 and tape frame 13 on a wafer carrier 17.
• the wafer carrier 17 can be made of any optically transparent flexible or inflexible material that is suitable for holding the wafer in place either through the use of an adhesive layer or by mechanical means such as mechanical, electrical or vacuum clamping.
• the wafer 11 is partially diced through along dice lanes.18 with a mechanical dicing saw or a laser dicing saw to form a partially diced wafer 112.
• the partially diced wafer 112 is placed face up, on the carrier 17, in an etching chamber 14 to come into contact with a spontaneous etchant 140 of silicon until the etchant 140 has etched away a remaining portion of silicon in the dice lanes.
• the etchant can be, but is not limited to, XeF 2 and can be either a gas or liquid.
• die strength is also enhanced because the dies are diced substantially simultaneously, avoiding any stress build up which may occur in conventionally diced wafers.
• the process of the invention provides the advantages over other etch processes, such as chemical or plasma etching, of being a fully integrated, dry, controllable, gas process, so that no specialist wet chemical handling is required, and clean, safe and user-friendly materials are used in a closed handling system that lends itself well to automation.
• etch processes such as chemical or plasma etching
• cycle time is of the order of dicing process time, so that throughput is not restricted.
• the invention uses a tape- compatible etch process which is also compatible with future wafer mounts, such as glass.
• no plasma is used, as in the prior art, which might otherwise induce electrical damage on sensitive electrical devices.
• the invention provides an inexpensive process which, used with laser dicing, provides a lower cost dicing process than conventional dicing processes.
• Ten 125mm diameter 180 ⁇ m thick silicon wafers were coated with standard photoresist. The wafers were split into two groups as shown in Table 1 with five wafers undergoing laser dicing and five wafers undergoing dicing by mechanical saw.
• the die strength of each wafer was measured using 3-point and 4-point flexural bend strength testing.
• Figure 7(a) shows a laser-cut un-etched die corner at x200 magnification
• Figure 7(b) shows a laser-cut un-etched sidewall at x800 magnification
• Figure 7(c) shows a laser-cut die corner etched 4 ⁇ m at x250 magnification
• Figure 7(d) shows a laser-cut sidewall etched 4 ⁇ m at x600 magnification
• Figure 7(e) shows a laser-cut die corner etched 25 ⁇ m at x250 magnification
• Figure 7(f) shows a laser-cut sidewall etched 25 ⁇ m at x700 magnification.
• Figure 8(a) shows a saw-cut un-etched die corner at x400 magnification
• Figure 8(b) shows a saw-cut un-etched sidewall at x300 magnification
• Figure 8(c) shows a saw-cut die corner etched 4 ⁇ m at x300 magnification
• Figure 8(d) shows a saw-cut sidewall with no resist etched 4 ⁇ m at x300 magnification
• Figure 8(e) shows a saw-cut die corner etched 25 ⁇ m at x500 magnification
• Figure 8(f) shows a saw-cut sidewall etched 25 ⁇ m at x300 magnification.
• any suitable liquid or gaseous spontaneous etchant such as a halide or hydrogen compound, for example F 2 , Cl 2 , HCl or HBr may be used with silicon or another semiconductor.

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• Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• Microelectronics & Electronic Packaging (AREA)
• General Physics & Mathematics (AREA)
• Manufacturing & Machinery (AREA)
• Computer Hardware Design (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• Power Engineering (AREA)
• Plasma & Fusion (AREA)
• Dicing (AREA)
• Weting (AREA)
• Drying Of Semiconductors (AREA)
• Polishing Bodies And Polishing Tools (AREA)
• Processing Of Stones Or Stones Resemblance Materials (AREA)

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Publications (1)

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Cited By (5)

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Citations (5)

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• 2004
  • 2004-11-01 GB GB0424195A patent/GB2420443B/en not_active Expired - Fee Related
• 2005
  • 2005-10-31 TW TW094138107A patent/TWI278032B/zh active
  • 2005-11-01 WO PCT/EP2005/011671 patent/WO2006048230A1/en not_active Ceased
  • 2005-11-01 KR KR1020077008211A patent/KR20070051360A/ko not_active Ceased
  • 2005-11-01 EP EP05808203A patent/EP1825507B1/en not_active Expired - Lifetime
  • 2005-11-01 JP JP2007538353A patent/JP4690417B2/ja not_active Expired - Fee Related
  • 2005-11-01 CN CN2005800441751A patent/CN101088157B/zh not_active Expired - Fee Related
  • 2005-11-01 US US11/666,796 patent/US20090191690A1/en not_active Abandoned
  • 2005-11-01 AT AT05808203T patent/ATE526681T1/de not_active IP Right Cessation
• 2010
  • 2010-01-28 JP JP2010016318A patent/JP2010147488A/ja active Pending

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