GB2420443B - Increasing die strength by etching during or after dicing - Google Patents

Increasing die strength by etching during or after dicing

Info

Publication number
GB2420443B
GB2420443B GB0424195A GB0424195A GB2420443B GB 2420443 B GB2420443 B GB 2420443B GB 0424195 A GB0424195 A GB 0424195A GB 0424195 A GB0424195 A GB 0424195A GB 2420443 B GB2420443 B GB 2420443B
Authority
GB
United Kingdom
Prior art keywords
dicing
carrier
semiconductor wafer
etching during
die strength
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
GB0424195A
Other languages
English (en)
Other versions
GB2420443A (en
GB0424195D0 (en
Inventor
Adrian Boyle
David Gillen
Richard Toftness
Kali Dunne
Eva Fernandes Gomez
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xsil Technology Ltd
Electro Scientific Industries Inc
Original Assignee
Xsil Technology Ltd
Electro Scientific Industries Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xsil Technology Ltd, Electro Scientific Industries Inc filed Critical Xsil Technology Ltd
Priority to GB0424195A priority Critical patent/GB2420443B/en
Publication of GB0424195D0 publication Critical patent/GB0424195D0/en
Priority to TW094138107A priority patent/TWI278032B/zh
Priority to US11/666,796 priority patent/US20090191690A1/en
Priority to KR1020077008211A priority patent/KR20070051360A/ko
Priority to CN2005800441751A priority patent/CN101088157B/zh
Priority to PCT/EP2005/011671 priority patent/WO2006048230A1/en
Priority to EP05808203A priority patent/EP1825507B1/en
Priority to JP2007538353A priority patent/JP4690417B2/ja
Priority to AT05808203T priority patent/ATE526681T1/de
Publication of GB2420443A publication Critical patent/GB2420443A/en
Application granted granted Critical
Publication of GB2420443B publication Critical patent/GB2420443B/en
Priority to JP2010016318A priority patent/JP2010147488A/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Dicing (AREA)
  • Weting (AREA)
  • Drying Of Semiconductors (AREA)
  • Polishing Bodies And Polishing Tools (AREA)
  • Processing Of Stones Or Stones Resemblance Materials (AREA)
GB0424195A 2004-11-01 2004-11-01 Increasing die strength by etching during or after dicing Expired - Fee Related GB2420443B (en)

Priority Applications (10)

Application Number Priority Date Filing Date Title
GB0424195A GB2420443B (en) 2004-11-01 2004-11-01 Increasing die strength by etching during or after dicing
TW094138107A TWI278032B (en) 2004-11-01 2005-10-31 Increasing die strength by etching during or after dicing
US11/666,796 US20090191690A1 (en) 2004-11-01 2005-11-01 Increasing Die Strength by Etching During or After Dicing
KR1020077008211A KR20070051360A (ko) 2004-11-01 2005-11-01 웨이퍼 다이싱 과정 중 또는 다이싱 과정 이후 에칭에 의해다이 강도를 증가시키는 방법
CN2005800441751A CN101088157B (zh) 2004-11-01 2005-11-01 通过在分割期间或之后进行蚀刻来增强晶片强度
PCT/EP2005/011671 WO2006048230A1 (en) 2004-11-01 2005-11-01 Increasing die strength by etching during or after dicing
EP05808203A EP1825507B1 (en) 2004-11-01 2005-11-01 Increasing die strength by etching during or after dicing
JP2007538353A JP4690417B2 (ja) 2004-11-01 2005-11-01 半導体ウエハのダイシング方法及びダイシング装置
AT05808203T ATE526681T1 (de) 2004-11-01 2005-11-01 Vergrössern der chipbelastungsfähigkeit durch ätzen während oder nach des zerteilens
JP2010016318A JP2010147488A (ja) 2004-11-01 2010-01-28 ダイシング中あるいは後のエッチングによるダイ強度の増加

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB0424195A GB2420443B (en) 2004-11-01 2004-11-01 Increasing die strength by etching during or after dicing

Publications (3)

Publication Number Publication Date
GB0424195D0 GB0424195D0 (en) 2004-12-01
GB2420443A GB2420443A (en) 2006-05-24
GB2420443B true GB2420443B (en) 2009-09-16

Family

ID=33515886

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0424195A Expired - Fee Related GB2420443B (en) 2004-11-01 2004-11-01 Increasing die strength by etching during or after dicing

Country Status (9)

Country Link
US (1) US20090191690A1 (enExample)
EP (1) EP1825507B1 (enExample)
JP (2) JP4690417B2 (enExample)
KR (1) KR20070051360A (enExample)
CN (1) CN101088157B (enExample)
AT (1) ATE526681T1 (enExample)
GB (1) GB2420443B (enExample)
TW (1) TWI278032B (enExample)
WO (1) WO2006048230A1 (enExample)

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AU2003224098A1 (en) * 2002-04-19 2003-11-03 Xsil Technology Limited Laser machining
JP2008159985A (ja) * 2006-12-26 2008-07-10 Matsushita Electric Ind Co Ltd 半導体チップの製造方法
JP2009111147A (ja) * 2007-10-30 2009-05-21 Denso Corp 半導体チップ及びその製造方法
GB2458475B (en) * 2008-03-18 2011-10-26 Xsil Technology Ltd Processing of multilayer semiconductor wafers
GB2459302A (en) * 2008-04-18 2009-10-21 Xsil Technology Ltd A method of dicing wafers to give high die strength
GB2459301B (en) * 2008-04-18 2011-09-14 Xsil Technology Ltd A method of dicing wafers to give high die strength
KR101140369B1 (ko) * 2010-03-26 2012-05-03 최선규 이플루오르화크세논을 이용한 기판 가공장치 및 다이싱 방법
US8071429B1 (en) 2010-11-24 2011-12-06 Omnivision Technologies, Inc. Wafer dicing using scribe line etch
US8666530B2 (en) * 2010-12-16 2014-03-04 Electro Scientific Industries, Inc. Silicon etching control method and system
US8673741B2 (en) 2011-06-24 2014-03-18 Electro Scientific Industries, Inc Etching a laser-cut semiconductor before dicing a die attach film (DAF) or other material layer
US8399281B1 (en) * 2011-08-31 2013-03-19 Alta Devices, Inc. Two beam backside laser dicing of semiconductor films
US8361828B1 (en) * 2011-08-31 2013-01-29 Alta Devices, Inc. Aligned frontside backside laser dicing of semiconductor films
US8536025B2 (en) * 2011-12-12 2013-09-17 International Business Machines Corporation Resized wafer with a negative photoresist ring and design structures thereof
US8952413B2 (en) 2012-03-08 2015-02-10 Micron Technology, Inc. Etched trenches in bond materials for die singulation, and associated systems and methods
US8664089B1 (en) * 2012-08-20 2014-03-04 Semiconductor Components Industries, Llc Semiconductor die singulation method
US9034733B2 (en) 2012-08-20 2015-05-19 Semiconductor Components Industries, Llc Semiconductor die singulation method
JP6166034B2 (ja) * 2012-11-22 2017-07-19 株式会社ディスコ ウエーハの加工方法
US8980726B2 (en) * 2013-01-25 2015-03-17 Applied Materials, Inc. Substrate dicing by laser ablation and plasma etch damage removal for ultra-thin wafers
WO2014126559A1 (en) 2013-02-13 2014-08-21 Hewlett-Packard Development Company, L.P. Fluid ejection device
US9472458B2 (en) 2014-06-04 2016-10-18 Semiconductor Components Industries, Llc Method of reducing residual contamination in singulated semiconductor die
JP6282194B2 (ja) * 2014-07-30 2018-02-21 株式会社ディスコ ウェーハの加工方法
US9601437B2 (en) 2014-09-09 2017-03-21 Nxp B.V. Plasma etching and stealth dicing laser process
US9337098B1 (en) 2015-08-14 2016-05-10 Semiconductor Components Industries, Llc Semiconductor die back layer separation method
JP6587911B2 (ja) * 2015-11-16 2019-10-09 株式会社ディスコ ウエーハの分割方法
CN108630599A (zh) * 2017-03-22 2018-10-09 东莞新科技术研究开发有限公司 芯片的形成方法
US10373869B2 (en) 2017-05-24 2019-08-06 Semiconductor Components Industries, Llc Method of separating a back layer on a substrate using exposure to reduced temperature and related apparatus
CN107579032B (zh) * 2017-07-27 2019-04-09 厦门市三安集成电路有限公司 一种化合物半导体器件的背面制程方法
JP7066263B2 (ja) * 2018-01-23 2022-05-13 株式会社ディスコ 加工方法、エッチング装置、及びレーザ加工装置
CN110634796A (zh) 2018-06-25 2019-12-31 半导体元件工业有限责任公司 用于处理电子管芯的方法及半导体晶圆和管芯的切单方法
US10916474B2 (en) 2018-06-25 2021-02-09 Semiconductor Components Industries, Llc Method of reducing residual contamination in singulated semiconductor die
JP7109862B2 (ja) * 2018-07-10 2022-08-01 株式会社ディスコ 半導体ウェーハの加工方法
US11217550B2 (en) 2018-07-24 2022-01-04 Xilinx, Inc. Chip package assembly with enhanced interconnects and method for fabricating the same
JP7296835B2 (ja) * 2019-09-19 2023-06-23 株式会社ディスコ ウェーハの処理方法、及び、チップ測定装置

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US4610079A (en) * 1980-01-22 1986-09-09 Tokyo Shibaura Denki Kabushiki Kaisha Method of dicing a semiconductor wafer
JPH02305450A (ja) * 1989-05-19 1990-12-19 Mitsubishi Electric Corp 加速度センサの製造方法
JPH03183153A (ja) * 1989-12-12 1991-08-09 Fujitsu Ltd 半導体装置の製造方法
JPH07201784A (ja) * 1994-01-07 1995-08-04 Fujitsu Ltd 半導体装置の製造方法
US20020013061A1 (en) * 1996-10-29 2002-01-31 Oleg Siniaguine Thinning and dicing of semiconductor wafers using dry etch, and obtaining semiconductor chips with rounded bottom edges and corners
US6730579B1 (en) * 1999-02-05 2004-05-04 Sharp Kabushiki Kaisha Method of manufacturing a semiconductor dice by partially dicing the substrate and subsequent chemical etching
US20040137700A1 (en) * 2002-02-25 2004-07-15 Kazuma Sekiya Method for dividing semiconductor wafer
JP2004260075A (ja) * 2003-02-27 2004-09-16 Seiko Epson Corp 半導体チップの製造方法、半導体チップ、電気光学装置、および電子機器
US20040182817A1 (en) * 2002-12-10 2004-09-23 Hidetoshi Murai Method for manufacturing electro-optical device, electro-optical device, and electronic apparatus
US20040212047A1 (en) * 2003-04-22 2004-10-28 Joshi Subhash M. Edge arrangements for integrated circuit chips
JP2005280832A (ja) * 2004-03-27 2005-10-13 Michiaki Ito 収容袋巻装体

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4610079A (en) * 1980-01-22 1986-09-09 Tokyo Shibaura Denki Kabushiki Kaisha Method of dicing a semiconductor wafer
JPH02305450A (ja) * 1989-05-19 1990-12-19 Mitsubishi Electric Corp 加速度センサの製造方法
JPH03183153A (ja) * 1989-12-12 1991-08-09 Fujitsu Ltd 半導体装置の製造方法
JPH07201784A (ja) * 1994-01-07 1995-08-04 Fujitsu Ltd 半導体装置の製造方法
US20020013061A1 (en) * 1996-10-29 2002-01-31 Oleg Siniaguine Thinning and dicing of semiconductor wafers using dry etch, and obtaining semiconductor chips with rounded bottom edges and corners
US6730579B1 (en) * 1999-02-05 2004-05-04 Sharp Kabushiki Kaisha Method of manufacturing a semiconductor dice by partially dicing the substrate and subsequent chemical etching
US20040137700A1 (en) * 2002-02-25 2004-07-15 Kazuma Sekiya Method for dividing semiconductor wafer
US20040182817A1 (en) * 2002-12-10 2004-09-23 Hidetoshi Murai Method for manufacturing electro-optical device, electro-optical device, and electronic apparatus
JP2004260075A (ja) * 2003-02-27 2004-09-16 Seiko Epson Corp 半導体チップの製造方法、半導体チップ、電気光学装置、および電子機器
US20040212047A1 (en) * 2003-04-22 2004-10-28 Joshi Subhash M. Edge arrangements for integrated circuit chips
JP2005280832A (ja) * 2004-03-27 2005-10-13 Michiaki Ito 収容袋巻装体

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Also Published As

Publication number Publication date
EP1825507A1 (en) 2007-08-29
JP2008518450A (ja) 2008-05-29
JP4690417B2 (ja) 2011-06-01
JP2010147488A (ja) 2010-07-01
CN101088157B (zh) 2010-06-23
TWI278032B (en) 2007-04-01
CN101088157A (zh) 2007-12-12
GB2420443A (en) 2006-05-24
ATE526681T1 (de) 2011-10-15
GB0424195D0 (en) 2004-12-01
EP1825507B1 (en) 2011-09-28
US20090191690A1 (en) 2009-07-30
TW200625435A (en) 2006-07-16
WO2006048230A1 (en) 2006-05-11
KR20070051360A (ko) 2007-05-17

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Legal Events

Date Code Title Description
732E Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977)

Free format text: REGISTERED BETWEEN 20090514 AND 20090520

PCNP Patent ceased through non-payment of renewal fee

Effective date: 20171101