WO2005096323A1 - Resistance pastille - Google Patents

Resistance pastille Download PDF

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Publication number
WO2005096323A1
WO2005096323A1 PCT/JP2005/005875 JP2005005875W WO2005096323A1 WO 2005096323 A1 WO2005096323 A1 WO 2005096323A1 JP 2005005875 W JP2005005875 W JP 2005005875W WO 2005096323 A1 WO2005096323 A1 WO 2005096323A1
Authority
WO
WIPO (PCT)
Prior art keywords
chip resistor
dividing groove
chip
insulating substrate
dividing
Prior art date
Application number
PCT/JP2005/005875
Other languages
English (en)
Japanese (ja)
Inventor
Hideshi Tohyama
Toshihide Yoshida
Hirokazu Kato
Satoru Higano
Original Assignee
Mitsubishi Materials Corporation
Kamaya Electric Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Materials Corporation, Kamaya Electric Co., Ltd. filed Critical Mitsubishi Materials Corporation
Priority to CN2005800100070A priority Critical patent/CN1977347B/zh
Publication of WO2005096323A1 publication Critical patent/WO2005096323A1/fr
Priority to HK07110906.5A priority patent/HK1105713A1/xx

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C1/00—Details
    • H01C1/02—Housing; Enclosing; Embedding; Filling the housing or enclosure
    • H01C1/028—Housing; Enclosing; Embedding; Filling the housing or enclosure the resistive element being embedded in insulation with outer enclosing sheath
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C1/00—Details
    • H01C1/14—Terminals or tapping points or electrodes specially adapted for resistors; Arrangements of terminals or tapping points or electrodes on resistors
    • H01C1/142—Terminals or tapping points or electrodes specially adapted for resistors; Arrangements of terminals or tapping points or electrodes on resistors the terminals or tapping points being coated on the resistive element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C17/00—Apparatus or processes specially adapted for manufacturing resistors
    • H01C17/006—Apparatus or processes specially adapted for manufacturing resistors adapted for manufacturing resistor chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C17/00—Apparatus or processes specially adapted for manufacturing resistors
    • H01C17/02—Apparatus or processes specially adapted for manufacturing resistors adapted for manufacturing resistors with envelope or housing

Definitions

  • the present invention relates to a chip resistor, and more particularly, to a chip resistor with further improved dimensional accuracy.
  • FIGS. 5 to 7 show the internal structure of a chip resistor manufactured by a conventional method.
  • a lattice-shaped dividing groove 2 is formed on both sides (or one side) of a sheet-like insulating substrate 1 made of ceramics or the like in a primary direction and a secondary direction (horizontal and vertical directions) by a blade mold or the like. 3 is provided.
  • a plurality of pairs of first upper electrodes 4a and a plurality of pairs of lower electrodes 5 are formed by printing on the insulating substrate 1 with the primary division groove 2 interposed therebetween, and then a resistance is formed between the first upper electrodes 4a.
  • the resistor 6 is formed by printing, the resistor 6 is trimmed to adjust the resistance value, and then a protective film 7 is formed thereon using a glass resin material, so that a large number of Resistors are juxtaposed
  • a chip resistor substrate can be configured.
  • the insulating substrate 1 (that is, the chip resistance substrate) is divided into strips along the primary division grooves 2, and the terminal electrodes 11 are formed on the divided surfaces by sputtering or conductive paste.
  • a second layer (second upper electrode) may be formed by printing along the primary division groove 2 in order to prevent the wraparound of the sputter.
  • the strip-shaped chip resistor substrate is divided along the secondary division grooves 3 to form a chip, and a plating layer 8 made of Ni and Sn is formed on each electrode 11 at both ends of the chip.
  • a plating layer 8 made of Ni and Sn is formed on each electrode 11 at both ends of the chip.
  • the upper and lower electrodes, the protective film, and the like are also buried in the dividing groove 3 along the secondary dividing surface.
  • Ni or Sn plating grows by the upper and lower electrodes, and extends over the ceramic side surface 10 a of the chip resistor 10 and is actually divided (see FIG. 9).
  • the terminal electrode 11 grew larger than the reference symbol W1) (reference symbol W2 in FIG. 9), and the overhang d was a factor that led to a decrease in shape and dimensional accuracy.
  • Patent Document 1 is disclosed as a technique for solving such inconvenience.
  • Patent Document 1 discloses that by forming a slit (divided groove) for dividing a large number of resistors formed in multiple on an insulating substrate into chips (chip formation) after the protective film forming step, There is disclosed a method of manufacturing a chip resistor in which an insulating substrate can be smoothly divided so that a divided surface shape can be accurately maintained.
  • Patent Document 1 JP-A-2003-86408
  • the electrode material and the protective film material adhere to and accumulate in the slit.
  • Insulation substrates can be divided smoothly and the dimensional accuracy of the divided surface shape can be kept good, but the slit shape has a U-shaped cross section. Therefore, the divided side surface of the chip is a vertical surface, and when a plating layer is formed on this vertical surface, the protrusion of the plating due to the growth of the plating directly increases the width of the chip. This is a great hindrance in further improving the shape and dimensional accuracy.
  • the present invention has been made in view of such a problem, and minimizes the protrusion of the plating after the formation of the electrode plating layer, and forms the divided surface of the chip so that the protrusion of the plating can be absorbed. Accordingly, it is an object of the present invention to provide a chip resistor which further improves chip dimensional accuracy.
  • a chip resistor substrate for manufacturing a chip resistor comprising a sheet-shaped insulating substrate and a plurality of pairs of electrodes formed on the substrate. And a plurality of resistors formed on the insulating substrate and connected to the plurality of pairs of electrodes, a protective film covering the resistors, and formed vertically and horizontally on the insulating substrate.
  • a chip resistance substrate comprising: a dividing groove for dividing an insulating substrate into chips, wherein the dividing groove has a taper, and at least an electrode material is removed in the dividing groove.
  • the insulating substrate is divided along the dividing grooves into chips in order to manufacture a chip resistor, and a plating layer is formed on both electrodes (Ni, Sn plating). )),
  • the electrode material does not exist in the dividing groove, so that the growth of the plating is suppressed, and the protrusion of the plating can be suppressed as small as possible.
  • the scattered material at the time of forming the dividing groove which adheres again to the edge of the dividing groove has a height of 3 ⁇ m or less and a width of 7 ⁇ m or less. is there.
  • the shape of the electrode edge portion of the chip resistor manufactured thereafter can be improved by extremely reducing the generation of flying objects (dross and the like).
  • the transportability of the resistor can be improved.
  • a thickness of a molten re-solidified layer formed on a wall surface of the division groove when the division groove is formed is 1. or less.
  • the division groove has a taper of 1 ⁇ 7 / ⁇ m.
  • the dividing surface has a slight taper in the dividing direction as compared with the dividing groove having a U-shaped cross section, and therefore, a chip manufactured thereafter.
  • the slight protrusion of the plating can be absorbed by the taper, and as described later, the protrusion of the plating can be suppressed to 10 m or less, and the chip dimensional accuracy including electrode plating growth can be reduced. It can be further improved.
  • the taper means the horizontal distance (h) from the edge of the divided groove to the groove bottom in FIG.
  • the division groove is formed with laser light having a wavelength of 360 nm or less.
  • a chip resistor in which the chip resistor substrate is divided along the dividing groove into a chip shape, the chip resistor including a plating layer formed on both end electrodes. A resistor is provided.
  • the overhang after the formation of the electrode plating layer is
  • a plurality of pairs of electrodes are formed on a sheet-shaped insulating substrate, and a plurality of resistors connected to the plurality of pairs of electrodes are formed on the insulating substrate.
  • Forming a protective film covering the resistor forming a dividing groove vertically and horizontally on the insulating substrate, dividing the insulating substrate along the dividing groove into a chip shape,
  • a method for manufacturing a chip resistor for forming a plating layer according to claim 1 wherein said dividing groove has a taper and at least an electrode material is removed in said dividing groove when said dividing groove is formed.
  • a method for manufacturing a chip resistor is provided.
  • FIG. 1 is a sectional view in the primary division direction showing an internal structure of a chip resistor according to the present invention.
  • FIG. 2 is a sectional view in the secondary division direction showing an internal structure of a chip resistor according to the present invention.
  • FIG. 3 is a sectional view of a chip end showing an internal structure of a chip resistor according to the present invention.
  • FIG. 4 is an enlarged external perspective view of a chip resistor according to the present invention.
  • FIG. 5 is a cross-sectional view in the primary division direction showing a structure of a conventional chip resistor.
  • FIG. 6 is a sectional view in the secondary division direction showing the internal structure of a conventional chip resistor.
  • FIG. 7 is an enlarged external perspective view of a conventional chip resistor.
  • FIG. 8 is an enlarged cross-sectional view showing a state of groove processing by laser light (UV laser) according to the present invention.
  • FIG. 9 is a sectional view of a chip end showing an internal structure of a conventional chip resistor.
  • the present invention is intended to improve the shape and dimensional accuracy of a chip resistor by minimizing the overhang after the formation of an electrode plating layer in a chip resistor.
  • An embodiment of a chip resistor will be described with reference to FIGS.
  • FIGS. 1 to 3 show the internal structure of the chip resistor according to the present embodiment
  • FIG. 4 shows the appearance of the chip resistor in an enlarged manner.
  • the chip resistor 10 of the present embodiment is formed by forming the upper electrodes 4a, 4b and the lower electrode 5 on a sheet-like ceramic substrate by the same manufacturing process as the conventional method shown in FIGS. Through the steps of forming the resistor 6, adjusting the resistance value by trimming, and forming the protective film 7, the primary division groove 2 and the secondary division groove 3 are formed on both surfaces of the substrate by laser irradiation light. is there.
  • the laser beam L used for the groove processing preferably has a wavelength of 360 nm or less (190 to 360 nm) without carbonizing the resin layer in order to cut the resin layer and the electrode layer of the substrate!
  • the process and means for forming the dividing grooves 2 and 3 are different from those of the conventional method. As shown in the figure, the ceramic substrate 1 containing the electrode material and the protective film material is irradiated with laser light L. Then, in the groove, the electrode material and the protective film material on the substrate are vaporized by the laser beam L, and most of them can be removed. Of course, the division is smooth, and burrs do not occur on the division surface.
  • FIG. 8 shows a state of the groove karoe by the above-mentioned laser light (UV laser) having a wavelength of 360 nm or less.
  • the scattered matter (dross or the like) removed by the groove processing adheres to both edges of the divided groove 2 (3) in a protruding manner.
  • the deposit 20 deteriorates the edge shape of the electrode described later, and adversely affects the transportability of the chip resistor at the time of mounting the balter.
  • the use of a UV laser minimizes the generation of the scattered matter, and the height H of the attached matter 20 is 3 ⁇ m or less and the width W is 7 ⁇ m or less. Thereby, the electrode shape is improved, and the transportability of the chip resistor at the time of mounting the balter can be improved.
  • a molten and re-solidified layer 21 (glass layer 21) is formed on the wall surface of the divided groove 2 (3). Since the glass layer 21 is brittle and easily peels off, it may cause a disconnection accident in a plating layer, which will be described later, at the time of chip production, and the projection of the glass layer may reduce the transportability of the chip resistor. Adversely affect.
  • the thickness T of the glass layer 21 is reduced to 1.5 / zm or less by using a UV laser. This prevents the glass layer from peeling off and falling off, preventing breakage of the plating layer etc., improving the surface roughness of the dividing groove wall surface, and improving the transportability of the chip resistor during Balta mounting. Can
  • the groove can have an appropriate taper angle depending on processing conditions (irradiation beam parameters, processing parameters, and the like).
  • processing conditions are optimized so that the sectional shape of the dividing grooves 2 and 3 is intentionally given a slight teno of 1 to 7 m.
  • the ceramic substrate 1 is divided into strips along the primary division grooves 2, and an end face electrode 11 is formed on the divided surface by sputtering or conductive paste.
  • the strip-shaped chip resistor substrate is further divided along the secondary division grooves 3 to form chips.
  • each electrode 11 at both ends of the chip is plated with Ni and Sn by a barrel plating method or the like to form a plating layer 8, thereby obtaining a chip resistor 10 shown in FIG.
  • the plating layer 8 grows on the dividing side surface 10a side of the upper and lower electrode caps at the end of the secondary dividing groove.
  • the electrode material and the protective film material in the dividing groove are formed by laser. Since the photochemical reaction due to irradiation and vaporization due to high heat and most of them have been removed, the overhang of the plating has become extremely small, and the cross-sectional shape of the dividing grooves 2 and 3 has an appropriate taper. The overhang of the chip is absorbed by this taper, and the chip shape W2 including the chip growth d can be suppressed to a size close to the chip division shape W1 as much as possible. Obtainable.
  • the chip resistor is a 0603 type, and the processing conditions of the dividing groove in the present invention are as follows.
  • UV laser output (work position measurement output): 0.75W
  • the average value of the overhang dimension d can be suppressed to 6.7 m or less in the present invention product, which is 14.6 m in the comparative example. According to the invention, it was confirmed that the overhang of the plating layer could be suppressed to 10 m or less.
  • the flying objects from the results in Table 2, it is found that when the height (H) is 6 or more and the width (W) is 9.13 m or more, the transportability is somewhat adversely affected. Then, the height of the flying objects was set to 3 m or less and the width was set to 7 m or less.
  • the re-solidified layer from the results in Table 3, if the thickness (T) is 1.72 m or more, the peeling resistance is somewhat inferior. . 5 m or less.
  • the taper from the results in Table 4, it is found that when the taper (h) is 8.31 m or more, the overhang is slightly larger and it is difficult to secure the overhang dimension of 10 ⁇ m or less. In, the taper was set to 1 to 7 ⁇ m or less.
  • the dividing groove of the insulating substrate has a taper and the electrode material is removed in the dividing groove, the plating growth after the formation of the electrode plating layer is achieved.
  • the protrusion of the plating on the split side surface can be suppressed as much as possible, and the protrusion of the plating can be absorbed by the taper of the dividing surface, so that the chip shape and dimensional accuracy including the plating growth can be improved. Can be.
  • a chip resistor with good dimensional accuracy enables high-density mounting with a narrow space between adjacent parts in taping mounting and balter mounting, and reattachment of flying objects caused by the formation of division grooves.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Apparatuses And Processes For Manufacturing Resistors (AREA)

Abstract

Une pluralitE de paires d'Electrodes sont formées sur un substrat isolant en feuille, une pluralitE de rEsistances A connecter A la pluralitE de paires d'Electrodes sont formEes sur le substrat isolant, puis un film de protection recouvrant les rEsistances est formé. Ensuite, le substrat isolant est découpé en plusieurs puces le long de rainures de découpe formEes longitudinalement et latitudinalement sur le substrat isolant. Une couche de placage est formEe sur les Electrodes d'extrEmitE. Les rainures de découpe sont effilEes et l'on retire de ces rainuresle matEriau d'Electrode de mEme que le matEriau de film de protection. Comme la protubérance du placage est minimisée aprEs la formation de couche de placage d'Electrode et que la surface découpée de la puce est formEe pour absorber la protubérance du placage, on peut obtenir une rEsistance pastille possEdant en outre une plus grande prEcision des cotes.
PCT/JP2005/005875 2004-03-31 2005-03-29 Resistance pastille WO2005096323A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN2005800100070A CN1977347B (zh) 2004-03-31 2005-03-29 芯片电阻器
HK07110906.5A HK1105713A1 (en) 2004-03-31 2007-10-09 Chip resistor

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2004-104384 2004-03-31
JP2004104384 2004-03-31
JP2005068394A JP2005317927A (ja) 2004-03-31 2005-03-11 チップ抵抗器
JP2005-068394 2005-03-11

Publications (1)

Publication Number Publication Date
WO2005096323A1 true WO2005096323A1 (fr) 2005-10-13

Family

ID=35064048

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2005/005875 WO2005096323A1 (fr) 2004-03-31 2005-03-29 Resistance pastille

Country Status (6)

Country Link
JP (1) JP2005317927A (fr)
KR (1) KR101016475B1 (fr)
CN (1) CN1977347B (fr)
HK (1) HK1105713A1 (fr)
TW (1) TWI447748B (fr)
WO (1) WO2005096323A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018210786A1 (fr) * 2017-05-16 2018-11-22 Heraeus Deutschland GmbH & Co. KG Substrat céramique-métal à faible phase amorphe
EP3418266A1 (fr) * 2017-06-22 2018-12-26 Heraeus Deutschland GmbH & Co. KG Substrat en métal/céramique comprenant une phase amorphe réduite

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4602738B2 (ja) * 2004-10-29 2010-12-22 太陽社電気株式会社 チップ抵抗器の製造方法
JP5242474B2 (ja) * 2009-03-24 2013-07-24 日本特殊陶業株式会社 多数個取りセラミック配線基板
JP2012009767A (ja) * 2009-11-27 2012-01-12 Kyocera Corp 多数個取り配線基板およびその製造方法、ならびに配線基板およびその製造方法
CN102394164B (zh) * 2011-07-11 2014-04-16 广东风华高新科技股份有限公司 一种小型片式电阻的制造方法
JP6144136B2 (ja) * 2013-07-17 2017-06-07 Koa株式会社 チップ抵抗器の製造方法
KR101538416B1 (ko) * 2015-02-25 2015-07-22 랄렉 일렉트로닉 코포레이션 칩 저항기 및 그 제작 방법
JP2017224677A (ja) * 2016-06-14 2017-12-21 Koa株式会社 チップ抵抗器およびその製造方法
CN106205911B (zh) * 2016-08-30 2020-01-21 肇庆鼎晟电子科技有限公司 一种防短路的热敏芯片及其制备方法

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Publication number Priority date Publication date Assignee Title
JPH11239887A (ja) * 1998-02-23 1999-09-07 Fuji Xerox Co Ltd レーザ加工条件自動設定方法およびレーザ加工条件自動設定装置
JP2001167914A (ja) * 1999-12-08 2001-06-22 Rohm Co Ltd 絶縁基板の分割溝形状
JP2003086408A (ja) * 2001-09-11 2003-03-20 Mitsubishi Materials Corp チップ抵抗器の製造方法

Family Cites Families (6)

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Publication number Priority date Publication date Assignee Title
JPS5931983B2 (ja) * 1977-06-17 1984-08-06 日本電気株式会社 半導体装置の製造方法
JPS57183092A (en) * 1981-05-06 1982-11-11 Nippon Carbide Kogyo Kk Sintered board capable of being readily separated
JPS5830118A (ja) * 1981-08-14 1983-02-22 ティーディーケイ株式会社 電子部品、その製造方法及び製造装置
JP2002313613A (ja) * 2001-04-18 2002-10-25 Matsushita Electric Ind Co Ltd チップ電子部品の製造方法
JP2004276386A (ja) * 2003-03-14 2004-10-07 Koa Corp 分割用セラミック基板およびその製造方法
JP4227821B2 (ja) * 2003-03-24 2009-02-18 コーア株式会社 チップ抵抗器の製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11239887A (ja) * 1998-02-23 1999-09-07 Fuji Xerox Co Ltd レーザ加工条件自動設定方法およびレーザ加工条件自動設定装置
JP2001167914A (ja) * 1999-12-08 2001-06-22 Rohm Co Ltd 絶縁基板の分割溝形状
JP2003086408A (ja) * 2001-09-11 2003-03-20 Mitsubishi Materials Corp チップ抵抗器の製造方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018210786A1 (fr) * 2017-05-16 2018-11-22 Heraeus Deutschland GmbH & Co. KG Substrat céramique-métal à faible phase amorphe
US11430741B2 (en) 2017-05-16 2022-08-30 Heraeus Deutschland GmbH & Co. KG Ceramic-metal substrate with low amorphous phase
EP4212497A1 (fr) * 2017-05-16 2023-07-19 Heraeus Deutschland GmbH & Co. KG Substrat céramique-métal à faible phase amorphe
EP3418266A1 (fr) * 2017-06-22 2018-12-26 Heraeus Deutschland GmbH & Co. KG Substrat en métal/céramique comprenant une phase amorphe réduite

Also Published As

Publication number Publication date
JP2005317927A (ja) 2005-11-10
CN1977347A (zh) 2007-06-06
HK1105713A1 (en) 2008-02-22
TW200537532A (en) 2005-11-16
KR101016475B1 (ko) 2011-02-24
CN1977347B (zh) 2010-11-03
KR20070024506A (ko) 2007-03-02
TWI447748B (zh) 2014-08-01

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