Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/67—Thin-film transistors [TFT]
  • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
  • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
  • H10D30/6733—Multi-gate TFTs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
  • H10D30/0245—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET] by further thinning the channel after patterning the channel, e.g. using sacrificial oxidation on fins
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/62—Fin field-effect transistors [FinFET]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/67—Thin-film transistors [TFT]
  • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
  • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
  • H10D30/6735—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes having gates fully surrounding the channels, e.g. gate-all-around
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/01—Manufacture or treatment
  • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes

Definitions

• the present invention relates to semiconductor devices and methods of manufacturing semiconductor devices.
• the present invention has particular applicability to double-gate devices.
• MOSFETs planar metal oxide semiconductor field effect transistors
• problems associated with short channel effects such as excessive leakage between the source and drain, become increasingly difficult to overcome.
• mobility degradation and a number of process issues also make it difficult to scale conventional MOSFETs to include increasingly smaller device features. New device structures are therefore being explored to improve FET performance and allow further device scaling.
• Double-gate MOSFETs represent new structures that have been considered as candidates for succeeding existing planar MOSFETs.
• double-gate MOSFETs two gates may be used to control short channel effects.
• a FinFET is a recent double-gate structure that exhibits good short channel behavior.
• a FinFET includes a channel formed in a vertical fin.
• the FinFET structure may be fabricated using layout and process techniques similar to those used for conventional planar MOSFETs.
• Implementations consistent with the present invention provide methodology for forming a gate and thinning a fin in a FinFET device.
• the fin may be thinned in the channel region to reduce the width of the fin in that region of the FinFET device.
• the foregoing and other advantages are achieved in part by a method of forming a gate in a FinFET device.
• the method includes depositing a first dielectric layer over a silicon on insulator (SOI) wafer, where the SOI wafer includes a silicon layer on an insulating layer.
• the method also includes forming a resist mask over a portion of the first dielectric layer, etching portions of the first dielectric layer and silicon layer not covered by the resist mask to form a fin and a dielectric cap covering a top surface of the fin.
• SOI silicon on insulator
• the method further includes depositing a gate layer over the dielectric cap, depositing a second dielectric layer over the gate layer, etching the gate layer and second dielectric layer to form a gate structure, forming sidewall spacers adjacent the gate structure and forming a third dielectric layer over the gate structure and sidewall spacers.
• the method also includes planarizing the third dielectric layer to expose a top surface of the second dielectric layer, removing the second dielectric layer and the gate layer in the gate structure, etching the fin to reduce a width of the fin in a channel region of the semiconductor device and depositing a gate material to replace the removed gate layer.
• the method includes forming a fin structure on an insulating layer, where the fin structure includes a conductive fin.
• the method also includes forming source and drain regions, forming a gate over the fin structure and removing the gate to create a recessed area.
• the method further includes thinning a width of the fin in a channel region of the semiconductor device and depositing a metal in the recessed area.
• Fig. 1 is a cross-section illustrating exemplary layers that may be used for forming a fin in accordance with an embodiment of the present invention.
• Fig. 2A is a cross-section illustrating the formation of a fin in accordance with an exemplary embodiment of the present invention.
• Fig. 2B schematically illustrates the top view of the semiconductor device of Fig. 2A in accordance with an exemplary embodiment of the present invention.
• Fig. 3 A is a top view illustrating the formation of a gate structure in accordance with an exemplary embodiment of the present invention.
• Fig. 3B is a cross-section illustrating the gate formation of Fig. 3 A in accordance with an exemplary embodiment of the present invention.
• Fig. 4 is a cross-section illustrating the formation of sidewall spacers adjacent the gate structure in accordance with an exemplary embodiment of the present invention.
• Figs. 5A and 5B are cross-sections illustrating the formation of metal-silicide compound on the device of Fig. 4 in accordance with an exemplary embodiment of the invention.
• Fig. 6 is a cross-section illustrating the formation of a dielectric layer on the device of Fig. 5 in accordance with an exemplary embodiment of the present invention.
• Fig. 7A is a cross-section illustrating the planarizing of the dielectric layer on the device of Fig. 6 in accordance with an exemplary embodiment of the present invention.
• Fig. 7B illustrates the removal of a portion of the dummy gate structure in accordance with an exemplary embodiment of the present invention.
• Fig. 8 illustrates the removal of another portion of the dummy gate structure in accordance with an exemplary embodiment of the present invention.
• Fig. 9 is a cross-section illustrating the thinning of the fin in a channel region in accordance with an exemplary embodiment of the present invention.
• Fig. 10A is a cross-section illustrating the formation of a gate in accordance with an exemplary embodiment of the present invention.
• Fig. 10B is a top view illustrating the semiconductor device of Fig. 10A in accordance with an exemplary embodiment of the present invention.
• Figs. 11A-1 ID are cross-sections illustrating the formation of a gate-all-around structure in accordance with another embodiment of the present invention.
• a dummy gate may be formed in a gate area of a FinFET device.
• the dummy gate may be removed and the fin may be etched to reduce the width of the fin in the channel region of the FinFET device.
• a conductive material may then be deposited to form the gate.
• Fig. 1 illustrates the cross-section of a semiconductor device 100 formed in accordance with an embodiment of the present invention.
• semiconductor device 100 may include a silicon on insulator (SOI) structure that includes a silicon substrate 110, a buried oxide layer 120 and a silicon layer 130 on the buried oxide layer 120. Buried oxide layer 120 and silicon layer 130 may be formed on substrate 110 in a conventional manner.
• SOI silicon on insulator
• buried oxide layer 120 may include a silicon oxide, such as Si ⁇ 2 , and may have a thickness ranging from about 1500 A to about 3000 A.
• Silicon layer 130 may include monocrystalline or polycrystalline silicon having a thickness ranging from about 200 A to about 1000 A. Silicon layer 130 is used to form a fin for a FinFET transistor device, as described in more detail below.
• substrate 110 and layer 130 may comprise other semiconducting materials, such as germanium, or combinations of semiconducting materials, such as silicon-germanium.
• Buried oxide layer 120 may also include other dielectric materials.
• a dielectric layer 140 such as a silicon nitride layer or a silicon oxide layer, may be formed over silicon layer 130 to act as a protective cap during subsequent etching processes.
• dielectric layer 140 may be deposited at a thickness ranging from about 100 A to about 250 A.
• a photoresist material may be deposited and patterned to form a photoresist mask 150 for subsequent processing.
• the photoresist may be deposited and patterned in any conventional manner.
• Semiconductor device 100 may then be etched.
• silicon layer 130 may be etched in a conventional manner, with the etching terminating on buried oxide layer 120, as illustrated in Fig. 2A.
• dielectric layer 140 and silicon layer 130 have been etched to form a fin 210 comprising silicon with a dielectric cap 140.
• source and drain regions may be formed adjacent the respective ends of fin 210.
• a layer of silicon, germanium or combination of silicon and germanium may be deposited, patterned and etched in a conventional manner to form source and , drain regions.
• Fig. 2B illustrates a top view of semiconductor 100 including source region 220 and drain region 230 formed adjacent fin 210 on buried oxide layer 120, according to an exemplary embodiment of the present invention.
• the top view in Fig. 2B is oriented such that the cross-section in Fig. 2A is taken along line AA in Fig. 2B.
• the photoresist mask 150 is not illustrated in Fig. 2B for simplicity.
• the photoresist mask 150 may be removed and a gate structure may be formed on semiconductor device 100.
• the gate structure initially formed on semiconductor device 100 may be referred to as a "dummy gate” since this gate formation may be removed at a later time, as described in more detail below.
• a gate layer and a protective dielectric layer may be deposited over fin 210 and dielectric cap 140 and etched to form a dummy gate structure.
• Fig. 3A is a top view illustrating dummy gate 300.
• Fig. 3B is a cross-section of semiconductor device 100 taken along line BB in Fig. 3A after formation of the dummy gate 300. Referring to Fig.
• dummy gate 300 may include a polysilicon or amorphous silicon layer 310 and may have a thickness ranging from about 300 A to about 1000 A and a width ranging from about 50 A to about 500 A in a channel region of semiconductor device 100.
• Dummy gate 300 may also include a dielectric layer 320 that comprises, for example, silicon nitride and may have a thickness ranging from about 100 A to about 300 A.
• Dielectric layer 320 acts as a protective cap for silicon layer 310.
• a dielectric layer may then be deposited and etched to form spacers 410 adjacent opposite sides of dummy gate 300, as illustrated in Fig. 4.
• Spacers 410 may comprise a silicon oxide (e.g., Si0 2 ) or another dielectric material.
• the width of spacers 410 may range from about 50 A to about 1000 A. Spacers 410 may protect underlying fin 210 during subsequent processing and facilitate doping of source/drain regions 220 and 230. A metal layer 510 may be deposited over source/drain regions 220 and 230, as illustrated in Fig. 5A.
• metal layer 510 may include nickel, cobalt or another metal, and may be deposited to a thickness ranging from about 50 A to about 200 A.
• a thermal annealing may then be performed to form a metal-silicide layer 520, as illustrated in Fig. 5B.
• the metal may react with the silicon in source/drain regions 220 and 230 to form a metal-silicide compound, such as NiSi or CoSi 2 , based on the particular metal layer 510 deposited.
• dielectric layer 610 may be deposited over semiconductor device 100.
• dielectric layer 610 may include a tetraethyl orthosilicate (TEOS) compound and may be deposited to a thickness ranging from about 2000 A to 3000 A. In alternative implementations, other dielectric materials may be used.
• the dielectric layer 610 may then be planarized. For example, a chemical- mechanical polishing (CMP) may be performed to planarize the dielectric layer 610 with the upper surface of dielectric cap 320 and to expose the upper surface of dielectric cap 320, as illustrated in Fig. 7A.
• CMP chemical- mechanical polishing
• the dielectric cap 320 may then be removed using, for example, a wet etching procedure, as illustrated in Fig. 7B.
• the wet etch may use an acid, such as H 3 P0 , to remove dielectric cap 320.
• an acid such as H 3 P0
• an upper portion of spacers 410 and dielectric layer 610 may also removed such that the upper surface of silicon layer 310 is substantially planar with the upper surface of spacers 410 and dielectric layer 610, as illustrated in Fig. 7B.
• Silicon layer 310 may then be removed, as illustrated in Fig. 8.
• silicon layer 310 may be etched using reactants that have a high etch selectivity with respect to polysilicon. This enables silicon material 310 to be removed without removing significant portions of any of the surrounding dielectric layers, such as spacers 410 and dielectric layer 140.
• a gate opening or recess 810 is formed, as illustrated in Fig. 8.
• a gate-shaped space referred to as gate recess 810, may be created in surrounding dielectric layer 610.
• the side surfaces of silicon fin may be exposed in the channel region of semiconductor device 100.
• Fin 210 may then be etched to reduce the width of fin 210 in the channel region. For example, a wet etch process may be performed to reduce the width of fin 210 in the channel region.
• dielectric layer 610 Portions of fin 210 not in the channel region and source/drain regions 220 and 230 are covered by dielectric layer 610, which prevents those portions of semiconductor device 100 from being etched while the desired portion of fin 210 is thinned.
• Fig. 9 illustrates a top view of semiconductor device 100 after the etching. Referring to Fig. 9, the dotted lines illustrate the thinned portion of fin 210 in the channel region.
• the overall width of fin 210 may be reduced by about 20 nanometers (nm) to 100 nm as a result of the etching.
• the width of fin 210 in the channel region after the etching labeled as W in Fig. 9, may range from about 30 A to about 500 A, in an exemplary implementation of the present invention. It should be understood that the width of fin 210 may depend on the particular device requirements and other parameters, such as the gate length.
• Area 810 in Fig. 9 illustrates the gate recess after removal of the dummy gate 300.
• the dielectric layer 610 and sidewall spacers 410 are not shown in Fig. 9 for simplicity.
• thinning the width of fin 210 in the channel region enables the semiconductor device 100 to achieve good short channel control.
• forming fin 210 as described above with respect to Figs. 1 and 2A makes it very difficult to achieve a silicon fin with the desirably small width.
• the present invention forms the fin 210 and dummy gate 300 in the manner described above and then removes the dummy gate and thins the fin. This results in a desirably narrow fin, while avoiding processing difficulties associated with trying to achieve such a thin fin using lithography alone.
• the side surfaces of fin 210 may be smoother and more uniform than those achieved using lithography alone. These smoother side surfaces of fin 210 may improve carrier mobility of the vertically-oriented channels of semiconductor device 100.
• a metal layer 1010 may then be deposited to fill the gate recess 810, as illustrated in Fig. 10A. Fig.
• the metal material may comprise tungsten (W), tantalum (Ta), titanium (Ti), nickel (Ni), TaSiN, TaN, or some other metal, and may be deposited to a thickness ranging from about 200 A to about 1000 A. Semiconducting materials, such as silicon or germanium may also be used as the gate material.
• the metal layer 1010 may be polished so that the metal is substantially planar with the upper surface of spacers 410, as illustrated in Fig. 10A.
• the dotted lines in Fig. 10A illustrate the channel region of fin 210.
• Fig. 10B illustrates a top view of the semiconductor device 100 consistent with the present invention after the gate material 1010 has been deposited and planarized.
• semiconductor device 100 includes a double-gate structure with gate 1010 being disposed on either side of fin 210.
• the shaded areas in Fig. 10B represent the metal-silicide layer 520 formed over source/drain regions 220 and 230.
• Gate 1010 may include a gate electrode or contact, illustrated as gate electrode 1012 in Fig. 10B, formed at one end of gate 1010.
• a second gate electrode/contact may be formed at the opposite end of gate 1010.
• the source/drain regions 220 and 230 may then be doped.
• n-type or p-type impurities may be implanted in source/drain regions 220 and 230.
• the particular implantation dosages and energies may be selected based on the particular end device requirements.
• One of ordinary skill in this art would be able to optimize the source/drain implantation process based on the circuit requirements and such steps are not disclosed herein in order not to unduly obscure the thrust of the present invention.
• Sidewall spacers 410 aid in controlling the location of the source/drain junctions by shielding portions of fin 210 in the channel region from being implanted with impurities.
• Activation annealing may then be performed to activate the source/drain regions 220 and 230.
• the resulting semiconductor device 100 illustrated in Fig. 10B is a double-gate device with gate 1010 extending over fin 210.
• the semiconductor device 100 illustrated in Fig. 10A may be planarized, via for example, a chemical-mechanical polishing (CMP), to remove the portion of gate layer 1010 above fin 210.
• CMP chemical-mechanical polishing
• electrically and physically separated gates may be formed on either side of fin 210. Such gates may be separately biased during operation of semiconductor device 100.
• a double-gate FinFET device is formed with a thin fin in the channel region of the FinFET device.
• the resulting structure exhibits good short channel behavior.
• the metal gate reduces gate resistance and avoids poly depletion problems associated with polysilicon gates.
• the present invention can also be easily integrated into conventional semiconductor fabrication processing.
• a gate-all-around MOSFET may be formed.
• FIG. 11 A illustrates a cross-sectional view of a FinFET device 1100 that includes a buried oxide layer 1110 formed on a substrate (not shown) with a fin 1020 formed thereon.
• a dry etch process may be performed to etch a portion of buried oxide layer 1110, as illustrated in Fig. 1 IB .
• a portion of buried oxide layer 1110 located below fin 1120 may be removed.
• the etching may laterally undercut a portion of buried oxide layer 1110 located below fin 1120, indicated by areas 1130 in Fig. 11B.
• a second etch such as a wet etch, may then be performed to etch the remaining portion of buried oxide layer 1110 located below fin 1120, as illustrated in Fig. 1 IC.
• the wet etch may laterally undercut the portion of buried oxide layer 1110 located below fin 1120, effectively suspending the fin 1120 over buried oxide layer 1110 in the channel region.
• the fin 1120 remains connected to the other portions of fin 1020 that are formed on buried oxide layer 1110 and are connected to the source and drain regions (not shown).
• a gate oxide layer 1140 may then be formed on the exposed surfaces of fin 1120, as illustrated in Fig. 1 ID.
• a gate layer 1150 may then be deposited over fin 1120, as illustrated in Fig. 1 ID.
• the gate layer 1150 may surround the fin 1120 in the channel region of the semiconductor device 1100.
• the resulting semiconductor device 1100 is a gate-all-around FinFET with gate material surrounding the fin in the channel region of semiconductor device 1100.
• the dielectric and conductive layers used in manufacturing a semiconductor device in accordance with the present invention can be deposited by conventional deposition techniques.
• metallization techniques such as various types of CVD processes, including low pressure CVD (LPCVD) and enhanced CVD (ECVD) can be employed.
• LPCVD low pressure CVD
• ECVD enhanced CVD
• the present invention is applicable in the manufacturing of double-gate semiconductor devices and particularly in FinFET devices with design features of 100 nm and below.
• the present invention is applicable to the formation of any of various types of semiconductor devices, and hence, details have not been set forth in order to avoid obscuring the thrust of the present invention.
• conventional photolithographic and etching techniques are employed and, hence, the details of such techniques have not been set forth herein in detail.
• a series of processes for forming the semiconductor device of Fig. 10B has been described, it should be understood that the order of the processes may be varied in other implementations consistent with the present invention.

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