WO2004062149A1 - Ofdm復調装置 - Google Patents
Ofdm復調装置 Download PDFInfo
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- WO2004062149A1 WO2004062149A1 PCT/JP2003/016260 JP0316260W WO2004062149A1 WO 2004062149 A1 WO2004062149 A1 WO 2004062149A1 JP 0316260 W JP0316260 W JP 0316260W WO 2004062149 A1 WO2004062149 A1 WO 2004062149A1
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- 238000001514 detection method Methods 0.000 claims abstract description 124
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/26—Systems using multi-frequency codes
- H04L27/2601—Multicarrier modulation systems
- H04L27/2602—Signal structure
- H04L27/2605—Symbol extensions, e.g. Zero Tail, Unique Word [UW]
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/26—Systems using multi-frequency codes
- H04L27/2601—Multicarrier modulation systems
- H04L27/2647—Arrangements specific to the receiver only
- H04L27/2655—Synchronisation arrangements
- H04L27/2662—Symbol synchronisation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/26—Systems using multi-frequency codes
- H04L27/2601—Multicarrier modulation systems
- H04L27/2647—Arrangements specific to the receiver only
- H04L27/2655—Synchronisation arrangements
- H04L27/2668—Details of algorithms
- H04L27/2673—Details of algorithms characterised by synchronisation parameters
- H04L27/2676—Blind, i.e. without using known symbols
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/26—Systems using multi-frequency codes
- H04L27/2601—Multicarrier modulation systems
- H04L27/2647—Arrangements specific to the receiver only
- H04L27/2655—Synchronisation arrangements
- H04L27/2657—Carrier synchronisation
Definitions
- the present invention relates to an OFDM demodulation device that demodulates an orthogonal frequency division multiplexing (OFDM) modulated signal.
- OFDM orthogonal frequency division multiplexing
- OFDM orthogonal frequency division multiplexing
- PSK Phase Shift Keying
- QAM Quadrature Amplitude Modulation
- the transmission bandwidth is divided by a number of subcarriers, so the bandwidth per subcarrier wave becomes narrower and the modulation speed slows down, but the total transmission speed remains the same as the conventional modulation method. It has the feature of.
- the symbol speed is reduced, the time length of the multipath relative to the time length of the symbol can be shortened, and multipath interference is reduced. It has the feature of.
- data is allocated to a plurality of subcarriers, so an IFFT (Inverse Fast Fourier Transform) arithmetic circuit that performs inverse Fourier transform during modulation, and an FFT (Fast Fast Fourier transform) that performs Fourier transform during demodulation Fourier Transform)
- IFFT Inverse Fast Fourier Transform
- FFT Fast Fourier transform
- Terrestrial digital broadcasts employing the OFDM scheme include, for example, DVB-T (Digital Video Broadcasting-Terrestrial) and ISDB-T (Integrated Services Digital Broadcasting-Terrestrial).
- the transmission symbol of the OFDM system (hereinafter referred to as OFDM symbol) is a copy of the effective symbol, which is the signal period during which the IFFT is performed during transmission, and the waveform of a part of the latter half of the effective symbol.
- the guard interval that has been set.
- the guard interval is provided in the first half of the OFDM symbol. In the OFDM system, by providing such a guard interval, inter-symbol interference due to multipath is allowed, and multipath resistance is improved.
- I SDB- T SB mode 3 standard (terrestrial digital audio broadcasting broadcast standards adopted in Japan)
- this in I SDB-T S B standard mode 3 among the 512 subcarriers in the effective Shinporu, transmission de Isseki to 433 pieces of subcarrier is modulated.
- the time length of the guard one interval is 1/4 of the time length of the effective Shinporu, 1/8, 1/16, and one of 1/32.
- FIG. 2 shows a block diagram of a conventional OFDM transmitting apparatus.
- the OFDM transmission apparatus 100 includes a transmission path encoding circuit 101, a mapping circuit 102, an IFFT operation circuit 103, a quadrature modulation circuit 104, a D / A conversion circuit 105, A frequency conversion circuit 106, an antenna 107, and a clock generation circuit 108 are provided.
- a transport stream (TS) specified by MPEG-2 Systems is input to the transmission path encoding circuit 101.
- the transmission path coding circuit 101 performs Reed-Solomon coding processing, energy spreading processing, interleaving processing, convolution on the input TS. It performs transmission coding and OFDM frame configuration processing to generate a transmission data sequence.
- the transmission data sequence generated by the transmission path encoding circuit 101 is supplied to the matching circuit 102.
- the mapping circuit 102 divides the input transmission data sequence in units of k bits, and maps each of the divided k bits to a complex signal by BPSK, QPSK, 16 ⁇ 38 or 64 ⁇ 38.
- BPSK bit-to-bit sequence
- QPSK quadrature phase-to-semiconductor
- the complex signal output from the mapping circuit 102 is supplied to an IFFT operation circuit 103.
- the IFFT operation circuit 103 includes a serial / parallel converter 111, an I / F operator 112, a guard interval adder 113, and a parallel / serial converter 114.
- the serial / parallel converter 111 cuts out the complex signal output from the mapping circuit 102 at a predetermined position and divides it into parallel signals for each Nu sample.
- Nu is the number of valid symbol samples.
- the I-th arithmetic unit 112 performs an IFFT operation for each Nu sample and outputs Nu data, which is a signal component of an effective symbol.
- the guard interval adder 113 receives the effective symbol (Nu data unit) from the IFFT calculator 112, and copies the data of the last Ng samples of the effective symbol as it is at the beginning of the guard symbol.
- the parallel / serial converter 114 serializes an OFDM symbol composed of Ns data and outputs the serialized OFDM symbol.
- the quadrature modulation circuit 104 quadrature-modulates the complex signal output from the IFFT operation circuit 103 with respect to an IF signal having a predetermined frequency.
- the orthogonally modulated IF signal is supplied to a D / A conversion circuit 105.
- the 0/8 conversion circuit 105 converts the orthogonally modulated IF signal into an analog signal.
- the analogized IF signal is supplied to the frequency conversion circuit 106.
- the frequency conversion circuit 106 frequency-shifts the analogized IF signal to generate a transmission signal in the RF signal band.
- the transmission signal generated by frequency conversion circuit 106 is transmitted via antenna 107.
- the clock generation circuit 108 supplies an operation clock to the matching circuit 102, the IFFT operation circuit 103, the D / A conversion circuit 105, and the like.
- Non-Patent Document 1 A configuration example of a conventional OFDM receiving apparatus is shown in, for example, Non-Patent Document 1 below.
- a conventional OFDM receiver manufactured based on Non-Patent Document 1 will be described.
- FIG. 5 shows a block diagram of a conventional 0 FDM receiving apparatus.
- a conventional OFDM receiver 200 includes an antenna 201, a tuner 202, a band-pass filter (BPF) 203, an octave conversion circuit 204, a DC cancel circuit 205, and a digital quadrature demodulator.
- BPF band-pass filter
- Circuit 206 FFT operation circuit 207, frame extraction circuit 208, synchronization circuit 209, carrier demodulation circuit 210, frequency diving circuit 211, time dithering circuit 212, demapping circuit 213, bit ding leave circuit 214, depuncturing circuit 215, video circuit 216, byte ding circuit 217, spread signal elimination circuit 218, transport stream generation circuit 219, RS decoding A circuit 220, a transmission control information decoding circuit 221 and a channel selection circuit 222 are provided.
- the transmission wave transmitted from OFDM transmitting apparatus 100 is received by antenna 201 of OFDM receiving apparatus 200 and supplied to tuner 202 as an RF signal.
- the RF signal received by the antenna 201 is frequency-converted into an IF signal by a tuner 202 including a multiplier 202a and a local oscillator 202b, and supplied to a BPF 203.
- the oscillation frequency of the received carrier signal oscillated from local oscillator 202 b is switched according to the channel selection signal supplied from channel selection circuit 222.
- the IF signal output from tuner 202 is filtered by BPF 203 After that, the data is digitized by the A / D conversion circuit 204.
- the digitized IF signal is DC-removed by a DC cancel circuit 205 and supplied to a digital quadrature demodulation circuit 206.
- Digital quadrature demodulation circuit 206 quadrature demodulates the digitized IF signal using a carrier signal of a predetermined frequency (carrier frequency), and outputs a baseband OFDM signal.
- the baseband OFDM signal becomes a complex signal composed of a real axis component (I channel signal) and an imaginary axis component (Q channel signal).
- the baseband OFDM signal output from the digital quadrature demodulation circuit 206 is supplied to an FFT operation circuit 207 and a synchronization circuit 209.
- the FFT operation circuit 207 performs an FFT operation on the baseband OFDM signal, and extracts and outputs a signal orthogonally modulated to each subcarrier.
- the FFT operation circuit 207 extracts a signal of an effective symbol length from one OFDM symbol, and performs an FFT operation on the extracted signal. That is, the FFT operation circuit 207 removes a signal for one guard interval length from one OFDM symbol and performs an FFT operation on the remaining signal.
- the range of the signal extracted for performing the FFT operation may be any position of one OFDM symbol as long as the extracted signal points are continuous. That is, as shown in Fig. 1, the start position of the range of the extracted signal is from the boundary position at the beginning of the OFDM symbol (the position A in Fig. 1) to the end position of the guard interval (the position in Fig. 1). (Position B)).
- the signal modulated on each subcarrier extracted by the FFT operation circuit 207 is a complex signal composed of a real axis component (I channel signal) and an imaginary axis component (Q channel signal).
- the signal extracted by the FFT operation circuit 207 is supplied to a frame extraction circuit 208, a synchronization circuit 209, and a carrier demodulation circuit 210.
- the frame extraction circuit 208 extracts the boundary of the OFDM transmission frame based on the signal demodulated by the FFT operation circuit 207, and also includes pilot signals such as CP and SP included in the OFDM transmission frame, TMCC and The transmission control information such as TPS is demodulated and supplied to a synchronization circuit 209 and a transmission control information decoding circuit 221.
- the synchronization circuit 209 detects the baseband OFDM signal, the signal modulated on each subcarrier after demodulation by the FFT operation circuit 207, and the detection by the frame extraction circuit 208.
- the OFDM symbol boundary is calculated using the pilot signals of CP, SP, etc. thus obtained and the channel selection signal supplied from the channel selection circuit 222, and the calculation range of the FFT calculation for the FFT calculation circuit 207 and its Set the timing.
- the carrier demodulation circuit 210 is supplied with a signal demodulated from each subcarrier output from the FFT operation circuit 207, and performs carrier demodulation on the signal. For example, when demodulating an OFDM signal of the IS DB- TSB standard, the carrier demodulation circuit 210 performs, for example, differential demodulation of DQP SK or synchronous demodulation of QP SK :, 16QAM, and 64QAM.
- the carrier demodulated signal is subjected to frequency din / leave processing by a frequency din / leave circuit 211, subsequently subjected to time din / leave processing by a time din / leave circuit 212, and then to a demapping circuit 213. Supplied to
- the demapping circuit 213 performs a data reassignment process (demapping process) on the carrier-demodulated signal (complex signal) to restore a transmission data sequence. For example, in the case of demodulating the OFDM signal I SDB- T SB standard, de-mapping circuit 213 performs demapping corresponding to QPS K, 16 QAM or 64QAM.
- the transmission data sequence output from the demapping circuit 213 passes through a bit ding circuit 214, a depuncturing circuit 215, a Viterbi circuit 216, a byte ding circuit 217, and a spreading signal elimination circuit 218. Dinari processing corresponding to bit-in / leave for error dispersion of symbol, depuncturing processing corresponding to puncturing processing for reduction of transmission bits, decoding of convolutionally encoded bit sequence
- the energy despreading process corresponding to the Viterbi decoding process, the dingliving process in units of bytes, and the energy spreading process is performed, and is input to the transport stream generation circuit 219.
- the transport stream generation circuit 219 inserts data defined by each broadcasting system, such as a null packet, at a predetermined position in the stream. Further, the transport stream generation circuit 219 performs a so-called smoothing process of smoothing the bit interval of the intermittently supplied stream to obtain a temporally continuous stream.
- the transmission data sequence subjected to the smoothing process is supplied to the RS decoding circuit 220.
- the RS decoding circuit 220 performs a Reed-Solomon decoding process on the input transmission data sequence and outputs it as a transport stream defined by MPE G-2 Systems.
- the transmission control information decoding circuit 222 decodes transmission control information such as TMCC and TPS modulated at a predetermined position of the OFDM transmission frame.
- the decoded transmission control information is sent to the carrier demodulation circuit 210, the time interleave circuit 212, the demapping circuit 213, the bit deinterleaving circuit 214, and the transport stream generation circuit 219. It is supplied and used for control of demodulation and reproduction of each circuit.
- a method using a guard interval uses the correlation of the signal sequence between the guard interval and its copy source, and determines that the part with the highest autocorrelation value of the received FDM signal is the symbol boundary position. It is a method to refuse.
- the method using a pilot signal is based on the fact that if the synchronization position deviates from the correct symbol boundary, the demodulated signal component rotates in phase according to the error. This is a method to detect the symbol boundary position based on the amount.
- the method using guard intervals has the advantage of quick synchronization pull-in, but has the disadvantage of low accuracy.
- the method using a pilot signal has the advantage of high accuracy, but has the disadvantage of slow synchronization pull-in.
- the operation of the symbol synchronization process is divided into two states: at the time of pull-in and at the time of holding.At the time of pull-in, a method using a guard interpal is used. At the time of holding, a method using a pilot signal is used.
- the OFDM demodulator according to the present invention is generated by copying an effective symbol generated by time-sharing an information sequence and modulating it to a plurality of subcarriers, and copying a part of the signal waveform of the effective symbol.
- This is a device that demodulates an orthogonal frequency division multiplex (OFDM) signal whose transmission unit is a transmission symbol including a guard interval.
- OFDM orthogonal frequency division multiplex
- the OFDM demodulator detects a reference time generating means for generating a reference time based on a reference clock, and a timing at which an autocorrelation value of the guard interval portion of the OFDM signal has a peak, and A guard correlation peak time detecting means for generating the timing (peak time) synchronized with the time, and a sympol boundary time calculation for calculating, based on the peak time, a symbol boundary time which is a boundary time of the transmission symbol synchronized with the reference time. Means.
- the symbol boundary time calculation means includes: a time generation unit that generates a symbol boundary time synchronized with the reference time; an error time detection unit that detects an error time between the symbol boundary time and the peak time; An averaging unit that calculates an error time (average error time) averaged by performing a single-pass filtering, wherein the time generation unit calculates the symbol boundary time based on the average error time. .
- the OFDM demodulator according to the present invention can realize symbol synchronization processing using only the correlation of guard intervals and can improve the synchronization accuracy.
- the symbol boundary time calculating means has an asymmetric gain section that multiplies the error time by a gain and supplies the error time to an averaging section.
- the asymmetric gain unit determines whether the peak time is earlier than the symbol boundary time or the peak time is later than the symbol boundary time, and determines the peak time more than the symbol boundary time. The gain when the peak time is later than the above-mentioned symbol boundary time is also increased when the gain is earlier.
- the OFDM demodulator has a limit that the symbol boundary time calculation means limits the level of the error time and supplies the error time to the averaging unit.
- the above limiter The upper limit and the lower limit are set.If the error time exceeds the upper limit, the upper limit is output as the error time.If the error time is lower than the lower limit, the upper limit is set. And outputs the lower limit value. If the error time is between the lower limit value and the upper limit value, the error time is output.
- the OFDM demodulator according to the present invention is characterized in that an effective symbol generated by time-sharing an information sequence and modulated into a plurality of subcarriers, and a signal waveform of a part of the effective symbol are copied.
- This is a device that demodulates an orthogonal frequency division multiplexed (OFDM) signal using a transmission symbol including the guardinterpal generated by the above as a transmission unit.
- OFDM orthogonal frequency division multiplexed
- the OFDM demodulator detects a reference time generation means for generating a reference time based on a reference clock, and an evening when the autocorrelation value of the guard interval portion of the OFDM signal has a peak, and detects the reference time.
- a guard correlation peak time detecting means for generating the synchronized timing (peak time), and a sympol boundary time calculating means for calculating, based on the peak time, a symbol boundary time which is a boundary time of the transmission symbol synchronized with the reference time. It has.
- the symbol boundary time calculation means determines whether the peak time is earlier than the symbol boundary time or the peak time is later than the symbol boundary time, and determines whether the peak time is shorter than the symbol boundary time.
- the gain when the peak time is later than the symbol boundary time is larger than the gain when the symbol time is earlier, and the asymmetric gain section multiplies the gain by the peak time and the asymmetric gain section.
- an averaging unit that calculates a symbol boundary time by performing one-pass filtering of the peak time multiplied by.
- FIG. 1 is a diagram for explaining an OFDM transmission symbol.
- FIG. 2 is a block diagram of a conventional OFDM transmitting apparatus.
- FIG. 3A is a diagram for explaining a BPSK modulation method
- FIG. 3B is a diagram illustrating an OPSK modulation method
- FIG. 3C is a diagram for explaining a modulation method
- FIG. 3C is a diagram for explaining a 16 Q AM modulation method.
- FIG. 4 is a diagram showing a configuration in the IFFT arithmetic circuit.
- FIG. 5 is a block diagram of a conventional OFDM receiving apparatus.
- FIG. 6 is a block diagram of the OFDM receiving apparatus according to the first embodiment of the present invention.
- FIG. 7 is a diagram illustrating a configuration of the FFT arithmetic circuit.
- FIG. 8 is a diagram for explaining a start flag indicating a start position of the FFT calculation and a positional deviation between the OFDM symbol boundary positions. ⁇
- FIG. 9 is a block diagram of a guard correlation / peak detection circuit.
- FIG. 10 is a timing chart of each signal in the guard correlation / peak detection circuit.
- FIG. 11 is a diagram illustrating a multipath environment.
- FIG. 12 is a timing chart of each signal in the guard correlation / peak detection circuit in a multipath environment.
- FIG. 13 is a diagram illustrating peak timing values in a multipath environment.
- FIG. 14 is an evening timing chart of each signal in the guard correlation / peak detection circuit in a flat fading environment.
- FIG. 15 is a diagram illustrating peak timing values in a flat fading environment.
- Figure 16 shows a timing chart of each signal in the guard correlation / peak detection circuit in a frequency selective fading environment.
- FIG. 17 is a diagram illustrating peak timing values in a frequency selective fading environment.
- FIG. 18 is a diagram showing the output fluctuation of the free-running counter when the transmission clock of the received OFDM signal is synchronized with the clock of the receiving device.
- FIG. 19 is a diagram illustrating the output fluctuation of the free-running counter when the clock of the receiving device is faster than the transmission clock of the received OFDM signal.
- FIG. 20 is a diagram showing the output fluctuation of the free-running counter when the clock of the receiving device is slower than the transmission clock of the received OFDM signal.
- FIG. 21 is a block diagram of the timing synchronization circuit.
- FIG. 22 is a circuit configuration diagram of the clock frequency error calculation circuit.
- FIG. 23 is a circuit configuration diagram of the initial phase calculation circuit.
- FIG. 24 is a circuit configuration diagram of an initial phase calculation circuit that performs a moving average.
- FIG. 25 is a circuit configuration diagram of an initial phase calculation circuit that performs one-pass filtering.
- FIG. 26 is a circuit configuration diagram of an initial phase calculation circuit that performs median selection.
- FIG. 27 is a block diagram of the symbol boundary calculation circuit.
- FIG. 28 is a circuit configuration diagram of a phase comparison circuit in the symbol boundary calculation circuit.
- FIG. 29 is a circuit diagram of a limiter in the symbol boundary calculation circuit.
- FIG. 30 is a circuit configuration diagram of an asymmetric gain circuit in the symbol boundary calculation circuit.
- FIG. 31 is a circuit configuration diagram of the low-pass filter in the sympol boundary calculation circuit.
- FIG. 32 is a circuit configuration diagram of a clock error correction circuit in the symbol boundary calculation circuit.
- FIG. 33 is a circuit configuration diagram of a phase generation circuit in the symbol boundary calculation circuit.
- FIG. 34 is a circuit configuration diagram of the symbol boundary correction circuit and the start flag generation circuit.
- FIG. 35 is a block diagram of a symbol boundary calculation circuit of the OFDM receiver according to the second embodiment of the present invention.
- FIG. 36 is a circuit configuration diagram of a gain circuit and an asymmetric mouth-pass filter in the symbol boundary calculation circuit of the OFDM receiver according to the second embodiment of the present invention.
- FIG. 37 is a circuit configuration diagram of a guard correlation / peak detection circuit of the OFDM receiver according to the third embodiment of the present invention.
- FIG. 38 is a timing chart of each signal in the guard correlation / peak detection circuit of the OFDM receiver according to the third embodiment of the present invention.
- FIG. 39 is a circuit configuration diagram of a symbol boundary calculation circuit of the OFDM receiver according to the third embodiment of the present invention.
- FIG. 40 is a circuit configuration diagram of the clock error correction circuit in the symbol boundary calculation circuit of the OFDM receiver according to the third embodiment of the present invention.
- FIG. 41 is a circuit configuration diagram of a phase generation circuit and an output circuit in the symbol boundary calculation circuit of the OFDM receiver according to the third embodiment of the present invention.
- FIG. 42 is a block diagram of the timing synchronization circuit of the OFDM receiver according to the fourth embodiment of the present invention.
- FIG. 43 is a block diagram of a symbol boundary calculating circuit of the OFDM receiver according to the fourth embodiment of the present invention.
- FIG. 44 is a block diagram of the timing synchronization circuit of the OFDM receiver according to the fifth embodiment of the present invention.
- FIG. 45 is a block diagram of a symbol boundary calculating circuit of the OFDM receiving apparatus according to the fifth embodiment of the present invention.
- FIG. 46 is a block diagram showing a modified example of the symbol boundary calculating circuit of the OFDM receiving apparatus according to the fifth embodiment of the present invention.
- FIG. 47 is a block diagram of the timing synchronization circuit of the OFDM receiver according to the sixth embodiment of the present invention.
- FIG. 48 is a block diagram of a symbol boundary calculation circuit in the timing synchronization circuit of the OFDM receiver according to the sixth embodiment of the present invention.
- FIG. 49 is a circuit configuration diagram of the clock error calculation circuit in the symbol boundary calculation circuit of the OFDM receiver according to the sixth embodiment of the present invention.
- FIG. 50 is a circuit configuration diagram of a phase generation circuit in the symbol boundary calculation circuit of the OFDM receiver according to the sixth embodiment of the present invention.
- FIG. 51 is a block diagram of a clock frequency error calculation circuit of the OFDM receiver according to the sixth embodiment of the present invention.
- FIG. 6 shows a block diagram of the OFDM receiver according to the first embodiment of the present invention.
- the OFDM receiver 1 includes an antenna 2, a tuner 3, a non-pass filter (BPF) 4, an A / D conversion circuit 5, Clock generation circuit 6, DC cancellation circuit 7, Digital quadrature demodulation circuit 8, Carrier frequency error correction circuit 9, FFT operation circuit 10, Phase correction circuit 11, Guard correlation / peak detection circuit 12, Timing A synchronization circuit 13, a narrowband carrier error calculation circuit 14, a wideband carrier error calculation circuit 15, an addition circuit 16, a numerically controlled oscillator (NCO) 17, 3 includes a frame synchronization circuit 18, an equalization circuit 19, a demapping circuit 20, a transmission line decoding circuit 21, and a transmission control information decoding circuit 22.
- BPF non-pass filter
- NCO numerically controlled oscillator
- a digital broadcast wave broadcast from a broadcasting station is received by the antenna 2 of the OFDM receiver 1 and supplied to the tuner 3 as an RF signal.
- the RF signal received by the antenna 2 is frequency-converted into an IF signal by a tuner 3 including a multiplier 3a and a local oscillator 3b, and supplied to a BPF4.
- the IF signal output from the tuner 3 is supplied to the A / D conversion circuit 5 after being filtered by the BPF 4.
- the A / D conversion circuit 5 samples the IF signal using the clock supplied from the clock generation circuit 6 and digitizes the IF signal.
- the IF signal digitized by the A / D conversion circuit 5 is supplied to a DC cancel circuit 7, and after the DC component is removed by the DC cancel circuit 7, is supplied to a digital quadrature demodulation circuit 8.
- the digital quadrature demodulation circuit 8 quadrature demodulates the digitized IF signal using a two-phase carrier signal having a predetermined carrier frequency, and outputs a baseband OFDM signal.
- the 0 FDM time domain signal output from the digital quadrature demodulation circuit 8 is supplied to a carrier frequency error correction circuit 9.
- this device 1 when digital quadrature demodulation is performed by the digital quadrature demodulation circuit 8, a two-phase signal of one Sin component and Cos component is required as a carrier signal. Therefore, this device 1 generates a two-phase carrier signal to be supplied to the digital quadrature demodulation circuit 8 by setting the frequency of the sampling clock to be supplied to the A / D conversion circuit 5 to be four times the center frequency of the IF signal ⁇ IF. It is possible.
- the data sequence of the 4 f IF clock is down-sampled to 1/4, and the number of effective symbol sampling points after digital quadrature demodulation is defined as the number of subcarriers (Nu).
- the clock of the data sequence after digital quadrature demodulation is set to a frequency that is 1 / subcarrier interval.
- the FFT operation is performed with twice the normal number of sampling points, and another 1/2 down sample may be performed after the FFT operation. .
- the number of sampling points (Nu) of the effective symbol after digital orthogonal demodulation may be set to 2 n times the number of subcarriers (where n is a natural number).
- the clock generation circuit 6 supplies the A / D conversion circuit 5 with a clock having the above-described frequency, and also operates a data series operation clock (A / D conversion circuit 5) after digital quadrature demodulation.
- a clock divided by 1Z4 with respect to the frequency of the clock given to the sub-carrier, for example, a clock having a frequency of one-subcarrier interval) is supplied to each circuit in the device 1.
- the operation clock generated from the clock generation circuit 6 is a free-running clock that is asynchronous with respect to the transmission clock of the received OFDM signal. That is, the operation clock generated from the clock generation circuit 6 is not synchronized in frequency and phase with the transmission clock by PLL or the like, and operates in a free-running state. In this way, the operation clock can be set to the free-running state because the timing synchronization circuit 13 detects a frequency error between the transmission clock of the OFDM signal and the operation clock and feeds the signal based on the frequency error component. This is because the error is removed at a later stage by the forward processing.
- the clock generation circuit 6 is an asynchronous free-running clock as described above, but the present invention can also be applied to a device that variably controls the operating clock frequency by feedback control. It is.
- the baseband OFDM signal output from the digital quadrature demodulation circuit 8 is a so-called time-domain signal before the FFT operation is performed. For this reason, the baseband signal before the FFT operation is hereinafter referred to as an OFDM time domain signal.
- the OFDM time domain signal becomes a complex signal composed of a real axis component (I channel signal) and an imaginary axis component (Q channel signal).
- the carrier frequency error correction circuit 9 corrects the carrier frequency error of the OFDM time domain signal by performing complex multiplication of the carrier frequency error correction signal output from the NC017 and the ⁇ FDM time domain signal after digital orthogonal demodulation. I do.
- the OFDM time-domain signal whose carrier frequency error has been corrected by the carrier frequency error correction circuit 9 is supplied to the FFT operation circuit 10 and the guard correlation / peak detection circuit 12.
- the FFT arithmetic circuit 10 extracts a signal of an effective symbol length from one OFDM symbol, that is, a guard interval from all samples (Ns) of one OFDM symbol. Extract the signal excluding the 5-minute sample number (Ng) samples, and perform FFT operation on the data of the effective symbol sample number (Nu).
- the FFT operation circuit 10 is provided with a start flag (operation start timing of the FFT operation) for specifying the extraction range from the timing synchronization circuit 13, and performs the FFT operation at the timing of the start flag.
- the FFT arithmetic circuit 10 includes a serial / parallel converter 25, a guard interval remover 26, an FFT arithmetic unit 27, and a parallel / serial converter 28. I have.
- the serial / parallel converter 25 starts counting from the start flag supplied from the timing synchronization circuit 13 and cuts out data of the number of samples (Ns) of the OFDM symbol, and the parallel data having one word of Ns is obtained. Is output.
- the guard-in filter 26 removes the first Nu data out of the parallel data of Ns samples in one word, and outputs the Ng data output after the word. Not performed.
- the FFT operation unit 27 performs an FFT operation on the data for the number of valid symbol samples (N u) output from the guard interval remover 26.
- the parallel / serial converter 28 receives data of the number of subcarriers (that is, Nu) from the FFT calculator 27.
- the parallel / serial converter 28 serializes the Nu data and outputs it.
- the FFT operation circuit 10 extracts data of the number of samples for the effective symbol from one OFDM symbol and performs the FFT operation process, thereby modulating each subcarrier in the OFDM symbol. Extract the signal components that are present.
- the signal output from the FFT operation circuit 10 is a so-called frequency domain signal after the FFT. Therefore, the signal after the FFT operation is hereinafter referred to as an OFDM frequency domain signal.
- the OFDM frequency domain signal output from the FFT operation circuit 10 is a complex signal composed of a real axis component (I channel signal) and an imaginary axis component (Q channel signal). It is.
- the OFDM frequency domain signal is supplied to the phase correction circuit 11.
- the phase correction circuit 11 corrects the OFDM frequency domain signal for a phase rotation component caused by a difference between an actual boundary position of the OFDM symbol and a start timing of the FFT operation.
- the phase correction circuit 11 corrects the phase of a shift that occurs with an accuracy shorter than the sampling period. That is, as shown in FIG. 8, the start timing of the FFT operation is 6 It can be controlled only in the operation clock unit of unit 1.
- the symbol boundary position of the OFDM signal actually received does not always coincide with the operation clock. Therefore, no matter how accurate the symbol synchronization control is, an error with an accuracy equal to or less than the operation clock cycle occurs.
- the phase correction circuit 11 corrects such a phase shift with an accuracy shorter than the operation clock cycle.
- the phase correction circuit 11 performs complex multiplication of the OFDM frequency domain signal output from the FFT operation circuit 10 with the phase correction signal (complex signal) supplied from the timing synchronization circuit 13. Perform phase rotation correction.
- the OFDM frequency domain signal having undergone the phase rotation correction is supplied to a wideband carrier error calculation circuit 15, a frame synchronization circuit 18, an equalization circuit 19, and a transmission control information decoding circuit 22.
- the guard correlation / peak detection circuit 12 receives an OFDM time domain signal.
- the guard correlation / peak detection circuit 12 obtains a correlation value between the input OFDM time domain signal and the OFDM time domain signal delayed by the effective symbol.
- the time length for obtaining the correlation is set to the time length of the guard interval.
- a signal indicating this correlation value (hereinafter referred to as a guard signal) is a signal having a peak at the boundary position of the OFDM symbol.
- the guard correlation / peak detection circuit 12 detects the peak position of the guard correlation signal and outputs a value (peak timing value Np) specifying the timing of the peak position.
- the peak timing value Np output from the guard correlation / peak detection circuit 12 is supplied to a timing synchronization circuit 13, and the phase of the correlation value at the peak timing is supplied to a narrow-band carrier error calculation circuit 14.
- the timing synchronization circuit 13 performs, for example, a filtering process on the peak timing value Np output from the guard correlation / peak detection circuit 12 to estimate the boundary position of the OFDM symbol, and estimates the boundary position.
- the calculation start timing for performing the FFT calculation is determined based on.
- the operation start timing is supplied to the FFT operation circuit 10 as a start flag.
- the FFT operation circuit 10 extracts a signal in the FFT operation range from the input OFDM time-domain signal based on the start flag and performs the FFT operation. Further, the timing synchronization circuit 13 calculates a phase rotation amount that occurs due to a time lag between the estimated boundary position of the OFDM symbol and the operation start timing for performing the FFT operation, and calculates the phase rotation amount based on the calculated phase rotation amount.
- a phase correction signal (complex signal) is generated based on the Pay.
- the narrow-band carrier error calculating circuit 14 calculates a narrow-band carrier frequency error component indicating a narrow-band component of the center frequency shift amount during digital orthogonal demodulation based on the phase of the correlation value at the boundary position of the OFDM symbol. Is calculated. Specifically, the narrow-band carrier frequency error component is a deviation amount of the center frequency with an accuracy of ⁇ 1/2 or less of the subcarrier frequency interval.
- the narrow-band carrier frequency error component obtained by the narrow-band carrier error calculating circuit 14 is supplied to an adding circuit 16.
- the wideband carrier error calculation circuit 15 calculates a wideband carrier frequency error component indicating a wideband component of the deviation amount of the center frequency during digital orthogonal demodulation based on the OFDM frequency domain signal output from the phase correction circuit 11. .
- the broadband carrier frequency error component is a deviation amount of the center frequency of the subcarrier frequency interval accuracy.
- the wideband carrier frequency error component obtained by the wideband carrier error calculation circuit 15 is supplied to an addition circuit 16.
- the addition circuit 16 adds the narrowband carrier error component calculated by the narrowband carrier error detection circuit 14 and the wideband carrier error component calculated by the wideband carrier error calculation circuit 15, and outputs the result from the carrier correction circuit 9.
- the deviation of the total center frequency of the calculated baseband OFDM signal is calculated.
- the adder circuit 16 outputs the calculated total deviation amount of the center frequency as a frequency error value.
- the frequency error value output from the adding circuit 16 is supplied to the NCO 17.
- NC017 is a so-called numerically controlled oscillator, and generates a carrier frequency error correction signal that increases or decreases according to the frequency error value output from the adding circuit 16.
- NC ⁇ 17 reduces the oscillation frequency of the carrier frequency error correction signal if the supplied frequency error value is a positive value, and decreases the error correction signal if the supplied carrier frequency error value is a negative value. Is controlled so as to increase the oscillation frequency. By performing such control, NC017 generates a carrier frequency error correction signal that stabilizes the oscillation frequency when the frequency error value becomes zero.
- the frame synchronization circuit 18 detects a synchronization word inserted at a predetermined position in the OFDM transmission frame, and detects a start timing of the OFDM transmission frame.
- the frame synchronization circuit 18 controls the symbol of each OFDM symbol based on the start timing of the OFDM transmission frame.
- the port number is specified and supplied to the equalization circuit 19 and the like.
- the equalization circuit 19 performs a so-called equalization process on the OFDM frequency domain signal.
- the equalization circuit 19 detects a pilot signal called an SP (Scattered Pilots) signal inserted in the OFDM frequency domain signal based on the symbol number supplied from the frame synchronization circuit 18.
- the OFDM frequency domain signal that has been equalized by the equalization circuit 19 is supplied to a demapping circuit 20.
- the demapping circuit 20 performs a de-allocation process (decoding) corresponding to a modulation method (for example, QPSK, 16 QAM or 64 QAM) on the OFDM frequency domain signal (complex signal) on which the equalization processing has been performed. Mapping process) to restore the transmitted data.
- the transmission data output from the demapping circuit 20 is supplied to the transmission path decoding circuit 21.
- the transmission path decoding circuit 21 performs a transmission path decoding process corresponding to the broadcast system on the input transmission data. For example, in the transmission line decoding circuit 21, the time din / rebin processing corresponding to the interleave processing in the time direction, the frequency / dental processing corresponding to the in / night control in the frequency direction, and the error dispersion of the multi-valued symbol are performed. Bit-interleave processing for bit interleaving, depuncturing processing for puncturing processing to reduce transmission bits, Viterbi decoding processing for decoding convolutionally encoded pit strings, and pipe It performs din / leave processing in units, energy despreading processing corresponding to energy spreading processing, error correction processing corresponding to RS coding processing, and the like.
- the transmission data decoded in this way is output as, for example, a transport stream defined by MPEG-2 Systems.
- the transmission control information decoding circuit 22 decodes transmission control information such as TMCC and TPS modulated at a predetermined position of the OFDM transmission frame.
- Ns Nu + Ng. 9
- FIG. 9 shows a block diagram of the guard correlation / peak detection circuit 12.
- FIG. 10 shows a timing chart of each signal in the guard correlation / peak detection circuit 12.
- the guard correlation / peak detection circuit 12 includes a delay circuit 31, a complex conjugate circuit 32, a multiplication circuit 33, a moving sum circuit 34, an amplitude calculation circuit 35, and an angle conversion circuit 36. , A self-running counter 37, a peak detection circuit 38, and an output circuit 39.
- the OFDM time domain signal (FIG. 10 (A)) output from the carrier frequency error correction circuit 9 is supplied to the delay circuit 31 and the multiplication circuit 33.
- the delay circuit 31 is a shift register composed of Nu register groups, and delays the input OFDM time domain signal by an effective symbol time.
- the FDM time domain signal (FIG. 10B) delayed by the effective symbol time by the delay circuit 31 is input to the complex conjugate circuit 32.
- the complex conjugate circuit 32 calculates a complex combination of the OFDM time-domain signal delayed by the effective symbol period, and supplies the complex combination to the multiplication circuit 33.
- the multiplication circuit 33 converts the undelayed OFDM time domain signal (FIG. 10 (A)) and the complex conjugate signal of the OFDM time domain signal (FIG. 10 (B)) delayed by the effective symbol period for each sample. Multiply by The result of the multiplication is input to the moving sum circuit 34.
- the moving sum circuit 34 includes, for example, a shift register composed of Ng register groups and an adder for calculating the sum of the values stored in each register, and is sequentially input for each sample. A moving sum operation is performed for each of the Ng samples on the multiplied result.
- the value output from the moving sum circuit 34 is a guard correlation signal indicating the correlation between the OFDM time domain signal and the OFDM time domain signal delayed by the effective symbol (Nu sample) (Fig. 10 (C )).
- the guard correlation signal output from the moving sum circuit 34 is supplied to an amplitude calculation circuit 35 and an angle conversion circuit 36.
- the amplitude calculation circuit 35 squares the real part and the imaginary part of the guard correlation signal, adds them, and takes the square root of the added result to obtain the amplitude component of the guard correlation signal.
- the amplitude component of the guard correlation signal is supplied to a peak detection circuit 38.
- the angle conversion circuit 36 performs a Tan-1 operation on the real part and the imaginary part of the guard correlation signal to obtain a phase component of the guard correlation signal.
- the phase component of the guard correlation signal is supplied to a peak detection circuit 38.
- the self-running counter 37 is a counter that counts an operation clock. Self-propelled counter 3 The count value N of 7 is incremented by 1 from 0 to Ns-1, and returns to 0 when it exceeds Ns-1 (Fig. 10 (D)). In other words, the self-running counter 37 is a cyclic counter having one cycle with the number of samples (Ns) during the OFDM symbol period. The count value N of the self-running counter 37 is supplied to a peak detection circuit 38.
- the peak detection circuit 38 detects a point where the amplitude value of the guard correlation signal is the highest within one cycle (0 to Ns-l) of the free-running counter 37, and detects the count value at that point. When the count value of the self-running counter 37 shifts to the next cycle, the peak detection circuit 38 detects a new point where the amplitude value of the guard correlation signal is high. The count value detected by the peak detection circuit 38 becomes a peak timing value N indicating the peak time of the guard correlation signal. Further, the peak detection circuit 38 also detects the phase component of the guard correlation signal at the peak time, and outputs the detected phase component to the output circuit 39.
- the output circuit 39 takes in the count value output from the peak detection circuit 38, stores it in an internal register, and can output the count value to the outside. (Fig. 10 (E)).
- the count value stored in the register is output to the subsequent timing synchronization circuit 13 as information (peak timing value Np) indicating the peak time of the guard correlation signal.
- the output circuit 39 captures the phase component output from the peak detection circuit, stores the phase component in the internal register, and stores the phase component in the external register. Set to a state where output is possible for.
- the phase component stored in the register is output to the subsequent narrow-band carrier error calculation circuit 14.
- the self-running counter 37 issues a valid flag which becomes high when the count value N becomes 0 (FIG. 10 (F)). This valid flag indicates the timing of issuing the peak timing value Np and the phase value to the subsequent circuit.
- the timing at which the count value N changes from the maximum value (Ns-1) to 0 and the timing at which the guard correlation signal becomes a peak (boundary timing of the OFDM symbol)
- the cyclic timing of the free-running counter 37 is adjusted so as to be shifted from the OFDM symbol period by about a half cycle.
- the peak timing value Np is adjusted to be about 1/2 of the maximum count value (Ns-1). The reason for such adjustment will be described.
- Peak detection circuit 38 peak detection The period is from the timing when the count value of self-propelled counter 37 becomes 0 to the time when it becomes Ns-1.
- the peak detection circuit 38 outputs the count value of the timing when the amplitude value of the guard correlation signal becomes the maximum during the period as the peak timing value Np.
- the timing at which the cycle of the self-running counter 37 is updated that is, the timing at which the count value becomes 0
- the timing at which the amplitude value of the guard correlation signal becomes maximum are close in time.
- the highly correlated portion that is, the mountain-shaped portion
- originally generated by the guard interpal of the immediately preceding OFDM symbol is included in the peak detection processing in the next OFDM symbol period and is determined. Will be lost.
- the peak value of the guard correlation signal may not always be constant due to various noise errors, but may fluctuate for each symbol.Therefore, the peak value is generated by the guard interval of the previous OFDM symbol.
- the highly correlated part may be determined to be the boundary position of the next OFDM symbol. Therefore, by adjusting the peak timing value Np in advance so as to be about 1/2 of the maximum value of the count value (Ns-1), the peak interval Np is generated by the guard interval of the previous OFDM symbol.
- the highly correlated portion (the mountain-shaped portion) can be excluded from the determination of the next OFDM symbol, and stable peak position detection can be performed.
- the cyclic timing of the count value N may be appropriately adjusted according to the clock frequency error.
- the guard correlation / peak detection circuit 12 has a configuration in which the peak timing value Np is generated for each OFDM symbol period. However, instead of one OFDM symbol period, M (M A natural number.) The configuration may be such that the peak timing value Np is generated at the OFDM symbol period. However, in this case, the valid flag is set to High (1) only once in the M OFDM symbol periods.
- the peak timing value Np output from the guard correlation / peak detection circuit 12 should ideally always be a constant value.
- the peak timing value Np includes noise and fluctuates due to the influence of disturbance generated on the transmission path such as jitter and the effect of a clock frequency error caused by a difference between the clocks of the transmitting device and the receiving device.
- FIG. 11 shows a typical multipath environment.
- Fig. 11 shows an environment in which there are two paths for transmitting radio waves from the transmitting device X to the receiving device 1; a route where direct radio waves reach and a route where radio waves reach after reflecting the high-rise building group Y. .
- the radio wave that arrives directly from the transmitting device X is called the main wave, and the radio wave that reflects from the skyscrapers Y is called the delayed wave.
- FIG. 12 (A) shows the OFDM time-domain signal (no delay) with the main wave and the delayed wave superimposed.
- FIG. 12 (B) shows a signal obtained by delaying the OFDM time-domain signal in a state where the main wave and the delayed wave are superimposed on each other by an effective symbol.
- the guard correlation signal is also a signal obtained by superimposing the correlation value of the main wave and the correlation value of the delayed wave, as shown in FIG. 12 (C).
- the peak timing value N p is The symbol boundary position of the wave and the symbol boundary position of the delayed wave are randomly selected (however, they are not selected at the same time). Therefore, when the peak timing value Np is viewed in the time direction, as shown in FIG. 13, a force value indicating the symbol boundary position of the main wave and a force value indicating the symbol boundary position of the delayed wave are obtained. Will occur randomly, making it difficult to perform accurate symbol synchronization.
- a flat fading environment is an environment in which the power of transmitted radio waves fluctuates periodically.
- Flat fading occurs, for example, when all radio waves arriving at the receiving device 1 are reflected waves.
- FIG. 14 (A) shows the OFDM time domain signal (no delay) in a flat-fed environment.
- FIG. 14 (B) shows a signal obtained by delaying the 0 FDM time domain signal by an effective symbol in a flat-fed environment.
- the guard correlation signal has a correct value when the signal power is high, but the noise is relative when the signal power is low. Become larger.
- FIGS. 14 (D), 14 (E), and 14 (F) the peak timing value N p is determined when the signal power is large.
- the correct sympol boundary position is selected, but the wrong value is selected in the time period when the radio wave power is low. Therefore, when the peak timing value Np is viewed in the time direction, an erroneous count value is randomly generated in a time period when radio wave power is low as shown in FIG. It becomes difficult to perform simple symbol synchronization.
- a frequency selective fading environment is an environment in which a multipath environment and a flat fading environment are combined.
- the frequency selective fading environment occurs when, for example, all radio waves arriving at the receiving device 1 are delayed waves, and the arrival times of these radio waves are divided into a plurality of groups.
- FIG. 16 (A) shows an OFDM time-domain signal (without delay) in a flat fading environment.
- FIG. 16B shows a signal obtained by delaying the ⁇ FDM time-domain signal in the flat fading environment by an effective symbol.
- a time zone in which the power of the main wave is larger than that of the delayed wave and a time zone in which the power of the delayed wave is larger than the power of the main wave appear periodically.
- the guard correlation signal When such a signal is received, as shown in Fig. 16 (C), the guard correlation signal has a peak at the boundary of the main wave symbol during the time period when the power of the main wave is large, and the power of the delayed wave is large. In the time zone, the boundary of the delay wave symbol becomes a peak. Assuming that peak detection is performed on such a guard correlation signal, the peak timing value Np naturally becomes the value of the main signal as shown in FIGS. 16 (D), 16 (E) and 16 (F). The main wave in the time when power is large The boundary position of the symbol is selected, and the boundary position of the symbol of the delayed wave is selected in the time zone where the power of the delayed wave is large. Therefore, when the peak timing value Np is viewed in the time direction, as shown in Fig. 17, the count value is alternately changed at a substantially constant cycle, and accurate symbol synchronization can be performed. It will be difficult.
- the peak frequency error is an error caused by a difference between the frequency of the oscillator of the transmitting device and the frequency of the oscillator of the receiving device.
- the error is caused by a difference in frequency between the transmission clock of the transmitted OFDM signal and the internal clock of the receiving device 1.
- the peak timing value Np output from the guard correlation / peak detection circuit 12 is the value of the self-running counter 37 at the peak timing of the guard correlation signal.
- the self-running counter 37 is a cyclic counter circuit, but the count number in one cycle is set in advance to the sampling number of 1 OFDM symbol.
- the peak timing value Np gradually increases.
- the peak timing value Np gradually decreases.
- the timing synchronization circuit 13 described below eliminates the various disturbances and errors as described above, and performs accurate symbol synchronization.
- FIG. 21 shows an internal configuration diagram of the evening synchronization circuit 13.
- the timing synchronization circuit 13 includes a clock frequency error calculation circuit 41, an initial value phase calculation circuit 42, a symbol boundary calculation circuit 43, a symbol boundary correction circuit 44, and a start flag generation circuit 45. Have.
- the peak timing value Np from the guard correlation / peak detection circuit 12 is input to the timing synchronization circuit 13 at M OFDM symbol periods (M is a natural number).
- M is a natural number.
- the operation of each circuit in the timing synchronization circuit 13 is controlled by the input timing cycle (M symbol cycle) of the peak timing value Np.
- the clock frequency error calculation circuit 41 estimates a clock frequency error based on the peak timing values Np input at M OFDM symbol periods, and inputs the estimated clock frequency error to the symbol boundary calculation circuit 43.
- the initial value phase calculation circuit 42 calculates an initial value of the peak timing value Np based on the peak timing value Np input in the M symbol period. This initial value is input to the symbol boundary calculation circuit 43.
- the symbol boundary calculating circuit 43 performs a filtering process on the peak timing value Np input at the M symbol period, and calculates a symbol boundary position Nx indicating the boundary position of the OFDM symbol.
- the symbol boundary position Nx is a value expressed in the range of 0 to Ns, which is the cycle of the free-running counter 37 in the guard correlation / peak detection circuit 12.
- the symbol boundary position Nx has a value with a precision below the decimal point, while the free-running counter 37 and the peak timing value Np have values with an integer precision.
- the symbol boundary calculating circuit 43 calculates a phase error between the output value (symbol boundary position Nx) and the input value (peak timing value Np), and based on the phase error component, stabilizes the output value (symbol boundary position Nx). Evening ring processing is performed.
- the initial value output from the initial value phase calculation circuit 42 is an initial output value at the start of the filtering process, for example.
- the symbol boundary calculating circuit 43 adds the clock frequency error calculated by the clock frequency error calculating circuit 41 to the phase error component, thereby changing the output value (symbol boundary position Nx) based on the clock frequency error. Has also been corrected. By obtaining the symbol boundary position including the clock frequency error in this way, the symbol boundary position can be specified with higher accuracy.
- the symbol boundary position Nx output from the symbol boundary calculation circuit 43 is input to the symbol boundary correction circuit 44.
- the symbol boundary correction circuit 44 detects an integer component of the symbol boundary position Nx input for each of the M symbols, and calculates a start time for the FFT calculation. The calculated start time is supplied to the start flag generation circuit 45. In addition, the symbol boundary correction circuit 44 detects a component that is smaller than the fraction of the symbol boundary position Nx, and obtains a time lag between the symbol boundary time and the FFT calculation start time with an accuracy equal to or less than an operation clock cycle. Then, the phase rotation amount of the signal component included in each subcarrier after the FFT operation is calculated based on the time shift amount. The calculated phase rotation amount is supplied to the phase correction circuit 11 after being converted into a complex signal.
- the start flag generation circuit 45 generates a start flag for specifying a signal cutout timing for the FFT calculation (that is, an FFT calculation start timing) based on the start time supplied from the symbol boundary correction circuit 44.
- This start flag is generated for each lOFDM symbol.
- the start flag may be generated after a delay of a predetermined margin time from the input symbol boundary position Nx. However, this margin time should not exceed at least the length of the guard interval.
- timing synchronization circuit 13 The detailed configuration of each circuit in the timing synchronization circuit 13 is specifically described below.
- the clock frequency error calculation circuit 41 detects a time change rate (slope amount S) of the peak timing value Np, and calculates a clock frequency error based on the slope amount S. This is because the clock frequency error can be calculated from the slope amount S because the slope amount S has a value proportional to the mouth frequency error. First, the reason will be described.
- the peak timing value Np output from inside the guard correlation / peak detection circuit 12 is the value of the free-running counter 37 at the peak timing of the guard correlation signal.
- the self-running counter 37 is a cyclic counter circuit, but the count of one cycle is previously set to 1 OFDM symbol sample. It is set to the number of pulling (Ns).
- the period of the free-running counter 37 is shorter than the symbol period of the received OFDM signal, that is, the operation clock of the free-running counter 37 is shorter than the transmission clock of the received OFDM signal.
- the peak timing value Np gradually increases.
- the cycle of the free-running counter 37 is longer than the symbol cycle of the received OFDM signal, that is, when the operation clock of the free-running counter 37 is slower than the transmission clock of the received OFDM signal, The peak timing value Np gradually decreases.
- the time rate of change of the peak timing value Np is a value proportional to the clock frequency error which is an error between the transmission clock of the received OFDM signal and the operation clock of the reception side.
- the clock frequency error calculation circuit 41 is a circuit that detects the slope amount S of the peak timing value Np proportional to the clock frequency error in this way.
- the slope amount S of the peak timing value NP can be said to be, in other words, a value obtained by measuring the symbol interval of the received OFDM symbol with the operation clock of the reception side.
- FIG. 22 shows a specific circuit configuration diagram of the clock frequency error calculation circuit 41.
- the clock frequency error calculation circuit 41 has a register 41a for delaying the peak timing value Np by one sample, a subtractor 4lb, and a low-pass filter 41c.
- the clock frequency error calculation circuit 41 receives a peak timing value Np in synchronization with an effective flag set to high (1) for each of M (M is a natural number) OFDM symbols. That is, the peak timing value Np is input from the guard correlation / peak detection circuit 12 at a constant input interval (M symbol period). Register 4 la delays the peak timing value Np by one sample (M symbol periods). The subtractor 4 lb subtracts the peak timing value Np of the previous sample stored in the register 41a from the peak timing value Np input from the guard correlation / peak detection circuit 12 to obtain the peak timing value N Calculate the change amount of P. The mouth-to-pass filter 41c averages the amount of change in the peak timing value Np, and obtains the time change rate (the amount of slope S) of the peak timing value Np.
- Register 4la is a register with an enable function.
- Table 1 shows the operation of the register with the enable function.
- k is an arbitrary timing
- k + 1 indicates a timing one clock after k.
- EN [x] is the value of the enable port at time X (0 or 1)
- D [x] is the value of the register input port at time X
- Q [x] is the time X Is the value of the output port.
- A is an arbitrary value.
- the register with the enable function has the flag asserted in the enable port.
- This circuit holds the value of the input port internally at the timing (set to 1) and outputs the value held internally from the output port.
- Other registers with an enable function described in this specification operate in the same manner as in Table 1.
- the clock frequency error calculation circuit 41 supplies the time change rate (slope amount S) of the peak timing value Np thus obtained to the symbol boundary calculation circuit 43 as a clock frequency error.
- the initial phase calculation circuit 42 calculates an initial value (initial phase) used for the filtering process performed by the symbol boundary calculation circuit 43.
- the initial phase calculation circuit 42 can be composed of, for example, a register 42 a having an enable function as shown in FIG.
- the peak timing value Np is input to the input port D of the register 42a, and the enable flag is input to the enable port EN.
- the initial phase calculation circuit 42 delays the peak timing value Np by one sample (M symbol), and outputs it as it is to the symbol boundary calculation circuit 43 as the initial phase.
- the initial phase calculation circuit 42 may be configured as shown in FIGS. 24 to 26 to improve the accuracy of the initial phase.
- the initial phase calculation circuit 42 shown in Fig. 24 calculates the sum of the output values of the shift register 42b composed of N stages of registers with enable function and the output values of all the registers in the shift register 42b. And a multiplier 42 d for multiplying the output value of the adder 42 c by 1 ZN.
- the peak timing value Np from the guard correlation / peak detection circuit 12 is input to the input port D of the first stage register of the shift register 42b.
- the enable flag EN output from the guard correlation / peak detection circuit 12 is input to the enable port EN of each register.
- the output value of the multiplier 42 d is output as the initial phase. That is, the initial phase calculation circuit 42 shown in FIG.
- the initial phase calculation circuit 42 shown in Fig. 25 has a register 42e with an enable function to hold the output value for one sample, and a peak timing value N input from the guard correlation / peak detection circuit 12 A subtractor 4 2 f that subtracts the output value of the register 4 2 e from p, a multiplier 4 2 g that multiplies the output value of the subtractor 4 2 f by a predetermined gain, and an output value of the multiplier 4 2 g And an adder 42h for adding the output value of the register 42e.
- the initial phase calculation circuit 42 shown in FIG. 25 Is input with the output value of the adder 42h, and the enable port EN is input with the valid flag from the guard correlation / peak detection circuit 12.
- the output value of the adder 42h is output as the initial phase.
- the initial phase calculation circuit 42 shown in FIG. 25 performs an average by performing one-pass filtering on the peak timing value N p by the IIR type filter, and outputs the average value as the initial phase. I have.
- the initial phase calculation circuit 42 shown in FIG. 26 has a shift register 42 i composed of N stages of registers with an enable function and one of the stored values of all registers in the shift register 42 i. And a median value selector 4 2 j for selecting the median value. Shift Regist Evening 4 2 1st stage Regis Evening input port! ), The peak timing value N p is input from the guard correlation / peak detection circuit 12. The enable flag output from the guard correlation / peak detection circuit 12 is input to the enable port EN of each register. The median value selector 42j receives N input values from each register of the shift register 42i, and outputs the N / 2th value when the input values are arranged in descending order. Therefore, in the initial phase calculating circuit 42 shown in FIG.
- the output value of the median value selector 42 j is output as the initial phase. That is, the initial phase calculation circuit 42 calculates the median value of the peak timing value Np for every N samples by the so-called median value selection filter, and outputs the calculated median value as the initial phase. Therefore, in the initial phase calculation circuit 42, for example, one peak timing having an input value When the value Np has an extremely large error, it is possible to effectively suppress the fluctuation due to the large error.
- the symbol boundary calculation circuit 43 receives the peak timing value Np from the guard correlation / peak detection circuit 12, performs loop filtering using a so-called DLL (Delay Locked Loop) based on the peak timing value Np, and obtains the symbol boundary position N This is a circuit for estimating x.
- DLL Delay Locked Loop
- the peak timing value Np is a value indicating the peak position of the guard correlation signal detected by the guard correlation / peak detection circuit 12.
- the symbol position Nx is a value indicating the boundary position of the OFDM symbol in the received OFDM signal.
- the peak evening value N p and the symbol boundary position NX take values within the range of the count value of the free-running counter 37 in the guard correlation / peak detection circuit 12. That is, the peak timing value Np and the symbol boundary position Nx take values ranging from 0 to Ns.
- the peak timing value Np is an integer precision value in the range of 0 to Ns since the count value of the self-running counter 37 is output as it is.
- the symbol boundary position Nx is a value including the precision below the decimal point in the range of 0 to Ns.
- the free-running counter 37 in the guard correlation / peak detection circuit 12 counts the operation clock of the OFDM receiver 1 and runs free-running, the count value is equal to the reference time of the OFDM receiver 1. Can be considered.
- the count of one cycle of the free-running counter 37 is set to the number of samples Ns in one symbol of the OFDM signal (the number obtained by adding the number of valid symbol samples Nu and the number of samples of the guard interval Ng). Have been. Therefore, the peak timing value Np and the symbol boundary position Nx represent the time synchronized with the self-running counter 37. In other words, it represents the phase of the OFDM signal with respect to the symbol period.
- the OFDM receiver 1 generates the peak timing value Np and the symbol position Nx using the value within the range of the number Ns of samples of one symbol of the OFDM signal as described above. Control can be performed easily at the symbol boundary position Has become.
- FIG. 27 shows a circuit configuration diagram of the symbol boundary calculation circuit 43.
- the symbol boundary calculation circuit 43 includes a phase comparison circuit 51, a limiter 52, an asymmetric gain circuit 53, a one-pass filter 54, and a clock error correction circuit 55. , A phase generation circuit 56, a synchronization management circuit 57, a first register 58, a second register 59, and a third register 60.
- the peak timing value Np and the valid flag are input to the symbol boundary calculation circuit 43.
- the valid flag is set to High (1) only once for each M symbol (M is a natural number) in synchronization with the patrol timing of the self-propelled counter 37.
- the symbol boundary calculating circuit 43 calculates the symbol boundary position NX at each timing when the effective flag becomes High.
- FIG. 28 shows a circuit configuration diagram of the phase comparison circuit 51.
- the phase comparison circuit 51 includes a subtractor 5 la and a modulo arithmetic unit 51 b.
- the phase comparison circuit 51 receives the peak timing value N p from the guard correlation / peak detection circuit 12 and the feedback value of the symbol boundary position N x, which is the output value of the symbol boundary calculation circuit 43. You.
- the symbol boundary position Nx input to the phase comparison circuit 51 is one sample before (ie, one time before) the input timing of the peak timing value Np output from the guard correlation / peak detection circuit 12. This is the value output from the symbol boundary calculation circuit 43 at the timing when the valid flag becomes High.
- the symbol boundary position Nx input to the phase comparison circuit 51 is input via the first register 58.
- the subtractor 51a subtracts the symbol boundary position Nx from the peak timing value Np.
- the modulo arithmetic unit 51b performs a remainder operation of Ns (the number of samples of one symbol) on the output value of the subtractor 51a. That is, the modulo arithmetic unit 5 lb divides the output value of the subtractor 5 la by N s (the number of samples of one symbol), and outputs the remainder.
- phase comparison circuit 51 when the count value of the free-running counter 37 is regarded as a symbol cycle, the currently estimated symbol boundary phase and the current symbol symbol are used. A phase difference ⁇ S from the peak phase of the signal is calculated. That is, when the count value of the self-running counter 37 is regarded as the reference time, the time difference between the currently estimated sympol boundary time and the current peak time of the guard correlation signal is calculated.
- the phase difference calculated by the phase comparison circuit 51 is supplied to the limiter 52.
- FIG. 29 shows a circuit configuration diagram of the limiter 52.
- the phase difference ⁇ S which is the output value of the phase comparison circuit 51, is input to the limiter 52.
- the limiter 52 includes a first comparator 52a that compares the upper limit value TH1 with the phase difference ⁇ 0, a second comparator 52b that compares the lower limit value TH2 with the phase difference ⁇ 0,
- the selector 52c selects one of the phase difference ⁇ , the upper limit value TH1 and the lower limit value ⁇ 2.
- the relationship between the upper limit value TH1 and the lower limit value ⁇ 2 is ⁇ 1> ⁇ 2.
- the first comparator 52a outputs Low (0) when the phase difference is smaller than the upper limit value TH1, and outputs High (1) when the phase difference is equal to or larger than the upper limit value TH1.
- the second comparator 52b outputs Low (0) if the phase difference is larger than the lower limit value TH2, and outputs High (1) if the phase difference ⁇ S is equal to or smaller than the lower limit value TH2.
- the selector 52c determines the phase difference output from the phase comparator 51. ⁇ 0 is output as it is.
- the selector 52c outputs the upper limit value TH1 if the output of the first comparator 52a is High (1), and outputs the upper limit value TH1 if the output of the second comparator 52b is High (1).
- the output value is clipped at the upper limit value TH1, and if the input phase difference ⁇ is less than the lower limit value, the output value is clipped at the lower limit value TH2.
- the value of the phase difference ⁇ S fluctuates in the plus and minus directions around 0, so TH1 ⁇ 0 and TH2 ⁇ 0 are set.
- the symbol boundary calculating circuit 43 by providing such a limiter 52, for example, a large impulse noise generated in a fading environment can be removed, and the synchronization holding characteristic can be improved.
- the phase difference ⁇ 0 whose level is limited by the limiter 52 is supplied to the asymmetric gain circuit 53.
- FIG. 30 shows a circuit configuration diagram of the asymmetric gain circuit 53.
- the asymmetric gain circuit 53 includes a comparator 53 a that determines the polarity of the phase difference ⁇ 0, a first multiplier 53 b that multiplies the phase difference by a first gain G a, and a phase difference ⁇ S From a second multiplier 53c that multiplies the second gain Gb, and a selector 53d that selects the output of either the first multiplier 53b or the second multiplier 53c. It is configured.
- the relationship between the first gain G a and the second gain G b is G a> G b.
- the comparator 53a compares the phase difference ⁇ S with 0, and if the phase difference ⁇ ⁇ ⁇ is smaller than 0, Low
- the selector 53d outputs the output value of the first multiplier 53b if the output of the comparator 53a is Low (0).
- the asymmetric gain circuit 53 determines whether the peak timing value Np is earlier or later than the symbol boundary position NX. If the peak timing value Np is earlier than the symbol boundary position NX, the gain (Gb ), And if the peak timing value Np is later than the symbol boundary position Nx, multiply by a larger gain (G a). That is, when a plurality of peak values are detected by multipath or the like, the asymmetric gain circuit 53 is provided with a phase difference so as to easily synchronize a signal (main wave) earlier in time. The gain by which is multiplied is changed.
- phase difference ⁇ 0 multiplied by the gain by the asymmetric gain circuit 53 is supplied to the low-pass filter 54.
- FIG. 31 shows a circuit configuration diagram of the low-pass filter 54.
- the low-pass filter 54 receives the phase difference ⁇ 0 multiplied by the gain by the asymmetric gain circuit 53 and the valid flag output from the guard correlation / peak detection circuit 12. Mouthful
- the pass filter 54 includes a register 54 a having an enable function, a subtracter 54 b, a multiplier 54 c, and an adder 54 d.
- an enable flag is input to the enable port EN, and the output value (average phase difference Ave A 0) of the corresponding single-pass filter 54 is input to the input port D.
- the subtractor 5 4 b calculates the value of the register 5 from the phase difference ⁇ ⁇ output from the asymmetric gain circuit 53.
- the subtractor 54 b outputs the output value (average phase difference Ave) of the corresponding low-pass filter 54 one sample before (the timing when the valid flag became High the previous time) from the input phase difference ⁇ ⁇ .
- a 0) is subtracted to calculate a residual of the phase difference ⁇ .
- the multiplier 54c multiplies the residual of the phase difference ⁇ 0 output from the subtractor 54b by a predetermined coefficient K.
- the adder 54d adds the residual multiplied by the predetermined coefficient K and the output value of the register 54a.
- the output value of the adder 54d is the output value of the low-pass filter 54 (average phase difference ⁇ ).
- the low-pass filter 54 is a circuit that averages the input phase difference ⁇ using an IIR type single-pass filter and calculates the average phase difference Ave ⁇ .
- the average phase difference Ave ⁇ S calculated by the single-pass filter 54 is a clock error correction circuit.
- FIG. 32 shows a circuit configuration of the clock error correction circuit 55 and a synchronization management circuit 57 as a control circuit thereof.
- the average phase difference Ave 00 which is the output value of the one-pass filter 54, and the valid flag output from the guard correlation / peak detection circuit 12 are input.
- the clock error correction circuit 55 includes a multiplier 55a, a register 55b, a first adder 55c, and a second adder 55d.
- the multiplier 55a multiplies the average phase difference Ave ⁇ output from the low-pass filter 54 by a predetermined coefficient K1.
- the output value of the multiplier 55a represents a residual component obtained when the clock frequency error for the specific symbol currently being processed is subtracted from the estimated clock frequency error.
- the residual component of the clock frequency error can be calculated by, for example, setting the coefficient K 1 to be the reciprocal of the number of samplings for n symbol (n is the interval of the symbol in which the valid flag occurs), that is, 1 / (n XN s) Can be calculated.
- Register 55b stores the currently estimated clock frequency error.
- the first adder 55c adds the currently estimated clock frequency error stored in the register 55b and the residual component output from the multiplier 55a to generate a new clock. Calculate the frequency error.
- the second adder 55 d adds the clock frequency error output from the first adder 55 c to the average phase difference Ave ⁇ output from the oral pallet filter 54.
- the average phase difference Ave ⁇ ⁇ to which the peak frequency error has been added is supplied to the phase generation circuit 56.
- the clock error correction circuit 55 corrects the clock frequency error for the average phase difference Ave ⁇ ⁇ by adding the clock frequency error to the average phase difference Ave AS. For this reason, the symbol boundary calculation circuit 43 can perform more accurate symbol synchronization processing.
- the currently estimated clock frequency error is stored in the register 55b.
- One of the two estimated values is selected and stored.
- One is an estimated value output from the first adder 55c, and the other is an estimated value output from the external clock frequency error calculation circuit 41.
- the click frequency error can be calculated by cumulatively adding the residual components. That is, the output of the multiplier 55a is cumulatively added, and when the value is stabilized, it becomes an estimated value of the clock frequency error.
- the clock frequency error can also be calculated from the slope value of the peak timing value N as described above.
- the mouth frequency error calculating circuit 41 outputs the mouth frequency error calculated from the slope value of the peak timing value Np.
- the above two values can be used for the clock frequency error to be added to the average phase difference Ave A 0, but the clock frequency error output from the clock frequency error calculation circuit 41 accumulates the residual error. Since the addition is not required, the response is fast, and since only the clock frequency error can be calculated by another path, the value can be accurately calculated without being affected by the phase error.
- the clock error correction circuit 55 determines the stable state of the output value of the clock frequency error calculation circuit 41, and in the case of the stable state, outputs the output value of the clock frequency error calculation circuit 41 to the register 5 If the output value is not stable (unstable state), the output value of the first adder 55 c is fed back and input to the register 55 b. I am trying to do it.
- the state management of the stable state and the unstable state is performed by the synchronization management circuit 57.
- the synchronization management circuit 57 manages the stable state of the output value of the clock frequency error calculation circuit 41 using a state machine.
- the state machine of the synchronization management circuit 57 first makes a transition to an unstable state at the start of operation. In the unstable state, if the output value of the clock frequency error calculation circuit 41 is within a certain range continuously for a predetermined number of times, the state is shifted to the stable state. At this time, the state machine holds the output value at the time of transition to the stable state as the current estimated value.
- the synchronization management circuit 57 sets the first load flag to High (1) when the state machine is in a stable state, and sets the first load flag to Low (0) when the state machine is in an unstable state. .
- Switching of the path input to the register 55b is performed by setting the register 55b as a register having a load enable function.
- Table 2 below shows the operation of the register with load enable function.
- k is an arbitrary timing
- k + 1 indicates a timing one clock after k.
- EN [x] is the value of the enable port at time X (0 or 1)
- LEN [x] is the value of the load enable port at time X (0 or 1)
- D [x] is the time.
- the input port value of the register at X, LD [x] is the value of the load port at register X at time X
- 0] is the value of the output port at time.
- a and B are arbitrary values.
- the register with the load enable function holds the value of the input port D or the load port LD at the timing when the signal is asserted (set to 1) at the enable port, and holds the value internally.
- This circuit outputs the value from output port Q. Whether the value of the input port D or the input port LD is stored depends on whether the load enable port LEN is High (1). Or Low (0).
- the other registers with a bit enable function described in this specification operate in the same manner as in Table 2.
- an enable flag is input to the enable port EN
- the output value of the first adder 55c is input to the input port D
- the The first load flag output from the synchronization management circuit 57 is input to the enable port LEN
- the clock frequency error from the clock frequency error calculation circuit 41 is input to the load terminal LD.
- the register 55 b stores the output value of the clock frequency error calculation circuit 41 It takes in internally, and if it is determined that it is in an unstable state, takes in the output value of the first adder 55c.
- FIG. 33 shows a circuit configuration of the phase generation circuit 56 and a synchronization management circuit 57 as a control circuit thereof.
- the phase generation circuit 56 outputs the average phase difference Ave A 0 after the clock frequency error component, which is the output value of the clock error correction circuit 55, and the guard correlation / peak detection circuit 12. Valid flag is input. Further, the initial phase, which is the output value of the initial phase calculation circuit 42, and the second load flag from the synchronization management circuit 57 are also input to the phase generation circuit 56.
- the phase generation circuit 56 includes an adder 56a and a register 56b.
- the current estimated phase is stored in the register 56b.
- the average phase difference Ave ⁇ output from the clock error correction circuit 55 and the current estimated phase stored in the register 56 b are input to the adder 56 a.
- the adder 56a adds the average phase difference ⁇ and the current estimated phase, and outputs a symbol boundary position Nx.
- Such a phase generation circuit 56 calculates the symbol boundary position Nx by adding the currently estimated phase to the average phase difference Ave AS.
- the phase generation circuit 56 By adding the error component of the phase calculated on the path from the phase comparison circuit 51 to the clock error correction circuit 55 to the currently estimated phase, the output phase (symbol which indicates the final symbol boundary position) Generate the boundary position N x). Since this output phase (symbol boundary position Nx) represents the phase of the cycle of the count value (0 to Ns) generated from the free-running counter 37, the output phase after the calculation is calculated. If the value exceeds N s or falls below 0, the value after performing modulo operation in the count cycle (N s) of the free-running counter 37 is output.
- the current estimated phase is stored in the register 56b, and one of the two estimated phases is selected and stored.
- One is an estimated value output from the adder 56a, and the other is an estimated value output from the external initial phase calculation circuit 42.
- the current estimated phase can be calculated by cumulatively adding the phase residual. That is, the output of the adder 56a is cumulatively added, and when the value is stabilized, the current estimated phase is obtained.
- the current estimated phase may be the peak timing value Np itself or a value obtained by filtering the peak timing value Np.
- the above two values can be used for the current estimated phase.However, the initial phase output from the initial phase calculation circuit 42 is not obtained by cumulatively adding the phase error. Fast response.
- the phase generation circuit 56 determines the stable state of the output value of the initial phase calculation circuit 42, and in the case of the stable state, stores the output value of the initial phase calculation circuit 42 in the register 56b.
- the output value of the adder 56a is fed back and stored in the register 56b.
- the state management of the stable state and the unstable state is performed by the synchronization management circuit 57.
- the synchronization management circuit 57 manages the state of the output value of the initial phase calculation circuit 42 using a state machine.
- the state machine of the synchronization management circuit 57 transitions to an unstable state at the start of operation. In the unstable state, if the output value of the initial phase calculation circuit 42 is within a certain range continuously for a predetermined number of times, the state is changed to the stable state. At this time, the state machine holds the output value at the time of transition to the stable state as the current estimated value.
- the synchronization management circuit 57 If the machine is in a stable state, the second load flag is set to High (1), and if the machine is in an unstable state, the second load flag is set to Low (0).
- the switching of the path input to the register 56 b is performed by setting the register 56 b as a register having a load enable function.
- the enable flag is input to the enable port EN, the output value of the adder 56 a is input to the input port D, and the load enable port LEN is input to the load enable port LEN.
- the second load flag output from the synchronization management circuit 57 is input, and the initial phase is input from the initial phase calculation circuit 42 to the load terminal LD.
- the synchronization management circuit 57 determines that the output value of the initial phase calculation circuit 42 is in a stable state, the register 56b takes in the output value of the initial phase calculation circuit 42, If it is determined that the state is unstable, the output value of the adder 56a is taken in.
- phase generation circuit 56 when calculating the symbol boundary position, it is possible to perform correction using the current estimated phase calculated by another path. Therefore, it is possible to calculate the symbol boundary faster and more accurately.
- the symbol boundary position Nx output from the phase generation circuit 56 is supplied to the first register 58 and the second register 59.
- the first register 58 and the second register 59 of the symbol boundary calculation circuit 43 are registers having an enable function.
- the enable flag is input to the enable port EN, and the output value (symbol boundary position Nx) of the phase generation circuit 56 is input to the input port D.
- the output port Q of the first register 58 is connected to the phase comparison circuit 51. Therefore, the first register 58 delays the symbol boundary position Nx by one sample (one valid symbol) and supplies the delayed signal to the phase comparison circuit 51.
- the enable flag is input to the enable port EN, and the output value (symbol boundary position Nx) of the phase generation circuit 56 is input to the input port!).
- the output port Q of the second register 59 is connected to the symbol boundary correction circuit 44. Therefore, the second register 59 delays the symbol boundary position Nx by one sample (one valid symbol). The signal is supplied to the symbol boundary correction circuit 44.
- the third register 60 is a normal register for reflecting the signal input to the input port]) to the output port Q with a delay of one clock.
- the input port m of the third register 60 receives the valid flag output from the guard correlation / peak detection circuit 12, and the output port Q is connected to the sympol boundary correction circuit 44. Therefore, the third register 60 supplies the valid flag to the symbol boundary correction circuit 44 in synchronization with the timing of the symbol boundary position NX.
- FIG. 34 shows a block diagram of the symbol boundary correction circuit 44.
- the symbol boundary position NX is input from the symbol boundary calculation circuit 43 to the symbol boundary correction circuit 44.
- the symbol boundary position Nx is a value within the count period (0 to Ns) of the free-running counter 37 in the guard correlation / peak detection circuit 12. That is, the symbol boundary position Nx is a value representing the symbol boundary position of the OFDM signal in phase with respect to the cycle of the self-running counter 37. In other words, it is a value represented by the reference time when the self-running counter 37 considers that the reference time is generated.
- the filtering of the symbol boundary position Nx is performed by the above-described symbol boundary calculating circuit 43, so that the accuracy is expressed to the cycle of the operation clock of the self-running counter 37 or less. That is, the symbol boundary position Nx is a value including the precision after the decimal point in the range of 0 to Ns.
- the symbol boundary correction circuit 44 re-expresses such a symbol boundary position N x with integer precision (that is, operation clock cycle precision), and calculates a symbol boundary position with operation clock precision. Simultaneously, based on the value of the decimal precision of the symbol boundary position Nx, the symbol boundary correction circuit 44 generates a phase error amount indicating an error of the precision equal to or less than the operation clock cycle between the cut-out timing of the FFT and the boundary timing of the symbol. Is calculated, and a phase correction signal to be supplied to the phase correction circuit 11 is generated based on the phase error amount / 3/3.
- the symbol boundary correction circuit 44 includes an integer rounding circuit 44a, a subtractor 44b, a phase correction amount calculation circuit 44, and a complex conversion circuit 44d. ing.
- the symbol rounding position Nx calculated from the symbol boundary calculating circuit 43 is input to the integer rounding circuit 44a.
- the integer rounding circuit 44a performs an operation of rounding the input symbol boundary position Nx to a value of the operation clock precision. That is, round to an integer value in the range 0 to Ns.
- the integer rounding circuit 44a performs an operation of rounding down the value after the decimal point of the symbol boundary position Nx, an operation of rounding up the value after the decimal point of the symbol boundary position Nx, or an operation of rounding the value after the decimal point of the symbol boundary position Nx. Performs an integer rounding operation such as a rounding operation.
- the symbol rounded position Nx after the integer rounding is supplied to the subtractor 44b. Further, the symbol rounded position Nx rounded by the integer is also supplied to the start flag generation circuit 45 as symbol start information.
- the subtractor 44b calculates the symbol boundary position Nx (output from the integer rounding circuit 44a) from the symbol boundary position Nx output from the symbol boundary calculation circuit 43 (symbol boundary position Nx expressed to the precision after the decimal point). Subtract integer precision symbol boundary position Nx).
- the output value of the subtractor 44b is an error having an accuracy equal to or less than the operation clock cycle between the cutout timing of the FFT and the boundary timing of the symbol, that is, a phase error amount i3 m .
- the phase error amount i3 m output from the subtractor 44b is supplied to the phase correction amount calculation circuit 44c.
- the phase correction amount calculating circuit 44 c with the phase error amount i3 m, Sabukiya rear number n of each subcarrier is input.
- the subcarrier number is input, for example, from the frame synchronization circuit 18 or the like.
- the phase correction amount calculation circuit 44c calculates a correction amount 0 clk (n) for each subcarrier from the phase error amount / 3 m based on the following equation.
- n indicates the subcarrier number
- N u denotes the number of samples of the effective Shinporu (i.e., the number of subcarriers).
- the subcarrier number of the subcarrier located at the center frequency of the OFDM signal is set to 0.
- subcarriers assigned to frequencies lower than the center frequency are assigned subcarrier numbers from 1 to 512, and subcarriers assigned to frequencies higher than the center frequency are assigned 1 to 511 subcarriers.
- a subcarrier number is assigned.
- the reason that the correction amount differs for each subcarrier is that the phase error amount / 3 m This is because the phase rotation amount generated by the delay time is different for each frequency because it is represented by the delay time between the timing of the boundary between the timing and the symbol.
- the phase correction amount calculation circuit 44c obtains the phase correction amount S clk (11), and supplies the obtained phase correction amount S clk (n) to the complex conversion circuit 44d .
- the complex conversion circuit 44 takes a sine and a cosine for the supplied phase correction amount S clk (n) and converts it into a complex signal.
- the complex conversion circuit 44 d calculates the complex correction phase correction amount.
- phase complementing circuit 11 (cos (0 clk (n)), si ⁇ ( ⁇ clk ( ⁇ ))) is supplied to the phase complementing circuit 11 as a phase correction signal.
- the phase correction circuit 11 supplied with such a phase correction signal converts the data corresponding to each subcarrier of the FF ⁇ OFD ⁇ frequency domain signal output from the arithmetic circuit 10 into a complex conversion circuit 44 d phase correction signal output from the (cos (0 clk (n) ), sin (0 C lk (n))) to be complex multiplication for correcting the phase error.
- the phase correction circuit 11 performs the following matrix operation.
- I in (n) and Q in (n) are the operation results of the subcarrier number n output from the FFT operation circuit 10, where I in (n) is a real component and Q in (n) is The imaginary component is shown. Also I. ut (n) and Q out (n) are the phase correction results of the subcarrier number n output from the phase correction circuit 11; ut (n) is the real component, Q. ut (n) indicates the imaginary component.
- the simple boundary correction circuit 44 can correct an error accurately with a very simple circuit configuration. Further, since the symbol boundary correction circuit 44 calculates the error amount using the guard correlation peak signal before the FFT calculation, the symbol boundary correction circuit 44 synchronizes much faster than performing correction using feedback using a pilot signal, for example. It becomes possible to pull in.
- the start flag generation circuit 45 receives the symbol information (Symbol boundary position Nx after integer rounding) input from the symbol boundary correction circuit 44 for each M symbol, and outputs a signal for FFT operation. (That is, FFT calculation start ) Is generated. A start flag is generated for each OFDM symbol.
- the start flag generation circuit 45 includes a counter 45a, a register 45b, and a comparator 45c.
- the counter 45 a is a counter of the same cycle that operates in synchronization with the free-running counter 37 in the guard correlation / peak detection circuit 12. That is, the counter 45a is a counter that counts a value from 0 to Ns. Further, the phase of the counter 45 a is delayed from the count value of the self-running counter 37 by the delay time in the above-described symbol boundary calculation circuit 43.
- the register 45b stores the symbol start information (the integer rounded symbol boundary position Nx) from the symbol boundary correction circuit 44 every time the valid flag is asserted (set to 1).
- the comparator 45c compares the count value generated by the counter 45a with the symbol start information stored in the register 45b, and generates a start flag that becomes High (1) at the same timing. I do.
- the start flag generated from the comparator 45c is supplied to the FFT operation circuit 10.
- the FFT calculation circuit 10 cuts out Nu data for performing the FFT calculation by parallelizing the input serial data sequence at the timing when the start flag becomes High (1).
- the start flag generation circuit 45 synchronizes with the serial data sequence input to the FFT operation circuit 10 from the timing indicated by the symbol boundary position Nx calculated by the symbol boundary calculation circuit 43. It is converted to a start flag and supplied to the FFT operation circuit 10.
- the counter 45a is provided inside the start flag generation circuit 45, but a value obtained by delay-adjusting the count value of the free-running counter 37 may be supplied to the comparator 45c. .
- the OFDM receiver 1 according to the first embodiment of the present invention is provided with the symbol boundary calculation circuit 43 having a so-called DLL circuit configuration. Therefore, in the OFDM receiving apparatus 1 of the first embodiment, an accurate sympol boundary position can be estimated based on the sympol boundary position calculated by using the correlation between guardinterpals.
- the limiter 52 for limiting the level of the phase difference ⁇ 0, which is the residual component of the DLL, within a predetermined range (TH1> TH2) is provided in the symbol boundary calculating circuit 43. Therefore, in the OFDM receiving apparatus 1 of the first embodiment, for example, large impulse noise generated in a fading environment can be removed, and the synchronization holding characteristic can be improved.
- an asymmetric gain circuit 53 for multiplying the phase difference ⁇ S, which is the residual component of the DLL, is provided in the symbol boundary calculation circuit 43.
- the asymmetric gain circuit 53 determines whether the symbol boundary position (peak timing value Np) input to the DLL is earlier or later than the symbol boundary position (symbol boundary position Nx) estimated by the DLL. If the value Np is earlier than the symbol boundary position NX, multiply by a smaller gain, and if the peak timing value Np is later than the symbol boundary position NX, multiply by a larger gain. Therefore, in the OFDM receiver 1 according to the first embodiment, when a plurality of peak values are detected by multipath or the like, the OFDM receiver 1 more strongly follows a signal (main wave) that is earlier in time. be able to.
- a clock error correction circuit 55 for adding a clock frequency error amount to the phase difference ⁇ 0 which is a residual component of the DLL is provided in the symbol boundary calculation circuit 43. Therefore, the OFDM receiver 1 of the first embodiment can more accurately estimate the symbol boundary position. Further, as the clock frequency error to be added to the phase difference ⁇ S, a clock frequency error calculated from the phase difference ⁇ 0 and a clock frequency error calculated from the peak timing value Np can be switched as appropriate. In the ⁇ FDM receiving apparatus 1 of the first embodiment, the synchronization pull-in time can be reduced by adding the clock frequency error converted from the peak timing value Np.
- the symbol boundary calculation circuit 43 stores the currently estimated symbol boundary position.
- the phase generation circuit 56 as the currently estimated symbol boundary position, the symbol boundary position generated by cumulatively adding the residual components and the initial position calculated from the peak timing value Np are appropriately switched. I can do it.
- the synchronization pull-in time is obtained by adding the initial position converted from the peak timing value Np to the phase difference ⁇ ⁇ as the currently estimated symbol boundary position. Can be shortened.
- the OFDM receiving apparatus is a modification of the symbol boundary calculating circuit 43 of the OFDM receiving apparatus 1 according to the first embodiment, and the other is the first embodiment. Is the same as Therefore, in the OFDM receiver according to the second embodiment of the present invention, only the symbol boundary calculation circuit will be described, and the same components as those in the first embodiment will be denoted by the same reference numerals in the drawings. The detailed description is omitted.
- FIG. 35 shows a block diagram of a symbol boundary calculating circuit 65 in the OFDM receiving apparatus according to the second embodiment.
- the symbol boundary calculation circuit 65 includes a phase comparison circuit 51, a limiter 52, a gain circuit 66, an asymmetric low-pass filter 67, a clock error correction circuit 55, and a phase It includes a generation circuit 56, a synchronization management circuit 57, a first register 58, a second register 59, and a third register 60.
- FIG. 36 shows a circuit diagram of the gain circuit 66 and the asymmetric single-pass filter 67.
- the phase difference ⁇ S after the level restriction which is the output value of the limiter 52, is input.
- the gain circuit 66 multiplies the input phase difference ⁇ by a predetermined gain G.
- the phase difference ⁇ S multiplied by the predetermined gain G is supplied to the asymmetric low-pass filter 67.
- phase difference ⁇ 0 multiplied by the gain by the gain circuit 66 and the valid flag output from the guard correlation / peak detection circuit 12 are input to the asymmetric low-pass filter 67.
- the asymmetric low-pass filter 67 includes a register 67a having an enable function, a comparator 67b, a subtractor 67c, a first multiplier 67d, and a second multiplier 67. e and selector 6 7 f and an adder 67 g.
- the enable flag is input to the enable port EN, and the output value (average phase difference AveAS) of the asymmetric low-pass filter 67 is input to the input port D.
- Comparator 67b compares phase difference ⁇ S with 0, outputs Low (0) if phase difference ⁇ ⁇ is smaller than 0, and outputs High (1) if phase difference is 0 or more. Output.
- the subtracter 67c subtracts the output value of the register 67a from the phase difference ⁇ S output from the gain circuit 66. That is, the subtractor 67c calculates the output value (average) of the asymmetric mouth-to-pass filter 67 one sample before (the timing when the valid flag became High the previous time) from the input phase difference ⁇ S.
- the residual of the phase difference ⁇ ⁇ is calculated by subtracting the phase difference ⁇ 0).
- the first multiplier 67d multiplies the residual of the phase difference ⁇ 0 output from the subtractor 67c by a first coefficient Ka.
- the second multiplier 67e multiplies the residual of the phase difference ⁇ 0 output from the subtractor 67c by a second coefficient Kb.
- the relationship between the first coefficient Ka and the second coefficient Kb is Ka> Kb. If the output of the comparator 67 b is Low (0), the selector 67 f outputs the output value of the first multiplier 67 b (the residual of the phase difference ⁇ 0 is multiplied by the first coefficient Ka Value), and if the output of the comparator 67 b is High (1), the output value of the second multiplier 53 c (the second coefficient Kb is added to the residual of the phase difference ⁇ 0) (Multiplied value) and output.
- the adder 67g adds the residual multiplied by the first coefficient Ka or the second coefficient Kb and the output value of the register 67a.
- the output value of the adder 67 g is the output value (average phase difference AveA0) of the asymmetric mouth-to-pass filter 67.
- the average phase difference Ave ⁇ calculated by the asymmetric low-pass filter 67 is supplied to the clock error correction circuit 55.
- the asymmetric low-pass filter 67 is a circuit that averages the input phase difference ⁇ and calculates the average phase difference AveAS by the IIR type filter. Further, the asymmetric mouth-pass filter 67 determines whether the peak timing value Np is earlier or later than the symbol boundary position Nx, and sets a higher pass band if the peak timing value Np is earlier than the symbol boundary position NX. If the peak evening value Np is later than the symbol boundary position NX, the passband is set lower. In other words, the asymmetric low-pass filter 67 When multiple peak values are detected due to noise or the like, the passband is switched so that the response characteristics for the earlier signal (main wave) are faster.
- An OFDM receiver according to the third embodiment of the present invention is a modification of the guard correlation / peak detection circuit 12 and the symbol boundary calculation circuit 43 of the OFDM receiver 1 according to the first embodiment.
- the rest is the same as the first embodiment. Therefore, in the FDM receiving apparatus according to the third embodiment of the present invention, only the guard correlation / peak detecting circuit and the symbol boundary calculating circuit will be described, and furthermore, the same components as those in the first embodiment will be described. Are given the same reference numerals in the drawings, and detailed description thereof is omitted.
- FIG. 37 shows a block diagram of a guard correlation / peak detection circuit 70 in the OFDM receiver according to the third embodiment.
- FIG. 38 shows a timing chart of each signal in the guard correlation / peak detection circuit 70.
- the OFDM receiver according to the third embodiment includes a guard correlation / peak detection circuit 70 as shown in FIG. 37 instead of the guard correlation / peak detection circuit 12.
- the guard correlation / peak detection circuit 70 includes a delay circuit 31, a complex conjugate circuit 32, a multiplication circuit 33, a moving sum circuit 34, an amplitude calculation circuit 35, and an angle conversion circuit 36. It includes a self-running counter 37, an output circuit 39, a timing control counter 71, an accumulative addition circuit 72, and a peak detection circuit 73.
- FIG. 38 (A) shows the OFDM time domain signal output from the carrier frequency error correction circuit 9
- FIG. 38 (B) shows the OFDM time domain signal delayed by the effective symbol time by the delay circuit 31. Is shown.
- FIG. 38 (C) shows a guard correlation signal indicating the correlation between the OFDM time domain signal and the OFDM time domain signal delayed by the effective symbol (N u samples).
- the timing control counter 71 counts the symbol flag (a flag that is set to High (1) when the counter value N becomes 0) output from the free-running counter 37.
- the timing control count 7 1 is the cumulative addition symbol number M (M is a natural number of 1 or more.) This is a counter for one cycle. That is, the timing control counter 71 is a counter that cyclically counts from 0 to M-1.
- the timing control counter 71 generates a valid flag (a flag that becomes High (1) when the counter value becomes 0), and outputs the valid flag to the accumulative addition circuit 72, the peak detection circuit 73, and the output circuit. Supply to 39.
- the accumulative addition circuit 72 accumulatively adds the amplitude component of the guard correlation signal output from the amplitude calculation circuit 35 at a symbol cycle, as shown in FIG. Specifically, within one cycle (0 to M-1) of the timing control counter 71 (from the timing when the valid flag becomes High (1), the valid flag is then changed to High (1) The amplitude component is cumulatively added until).
- the cumulative addition circuit 72 refers to the count value N output from the free-running counter 37 and cumulatively adds values obtained when the count value is the same. That is, the signal components at the same timing in the OFDM symbol are cumulatively added.
- the cumulative addition circuit 72 supplies a cumulative signal indicating the cumulative addition value of the amplitude component of the guard correlation signal to the peak detection circuit 73.
- the peak detection circuit 73 detects the point with the highest cumulative addition value within one cycle (0 to Ns-l) of the timing control counter 71, and detects the count value of the self-running count 37 at that point. When the count value of the timing control counter 71 shifts to the next cycle, the peak detection circuit 73 detects a new point at which the cumulative addition value is high. The count value detected by the peak detection circuit 73 becomes a peak timing value Np indicating the peak time of the guard correlation signal. Further, the peak detection circuit 73 also detects the phase component of the guard correlation signal at the peak time, and outputs the detected phase component to the output circuit 39.
- the output circuit 39 fetches the count value output from the peak detection circuit 73 at a timing when the count value of the timing control counter 71 becomes 0 (timing when the valid flag becomes High (1)) and stores it in an internal register. It is stored, and the count value is set so that it can be output to the outside (Fig. 38 (E)).
- the count value stored in the register is output to the subsequent timing synchronization circuit as information indicating the peak time of the guard correlation signal (peak timing value Np).
- the output circuit 39 fetches the phase component output from the peak detection circuit, stores the phase component in the internal register, and stores the phase component to the outside. And set it to a state where it can be output.
- the phase component stored in the register is calculated by the subsequent narrowband carrier error calculation. Output to output circuit 14.
- the guard correlation signal is cumulatively added for M symbols, and the peak position is calculated based on the result of the cumulative addition. Therefore, the boundary position can be detected with higher accuracy than when the peak position is detected for each symbol.
- the guard correlation / peak detection circuit 70 outputs a peak timing value Np (FIG. 38 (F)), a phase component, a valid flag (FIG. 38 (G)), and a symbol flag (FIG. 38 (H)).
- the peak timing value Np and the phase component are output to the outside at the timing when the valid flag becomes High (1). That is, the peak timing value Np and the phase component are output for each M symbol.
- the symbol flag (FIG. 38 (H)) is a flag which becomes High (1) in each cycle of the free-running counter 37 (timing when the counter value of the free-running counter 37 becomes 0).
- FIG. 39 shows a block diagram of the symbol boundary calculating circuit 74 in the OFDM receiving apparatus according to the third embodiment.
- the OFDM receiving apparatus includes a symbol boundary calculating circuit 74 as shown in FIG. 39 instead of the symbol boundary calculating circuit 43.
- the symbol boundary calculation circuit 74 includes a phase comparison circuit 51, a limiter 52, an asymmetric gain circuit 53, a low-pass filter 54, a clock error correction circuit 55, a synchronization management circuit 57, a clock error correction circuit 75, A phase generating circuit 76 and an output circuit 77 are provided.
- phase comparison circuit 51 The operations of the phase comparison circuit 51, the limiter 52, the asymmetric gain circuit 53, the one-pass filter 54, and the synchronization management circuit 57 are the same as those in the first embodiment.
- the peak timing value Np, the valid flag, and the symbol flag are input to the symbol boundary calculation circuit 74 from the guard correlation / peak detection circuit 70.
- the valid flag is High (1) only once per M symbol.
- the symbol flag is High (1) for each symbol.
- the symbol boundary calculation circuit 43 is a circuit that can calculate the symbol boundary position Nx for each symbol with respect to the peak timing value Np input once to the M symbol.
- FIG. 40 shows a circuit configuration of the clock error correction circuit 75.
- the clock error correction circuit 75 receives the average phase difference Ave ⁇ ⁇ ⁇ ⁇ , which is the output value of the low-pass filter 54, and the valid flag output from the guard correlation / peak detection circuit 70.
- the clock error correction circuit 75 also receives the clock frequency error, which is the output value of the clock frequency error calculation circuit 41, and the first load flag from the synchronization management circuit 57.
- the clock error correction circuit 75 includes a multiplier 75a, a first adder 75b, a first register 75c, a second register 75d, and a second adder. Container 7 5e.
- the multiplier 75a multiplies the average phase difference Ave output from the low-pass filter 54 by a predetermined coefficient K1.
- the output value of the multiplier 75a represents the residual component of the clock frequency error.
- the first adder 75b adds the currently estimated clock frequency error stored in the first register 75c to the residual component output from the multiplier 75a, Calculate the clock frequency error that is corrected for the average phase difference Ave A ⁇ .
- the first register 75c stores the currently estimated clock frequency error output from the first adder 75b.
- the first register 75c is a register with a so-called load enable function, and an enable flag is input to the enable port EN, and the output value of the first adder 75b is input to the input port!).
- the first load flag output from the synchronization management circuit 57 is input to the load enable port LEN, and the clock frequency error from the clock frequency error calculation circuit 41 is input to the load terminal LD. Therefore, if it is determined by the synchronization management circuit 57 that the output value of the clock frequency error calculation circuit 41 is stable, the first register 75c stores the output of the clock frequency error calculation circuit 41. The value is taken in internally, and if it is determined to be unstable, the output value of the first adder 75b is taken in.
- the second register 75 d stores the average phase difference Ave A 0 output from the low-pass filter 54.
- the second register 75d is a register with an enable function.
- the enable flag is input to the enable port. That is, the second register 75 d delays the average phase error Ave A ⁇ by one valid flag period (M symbol period).
- the second adder 75e adds the clock frequency error output from the first register 75c to the average phase difference Ave ⁇ S output from the second register 75d.
- the average phase difference Ave ⁇ to which the clock frequency error has been added is supplied to the phase generation circuit 76 and the output circuit 77.
- the clock error correction circuit 75 corrects the clock frequency error component with respect to the average phase error Ave ⁇ 0, and outputs the output average phase error Ave ⁇ S to one valid flag period (M symbol period). ) Can be retained.
- FIG. 41 shows a circuit configuration of the phase generation circuit 76 and a circuit configuration of the output circuit 77.
- the average phase difference ⁇ S which is the output value of the clock error correction circuit 75, and the valid flag output from the guard correlation / peak detection circuit 70 are input to the phase generation circuit 76.
- the initial phase which is the output value of the initial phase calculation circuit 42, and the second load flag from the synchronization management circuit 57 are also input to the phase generation circuit 76.
- the phase generation circuit 76 includes an adder 76a and a register 76b.
- the average phase difference Ave ⁇ output from the clock error correction circuit 75 and the current estimated phase stored in the register 76b are input to the adder 76a.
- the adder 76a adds the average phase difference Ave A ⁇ and the current estimated phase, and outputs a symbol boundary position Nx.
- the register 76 b is a register having a so-called load enable function, a valid flag is input to an enable port EN, an output value of the first adder 76 a is input to an input port D,
- the second load flag output from the synchronization management circuit 57 is input to the load enable port LEN, and the initial phase is input from the initial phase calculation circuit 42 to the load terminal LD. Therefore, if the synchronization management circuit 57 determines that the output value of the initial phase calculation circuit 42 is stable, the register 76 b stores the output value of the initial phase calculation circuit 42 internally. If it is determined to be unstable, the output value of the adder 76a is taken in.
- the symbol boundary position Nx output from the phase generation circuit 76 is supplied to the phase comparison circuit 51.
- the phase generation circuit 76 calculates the symbol boundary position Nx by adding the currently estimated phase to the average phase difference Ave AS. In other words, the phase generation circuit 76 adds the error component of the phase calculated on the path from the phase comparison circuit 51 to the clock error correction circuit 75 to the currently estimated phase to obtain the final symbol. Generates an output phase (symbol boundary position N x) indicating the boundary position.
- the value in the register 76b is updated every valid flag period (for each M symbol).
- the output circuit 77 receives the average phase difference Ave A ⁇ , which is the output value of the clock error correction circuit 75, and the symbol flag output from the guard correlation / peak detection circuit 70.
- the output circuit 77 also receives the initial phase, which is the output value of the initial phase calculation circuit 42, and the second load flag from the synchronization management circuit 57.
- the output circuit 77 includes a multiplier 77a, an adder 77, a first register 77c, and a second register 77d.
- the average phase difference Ave ⁇ output from the clock error correction circuit 75 is input to the multiplier 77a.
- the average phase error Ave ⁇ S is a value that is updated every M symbol.
- the multiplier 77a multiplies the average phase error Ave A0 by 1 / M and interpolates to a value corresponding to one symbol.
- the adder 77b receives the output value of the multiplier 77a and the current estimated phase stored in the register 77c.
- the adder 77b adds the average phase difference Ave AS interpolated to the value for each symbol and the current estimated phase, and outputs a symbol boundary position Nx.
- the register 77c is a register with a so-called load enable function.
- the enable flag EN is input to the enable port EN, the output value of the adder 77b is input to the input port!), And the load enable is performed.
- the second load flag output from the synchronization management circuit 57 is input to the port LEN, and the initial phase is input from the initial phase calculation circuit 42 to the load terminal LD. Therefore, if the synchronization management circuit 57 determines that the output value of the initial phase calculation circuit 42 is stable, the register 76 b stores the output value of the initial phase calculation circuit 42 internally. If it is determined to be unstable, the output value of the adder 76a is taken in.
- the symbol boundary position Nx output from the phase generation circuit 76 is supplied to the symbol boundary correction circuit 44.
- the register 77d is a register that delays the signal input to the input port D by one clock.
- the valid flag output from the guard correlation / peak detection circuit 70 is input to the register 77 d input port]), and a simple boundary correction circuit 44 is connected to the output port Q. Therefore, the register 77 d supplies the symbol flag to the symbol boundary correction circuit 44 by synchronizing the timing with the symbol boundary position Nx.
- the symbol flag output from the register 77d is used for the symbol supplied to the symbol boundary correction circuit 44. Output as valid flag of boundary position Nx.
- the average phase error Ave ⁇ calculated once for each M symbol in the path from the phase comparison circuit 51 to the clock error correction circuit 75 is set to 1 / M.
- the value is cumulatively added for each symbol. Therefore, even if the guard correlation / peak detection circuit 70 generates the peak timing value Np for each M symbol, the symbol boundary position NX can be generated for each symbol.
- Some transmission standards for OFDM signals can change the period of the OFDM symbol and the length of the guard interval.
- the ISDB-T standard specifies one to three modes, and the effective symbol length can be changed according to the setting of this mode.
- the ratio between the symbol length and the guard interval length can also be changed.
- one of 1/4, 1/8, 1/16, and 1/32 can be selected as the ratio between the effective symbol length and the guard interval length.
- the OFDM receiving apparatus has a function of switching various control parameters in accordance with the symbol period and guard-in duration of an OFDM signal to be received.
- An OFDM receiver is a modification of the timing synchronization circuit of the OFDM receiver 1 according to the first embodiment, and further includes a mode generation circuit and a controller. The rest is the same as the first embodiment. Therefore, in the OFDM receiving apparatus according to the fourth embodiment of the present invention, only the timing synchronization circuit, the mode generation circuit and the controller will be described, and the same components as those of the first embodiment will be described. Are denoted by the same reference numerals in the drawings, and a detailed description thereof will be omitted.
- FIG. 42 shows a block diagram of a timing synchronization circuit 80 in the OFDM receiver according to the fourth embodiment.
- the OFDM receiver according to the fourth embodiment includes a timing synchronization circuit 80, a mode / GI generation circuit 81, and a band control circuit 82.
- the timing synchronization circuit 80 is provided in place of the timing synchronization circuit 13 of the OFDM receiver 1 according to the first embodiment.
- the mode / GI generation circuit 81 is a circuit that generates information (mode) indicating the effective symbol length of the received OFDM signal and information (GI) indicating the guard interval length.
- the mode and GI setting information are provided from, for example, an external controller or a user.
- the mode / GI generation circuit 81 is a circuit that detects setting information of the controller and the user and supplies the information to the symptom boundary calculation circuit 83.
- the band control circuit 82 is a circuit that generates information (band control information) indicating the set value of each filter coefficient and gain coefficient in the symbol boundary calculation circuit 83.
- the bandwidth control setting information is provided, for example, from an external controller or a user.
- the band control circuit 82 is a circuit that detects setting information of the controller / user and supplies the information to the symbol boundary calculation circuit 83.
- the symbol boundary calculation circuit 83 includes a phase comparison circuit 51, a limiter 52, an asymmetric gain circuit 53, a low-pass filter 54, a clock error correction circuit 55, and a phase
- the circuit includes a generation circuit 56, a synchronization management circuit 57, a first register 58, a second register 59, a third register 60, and a filter control circuit 84.
- phase comparison circuit 51 The internal circuit configuration and operation of the phase comparison circuit 51, limiter 52, asymmetric gain circuit 53, one-pass filter 54, and quick error correction circuit 55 are the same as those in the first embodiment. However, various parameters such as filter coefficients, gain coefficients, and various threshold values can be changed from the filter control circuit 84.
- the filter control circuit 8 is based on the mode / GI and band control information, and based on the phase comparison circuit 51, the limiter 52, the asymmetric gain circuit 53, the low-pass filter 54, and the filter coefficient and gain of the clock error correction circuit 55. It controls the coefficients and various parameters of various thresholds.
- the symbol boundary calculating circuit 43 of the OFDM receiving apparatus In the symbol boundary calculating circuit 43 of the OFDM receiving apparatus according to the first embodiment, one loop filtering process is performed for each input interval (valid flag generation interval) of the peak timing value Np.
- This processing cycle is the cycle of the self-running counter 37. That is, it is synchronized with the symbol period of the received OFDM signal. Therefore, in the first embodiment, when the mode or guard interval length of the received OFDM signal is changed, the cyclic period of self-running counter 37 is changed accordingly. The cycle of self-propelled counter 37 changes Then, even if the values of the filter coefficients and the like in the symbol boundary calculation circuit 43 are not changed, the filter band changes according to the symbol length.
- the filter band set in the sympol boundary calculation circuit 43 be changed not in dependence on the symbol length but in accordance with the reception environment such as the Doppler frequency.
- the filter coefficient, the gain coefficient, and various kinds of signals according to the mode / GI are set so that the basic filter band does not change even if the symbol length changes. Controls various parameters of the threshold.
- the filter coefficient in mode 3 is used as the basic filter coefficient, and when the setting is changed to mode 3, all filter coefficients are changed to 1/2, and so on. Do.
- the filter control circuit 84 changes the above-mentioned basic filter band in response to a band change command from the user so that various parameters of the filter coefficient, the gain coefficient, and various thresholds according to the mode / GI are changed. Control the evening.
- the OFDM receiving apparatus of the fourth embodiment it is possible to perform optimal demodulation according to the setting value of the received OFDM signal.
- the filter coefficient itself is changed so that the filter band is not changed by changing the set value of the received OFDM signal.
- the guard correlation / peak detection circuit 12 May be controlled at intervals of generation of the peak timing value Np. That is, even if the symbol length changes, the peak timing Np is generated at a constant interval so that, for example, the peak timing Np is thinned out or the peak timing generated by the guard correlation / peak detection circuit 12 is generated.
- the interval of the value Np itself may be controlled.
- the OFDM receiver according to the fifth embodiment is different from the OFDM receiver according to the first embodiment in that the symbol boundary calculation circuit 43 is not a feedback filter having a DLL configuration but a feedforward filter. It has been replaced.
- An OFDM receiver according to a fifth embodiment of the present invention described below is the same as the first embodiment except that the timing synchronization circuit 13 of the OFDM receiver 1 according to the first embodiment is changed. It is. Therefore, for the OFDM receiver according to the fifth embodiment of the present invention, Only the timing synchronization circuit will be described, and the same components as those in the first embodiment will be denoted by the same reference numerals in the drawings, and detailed description thereof will be omitted.
- the OFDM receiving apparatus includes an evening synchronization circuit 85 as shown in FIG.
- This timing synchronization circuit 85 is provided in place of the timing synchronization circuit 13 of the first embodiment.
- the timing synchronization circuit 85 includes an initial phase calculation circuit 42, a symbol boundary calculation circuit 86, a symbol boundary correction circuit 44, and a start flag generation circuit 45.
- FIG. 45 shows the internal configuration of the sympol boundary correction circuit 44.
- the symbol boundary calculation circuit 86 includes an asymmetric gain circuit 87, a single-pass filter 88, a synchronization management circuit 89, a selector 90a, and a register 90b with an enable function. Have.
- the peak timing value Np and the valid flag, and the initial phase output from the initial phase calculation circuit 42 are input to the symbol boundary calculation circuit 86.
- the asymmetric gain circuit 87 stores the peak evening value Np output from the guard correlation / peak detection circuit 12 and the symbol boundary position Nx, which is the output value of the symbol boundary calculation circuit 86, for one valid flag by the register 90b. Entered after being delayed.
- the asymmetric gain circuit 87 includes a subtractor 87a, a comparator 87b, a first multiplier 87c for multiplying the peak timing value Np by a first gain Ga, and a second multiplier 87c for multiplying the peak timing value Np by a second.
- the subtracter 87a subtracts the symbol boundary position Nx from the peak timing value Np input from the guard correlation / peak detection circuit 12, and calculates a difference value.
- the comparator 87b compares the difference value output from the subtractor 87a with 0, and outputs Low (0) when the difference value is smaller than 0, and outputs High (0) when the difference value is 0 or more. (1) is output. If the output of the comparator 87 b is Low (0), the selector 87 e selects and outputs the output value of the first multiplier 87 c (the value obtained by multiplying the peak timing value Np by Ga). Then ratio If the output of the comparator 87b is High (1), the output value of the second multiplier 87d (the peak evening value Np multiplied by Gb) is selected and output. .
- the asymmetric gain circuit 87 determines whether the peak timing value Np is earlier or later than the symbol boundary position NX. If the peak timing value Np is earlier than the symbol boundary position NX, the gain (Gb ), And if the peak timing value Np is later than the symbol boundary position Nx, multiply by a larger gain (G a). In other words, the asymmetric gain circuit 87 sets the peak timing so that it can easily synchronize with a faster signal (main wave) when multiple peak values are detected by multipath or the like. The gain by which the value N p is multiplied is changed.
- the peak timing value Np multiplied by the gain by the asymmetric gain circuit 87 is supplied to the one-pass filter 88.
- the peak pass timing value Np multiplied by the gain by the asymmetric gain circuit 87 and the valid flag output from the guard correlation / peak detection circuit 12 are input to the mouth-pass filter 88.
- the oral pass filter 88 receives the initial phase output from the initial phase calculation circuit 42 and the load flag output from the synchronization management circuit 89.
- the single-pass filter 88 includes a register 88a, a multiplier 88b, a subtractor 88c, and a caro calculator 88d.
- Register 88a stores the current estimated phase.
- the multiplier 88b multiplies the current estimated phase stored in the register 88a by a predetermined coefficient.
- the subtracter 88 c subtracts the value output from the multiplier 88 b from the value output from the asymmetric gain circuit 87.
- the adder 88d adds the current estimated phase stored in the register 88a and the output value of the subtractor 88c to output an estimated phase.
- the output value of the adder 88d becomes the output value of the low-pass filter 88.
- the selector 90a switches between the output value of the low-pass filter 88 and the output value from the initial phase calculation circuit 42, and outputs it as the symbol boundary position Nx.
- the switching control of the selector 90a is performed by a load flag output from the synchronization management circuit 89.
- the load flag is High (1)
- the initial phase output from the initial phase calculation circuit 42 is output as the symbol boundary position Nx.
- the load flag is Low (0)
- the value output from the pass filter is output as the symbol boundary position Nx.
- the register 88a is a register with a load enable function.
- the enable flag is input to the enable port EN, the output value of the adder 88d is input to the input port D, and the load enable
- the load flag output from the synchronization management circuit 89 is input to one pull port LEN, and the initial phase is input from the initial phase calculation circuit 42 to the load terminal LD. That is, the register 88a stores two estimated values as the current estimated phase, the estimated value output from the adder 88d and the estimated value output from the external initial phase calculation circuit 42. It is possible to input.
- the above two values can be used for the current estimated phase input to the register 88a, but the initial phase output from the initial phase calculation circuit 42 reduces the phase error.
- the response is fast because it is not determined by cumulative addition.
- the synchronization management circuit 89 manages two states, a synchronization pull-in state and a steady state.
- the synchronization management circuit 89 sets the load flag to High (1) and sets the initial phase output from the initial phase calculation circuit 42 in the register 88a in order to shorten the pull-in period in the synchronization pull-in state. While storing, the value output from the initial phase calculation circuit 42 from the selector 90a is output as the symbol boundary position Nx. On the other hand, in the steady state, the output value of the single-pass filter 88 output from the adder 88 d is stored in the register 88 a with the load flag set to Low (0), and Mouth-to-pass fill E 8 Output the output value of 8 as the symbol boundary position Nx.
- the synchronization management circuit 89 manages the state between the pull-in state and the steady state using, for example, a state machine.
- a state machine for example, there is a method using a timer in which a retracted state is set until a certain time elapses after the operation is started, and a steady state is set after a certain time elapses, or an initial phase calculation circuit 4
- There is a method of monitoring the output value of the initial phase calculation circuit 42 which sets the retracted state until the amount of change in the output value of step 2 falls within a certain range, and then sets the state to the steady state after entering the certain range. .
- the sympol boundary calculation circuit is a feed-forward type filter, so that the synchronization processing of the symbol boundary position is drawn at higher speed. (Modification)
- the symbol boundary calculation circuit 86 may be a circuit as shown in FIG.
- the symbol boundary calculation circuit 86 shown in FIG. 46 has an asymmetric mouth-pass filter 91, a synchronization management circuit 89, a selector 90a, and a register 90b with an enable function.
- the asymmetric low-pass filter 91 receives the peak timing value Np from the guard correlation / peak detection circuit 12 and the validity flag output from the guard correlation / peak detection circuit 12.
- the asymmetric low-pass filter 91 receives the initial phase output from the initial phase calculation circuit 42 and the load flag output from the synchronization management circuit 89.
- the asymmetric low-pass filter 91 includes a first subtractor 9 la, a comparator 9 lb, a register 91 c, a second subtractor 91 d, and a first multiplier that multiplies the first coefficient Ka. 91 e, a second multiplier 91 f for multiplying the second coefficient Kb, and a selector 91 g.
- the relationship between the first gain Ka and the second gain Kb is Ka> Kb.
- the first subtractor 91a subtracts the symbol boundary position Nx from the peak evening value Np input from the guard correlation / peak detection circuit 12, and calculates a difference value.
- the comparator 9 lb compares the difference value output from the first subtractor 91 a with 0, outputs Low (0) if the difference value is smaller than 0, and outputs H if the difference value is 0 or more. Output i gh (1).
- Register 91c stores the current estimated phase.
- the second subtracter 91 d subtracts the current estimated phase stored in the register 91 c from the peak timing value N p output from the guard / peak detection circuit 12, and calculates the residual Calculate the components.
- the first multiplier 91e multiplies the residual component output from the second subtractor 91d by a first coefficient Ka.
- the selector 91 g selects and outputs the output value of the first multiplier 91 e (the value obtained by multiplying the residual component by Ka). If the output of the comparator 9 lb is High (1), the output value of the second multiplier 91 f (the value obtained by multiplying the residual component by Kb) is selected and output.
- the adder 91h adds the current estimated phase stored in the register 91c and the output value of the selector 91g to output an estimated phase.
- the output value of the adder 91h is the output value of the asymmetric mouth-pass filter 91.
- the symbol boundary calculation circuit is a feedforward type IIR filter, so that the synchronization processing of the symbol boundary position is more quickly performed.
- the asymmetric low-pass filter 91 determines whether the peak timing value Np is earlier or later than the symbol boundary position NX, and the peak timing value Np is smaller than the symbol timing. Set the passband higher if it is earlier than the boundary position NX, and set it lower if the peak timing value Np is later than the symbol boundary position NX. In other words, the asymmetric low-pass filter 91 adjusts the pass band so that the response characteristic becomes faster for a signal (main wave) that is earlier in time when a plurality of peak values are detected by multipath or the like. Switching.
- the OFDM receiver of the sixth embodiment has a configuration in which the clock frequency error calculator 41 and the initial phase calculator 42 are removed from the evening synchronization circuit 13 of the OFDM receiver of the first embodiment.
- the other configuration is the same as that of the first embodiment. Therefore, in the OFDM receiver according to the sixth embodiment of the present invention, only the timing synchronization circuit will be described, and the same components as those in the first embodiment will be denoted by the same reference numerals in the drawings. The detailed description is omitted.
- the OFDM receiving apparatus of the sixth embodiment employs a timing synchronization circuit 92 as shown in FIG.
- This timing synchronization circuit 92 is provided in place of the timing synchronization circuit 13 of the first embodiment.
- the timing synchronization circuit 92 includes a symbol boundary correction circuit 93, a symbol boundary correction circuit 44, and a start flag generation circuit 45. That is, the configuration is such that the clock frequency error calculation circuit 41 and the initial phase calculation circuit 42 are removed from the evening synchronization circuit of the first embodiment.
- the symbol boundary calculation circuit 93 is configured as shown in FIG. 6 As shown, the phase comparison circuit 51, the limiter 52, the asymmetric gain circuit 53, the low-pass filter 54, the clock error correction circuit 55, the phase generation circuit 56, and the first register
- the configuration includes an evening 58, a second register 59, and a third register 60. That is, the configuration is such that the synchronization management circuit 57 is removed from the symbol boundary calculation circuit 43 of the first embodiment.
- the clock error correction circuit 55 may use the register 55b as a register with an enable function as shown in FIG.
- the register 55b may be a register with an enable function, as shown in FIG.
- the OFDM receiving apparatus according to the seventh embodiment is obtained by replacing the clock frequency error calculating circuit 41 of the OFDM receiving apparatus according to the first embodiment with a circuit as shown in FIG. 51.
- the configuration is the same as in the first embodiment. Therefore, in the OFDM receiving apparatus according to the seventh embodiment of the present invention, only the clock frequency error calculating circuit 41 will be described.
- the clock frequency error calculation circuit 41 applied to the seventh embodiment includes an inclination detection circuit 95, a histogram generation circuit 96, and an output circuit 97. .
- the slope detection circuit 95 is a circuit that detects the temporal change rate of the peak timing value Np input from the guard correlation / peak detection circuit 12. That is, the circuit detects the amount of inclination S of the peak timing value Np.
- a plurality of detection paths having different detection periods for detecting the amount of inclination are provided in the inclination detection circuit 95, and a plurality of inclination amounts S obtained in each detection path are output.
- the reception levels of the main wave and the delayed wave fluctuate periodically. Therefore, when the peak position of the guard correlation signal is detected, the boundary of the symbol indicated by the peak position is periodically switched between the main wave and the delayed wave. In other words, if the reception level of the main wave is higher, If the reception level of the delayed wave is higher, the symbol boundary position of the delayed wave is detected.
- the peak timing value Np is an increase in the time difference between the main wave and the delayed wave at substantially constant periods (fading periods). And decrease are alternately repeated. Also, the cycle at which the main wave reception level and the delayed wave reception level are switched by frequency selective fading differs depending on the reception environment, and becomes longer or shorter.
- a plurality of slope detection paths having different detection periods T for detecting the slope amount S of the peak timing value Np are provided in the slope detection circuit 95, and the slopes detected by the plurality of slope detection paths are provided.
- the clock frequency error is comprehensively measured based on the quantity S (for example, S 1 to S 5 shown in FIG. 51). By detecting in this way, even if frequency selective fading or the like occurs, the clock frequency error can be detected more accurately.
- the histogram generation circuit 96 receives a plurality of slope amounts S having different detection periods of the slope of the peak timing value Np.
- the histogram generation circuit 96 classifies the plurality of input gradient amounts S into classes divided according to the magnitude (level) of the gradient amount S, and a histogram indicating the frequency of detection of the gradient amount S for each classified class. Generate The histogram generation circuit 96 accumulates the detection frequency of the amount of inclination S in the histogram, and outputs the mode of the histogram (class value of the class with the highest frequency).
- the output circuit 97 determines whether or not the mode output from the histogram generation circuit 96 is stable. If the mode is determined to be stable, the output circuit 97 generates a synchronization establishment flag and outputs the synchronization establishment flag. The frequent value is output to the outside as a clock frequency error.
- a plurality of paths for detecting the amount of slope S of the peak timing value Np are provided, and the clock frequency error is calculated by setting the detection intervals of each path to different intervals. are doing. Therefore, for example, even when the reception environment deteriorates, the clock frequency error can be accurately calculated.
- the frequency of detecting the amount of slope of the peak timing value Np is replaced with a histogram, and the clock frequency error is calculated based on the histogram. An accurate and stable clock frequency error can be calculated.
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- Synchronisation In Digital Transmission Systems (AREA)
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP20030780893 EP1492259A1 (en) | 2002-12-27 | 2003-12-18 | Ofdm demodulation apparatus |
US10/505,794 US20050147186A1 (en) | 2002-12-27 | 2003-12-18 | Ofdm demodulation apparatus |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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JP2002382212A JP2004214961A (ja) | 2002-12-27 | 2002-12-27 | Ofdm復調装置 |
JP2002-382212 | 2002-12-27 |
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WO2004062149A1 true WO2004062149A1 (ja) | 2004-07-22 |
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PCT/JP2003/016260 WO2004062149A1 (ja) | 2002-12-27 | 2003-12-18 | Ofdm復調装置 |
Country Status (5)
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US (1) | US20050147186A1 (ja) |
EP (1) | EP1492259A1 (ja) |
JP (1) | JP2004214961A (ja) |
CN (1) | CN1692588A (ja) |
WO (1) | WO2004062149A1 (ja) |
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CN1692588A (zh) | 2005-11-02 |
US20050147186A1 (en) | 2005-07-07 |
JP2004214961A (ja) | 2004-07-29 |
EP1492259A1 (en) | 2004-12-29 |
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