WO2003058700A1 - Procede de traitement au plasma - Google Patents

Procede de traitement au plasma Download PDF

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Publication number
WO2003058700A1
WO2003058700A1 PCT/JP2002/013861 JP0213861W WO03058700A1 WO 2003058700 A1 WO2003058700 A1 WO 2003058700A1 JP 0213861 W JP0213861 W JP 0213861W WO 03058700 A1 WO03058700 A1 WO 03058700A1
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WO
WIPO (PCT)
Prior art keywords
mask
plasma
film
processing
gas containing
Prior art date
Application number
PCT/JP2002/013861
Other languages
English (en)
Japanese (ja)
Inventor
Kiwamu Fujimoto
Jeong Jy
Takashi Fuse
Original Assignee
Tokyo Electron Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Limited filed Critical Tokyo Electron Limited
Priority to AU2002359950A priority Critical patent/AU2002359950A1/en
Publication of WO2003058700A1 publication Critical patent/WO2003058700A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

Definitions

  • the present invention relates to a plasma processing method performed in a semiconductor device manufacturing process. Background technology
  • a conventional plasma processing method in which an interlayer insulating film in an object to be processed, for example, an organic insulating film is etched through an opening pattern of a mask, and then the mask is removed is performed by removing the organic insulating film in a processing vessel using a fluorocarbon or the like.
  • the organic insulating film is etched using a CF-based gas plasma until a barrier layer such as a SiN film below the organic insulating film is exposed, and then a plasma such as oxygen gas is used in the same processing vessel.
  • the present invention has been made to solve the above problems, and has as its object to provide a plasma processing method for preventing generation of reactive species of F and removing a mask while suppressing the removal of a barrier layer. It is another object of the present invention to provide a blaze processing method for removing the mask while maintaining the selectivity of the mask with respect to the silicon layer.
  • the gas containing F introduced into the processing vessel is pumped. Forming a film on the Si-containing film in the object to be processed through a mask opening pattern on the film to expose the Si-containing film; A step of removing a by-product containing F attached to the substrate, and a step of removing the mask in the processing container.
  • the gas containing F introduced into the processing chamber is turned into plasma, and the Si-containing film in the object to be processed is opened through a mask on the Si-containing film.
  • the gas containing the introduced 0 2 into plasma in the first or second plasma processing method, in the step of removing a by-product containing F attached to an object in the processing container, is characterized in that the removal of the by-products.
  • the gas containing N 2 and H 2 is turned into plasma to remove the mask. It is characterized by the following.
  • the gas containing F introduced into the processing chamber is turned into plasma, and the film on the Si-containing film in the object to be processed is masked on the film. Etching through the opening pattern to expose the Si-containing film; and removing the mask in a processing container separate from the processing container.
  • the gas containing F introduced into the processing container is turned into plasma, and the Si-containing film in the object to be processed is passed through an opening pattern of a mask on the film. It is characterized by comprising a step of etching halfway and a step of removing the mask in a processing container different from the processing container.
  • the gas containing F introduced into the processing container is turned into plasma, and the film on the Si-containing film in the object to be processed is formed on the (previous) film. etching through the opening pattern of the mask on the, to expose the S i containing film, to remove the mask by plasma gas containing N 2 by the processing chamber And a step of performing the above.
  • the gas containing F introduced into the processing container is turned into plasma, and the Si-containing film in the object to be processed is converted into a mask on the (previous) film. It is characterized by comprising a step of etching partway through the opening pattern and a step of removing the mask by converting a gas containing N 2 into plasma in the processing container.
  • the gas containing N 2 contains H 2 .
  • the flow rate of H 2 to the sum of the flow rates of the flow rate and H 2 N 2 is greater than 0%, it is characterized in that 20% or less.
  • the gas containing F is introduced into the processing vessel, and the gas containing F is turned into plasma, and the film on the Si-containing film in the object to be processed is removed from the mass on the film.
  • a step of exposing the Si-containing film by etching through a sealing pattern, and a step of removing the mask by converting a gas containing NH 3 into plasma in the processing container. is there.
  • the gas containing F introduced into the processing container is turned into plasma, and the Si-containing film in the object to be processed is masked on the (previous) film.
  • S i containing film is a film having at least one of S iN, S i0 2, S iC It is characterized by the following.
  • the gas containing F is at least CF 4 , CHFas CH2F2 CH 3 F, C2F4.
  • the gas is a gas containing at least one of F 6 , C 3 F 8 , C 4 F 6 , C 4 F 8 , and C 8 F 8 .
  • the mask is a photoresist.
  • FIG. 1 is a schematic sectional view showing an example of a plasma processing apparatus applied to the plasma processing method of the present invention.
  • FIG. 2 is a schematic sectional view showing a main part of a wafer used in one embodiment of the plasma processing method of the present invention.
  • FIG. 3 is a schematic sectional view showing a main part of a wafer used in another embodiment of the plasma processing method of the present invention.
  • FIG. 4 is a schematic sectional view showing a main part of a wafer used in still another embodiment of the plasma processing method of the present invention.
  • FIG. 5 is a view showing the results of Example 2 of the present invention, and shows the relationship between the flow rate ratio of the processing gas (N 2 / (N 2 + H)), the asshing rate of the mask, and the selection ratio of the mask to the barrier layer. It is a graph which shows the best mode for carrying out the invention.
  • a plasma processing apparatus 10 used in the present embodiment includes a processing vessel 11 formed of metal (for example, aluminum whose surface is oxidized) and grounded; A susceptor 13 made of a conductor disposed at the center of the bottom surface of the inside 1 via an insulator 12 and a shower head formed above the susceptor 13 and supplying a processing gas 1 It has four.
  • a high frequency power supply 16 for plasma generation is connected to the susceptor 13 through a mattress 15, and a high frequency power of 13.56 MHz is applied from the high frequency power supply 16 to the susceptor 13.
  • An electrostatic chuck 17 is arranged on the susceptor 13, and a DC power supply 18 is connected to an electrode 17 A interposed in the electrostatic chuck 17.
  • a dipole ring magnet (DRM) 19 is rotatably arranged on the outer periphery of the processing container 11.
  • a processing gas source (not shown) was connected to the top surface of the processing vessel 11.
  • a gas introduction section 11 A is formed, and the processing gas introduced from the gas introduction section 11 A is supplied uniformly through the shower head 14 to the entire surface of the workpiece (eg, wafer) W. is there.
  • An exhaust port 11 B connected to an exhaust pump (not shown) is formed at a lower portion of the processing vessel 11. The inside of the processing vessel 11 is lowered to a predetermined pressure through the exhaust port 11 B through the exhaust pump. It is.
  • the wafer W is loaded into the processing vessel 11 from a loading port (not shown), and is placed on the electrostatic chuck 17 on the susceptor 13.
  • a processing gas is introduced while the inside of the processing container 11 is exhausted, the DRM 19 is rotated, and high-frequency power is applied to the susceptor 13.
  • a DC voltage is also applied to the electrostatic chuck 17 simultaneously with or before and after the application of the high-frequency power, and the wafer W is attracted and fixed on the electrostatic chuck 17.
  • the processing gas is converted into a plasma by applying a rotating magnetic field from the DRM 19, and the portion of the wafer W to be subjected to the plasma processing is processed as follows. Plasma treatment is performed.
  • a metal wiring layer 21, a barrier layer (here, a Si-containing film) 22, an insulating film layer 23, a mask 24 are formed, and a predetermined opening pattern 24 A is formed in the mask 24.
  • the plasma processing target is subjected to plasma processing through the opening pattern 24 A of the mask 24.
  • the insulating film layer 23 is plasma-etched from the opening pattern 24A of the mask 24 using a gas containing a fluorocarbon, for example, as shown in FIG.
  • the step of removing the by-product containing F attached to the components in the processing container 11 was included. Therefore, in the step of removing the mask 24, the barrier was removed. Active species including F acting on the layer 22 are not generated, and the scraping of the barrier layer 22 can be suppressed. Also, the plasma of the gas containing N 2 and H 2 If the mask 24 is removed, the side surface of the insulating film layer 23 on the Si layer containing the barrier layer 22 can be suppressed from being scraped. In addition, by removing the mask 24 using plasma of N 2 or a gas in which a small amount of H 2 is added to N 2 , it is possible to omit a step of removing a by-product containing F as described later. it can.
  • the mask 24 may be transferred into a processing container different from the processing container in which the etching has been performed, and the mask 24 may be removed in the processing container.
  • the etching of the insulating film layer 23 on the barrier layer 22 and the removal of the mask 24 are performed in separate processing containers, so that the etching process of the insulating film layer 23 on the barrier layer 22 is performed.
  • the mask 24 can be removed in a state where there is no F-containing by-product adhering to the components inside, that is, in a state where active species including F acting on the exposed barrier layer 22 are not generated. Shaving can be suppressed.
  • the mask for the barrier layer 22 can be formed.
  • the selectivity of the mask is about 30, which makes it possible to remove the mask 24 while maintaining a considerably high value.
  • a small amount of H 2 may be added to the gas containing N 2 .
  • the addition of H 2 it is possible to increase the Adzushingureto mask 24.
  • the flow rate of H 2 to the sum of the flow rate of the flow rate and H 2 in N 2 is preferably 20% or less than 0%, more rather preferably 20% or more than 1%, more preferably 1 % To 10%.
  • the masking rate of the mask 24 is also increased (about 180 nm / min or more) while the selection ratio of the mask 24 to the Si-containing film (barrier layer 22) is maintained at a relatively high level. it can.
  • an inert gas such as Ar or He may be added to the gas for removing these masks.
  • the S i containing film is a membrane having at least one of S iN, S i 0 2, S i C.
  • the film on the Si-containing film is an insulating film having a low relative dielectric constant in order to improve device performance.
  • insulating films having a low relative dielectric constant include MSQ, porous MSQ (trade name of JSR: LKD), porous silica, FSG, and CVD-SiOC (trade names: CO RAL, Black Diamond). No. Of course, S i0 2 also used Can be
  • Examples of the gas containing F for etching the film on the Si-containing film include CF 4 , C 2 F 4 , C 2 F 6 , C 3 F 6 , C 3 F 8 , C 4 F 6 , C 4 and F 8, C etc.
  • 8 F 8 fluoroalkyl force one Bonn, CHF 3 can be used CH2F2S CH 3 Hyde port fluoroalkyl force one Bonn least gas containing any one or more well such as F.
  • N 2 , O 2 , CO, Ar, He or the like may be added to these.
  • the mask used in these inventions, the photoresist is preferred, and 'removing the photoresist, a gas containing the above N 2, other gases including N 2 and H 2, a gas containing 0 2 Of plasma can be used.
  • the present invention can also be applied to, for example, a case where a groove having a dual damascene structure shown in FIG. 3 is formed.
  • the wafer W has a metal wiring layer 31, an underlayer (here, for example, an SiN film) 32, and a Si-containing film layer (here, for example, a Si layer 2 film layer 33 and a mask 34 (here, for example, a photoresist layer) are formed, and the mask 34 is formed with a predetermined opening pattern 34A.
  • the Si-containing film layer 33 is plasma-etched until the underlying layer 32 is exposed through the opening pattern 34A of the mask 34 to form a hole 33A.
  • etching gas for example, it may be used C 4 F 8 (or C 5 F 8, C 4 Fe ) CO and 0 2 and a mixed gas of Ar or the like.
  • N 2 may be further added.
  • the mask 34 is removed by asking using plasma of a mixed gas containing N 2 and H 2 introduced into the processing chamber 11 as shown in FIG.
  • a photoresist is applied to form a mask 35 having an opening pattern 35A larger than the hole 33A in FIG. 3 (b), and then using the same etching gas as in FIG. 3 (a).
  • etching is performed halfway through the Si-containing film layer 33 to form a groove 33B (see (c) in the figure).
  • F By-products are removed.
  • the mask 35 is removed by plasma using the same plasma of the same gas as in the case of removing the mask 34 shown in FIG. 3A, as shown in FIG.
  • the underlying layer 3 2 is etched with CF 4, CHF 3, a mixed gas of CH 2 F least one 0 2 2 N 2 and A r 2 You can.
  • the overetching time is short, and the underlying metal Layer 31 loss is minimized.
  • the present invention can be applied to a case where a groove is first formed in a dual damascene structure.
  • the portion of the wafer W to be subjected to the plasma processing is the same as in the case of FIG. That is, after a mask 44 having an opening pattern 44 A of a predetermined size is formed by a photoresist, as shown in FIG. 4A, the Si-containing film is formed from the opening pattern 44 A of the mask 44. Layer 43 is etched partway to form groove 43A. Subsequently, after the mask 44 is removed by asshing in the same manner as described above, a photoresist is applied again, and an opening pattern 45 A having a diameter smaller than the width of the groove 43 A in FIG. Is formed.
  • the Si-containing film layer 43 is etched from the opening pattern 45 A of the mask 45 to the underlayer (SiN film layer) 42 until the hole 43 B is formed (see FIG. c))). Thereafter, the mask 45 is removed by asking in the same manner as described above (see (d) of FIG. 9).
  • the mask 45 is removed by asking in the same manner as described above (see (d) of FIG. 9).
  • the type of the barrier layer 22 is changed using the plasma processing apparatus shown in FIG. 1, and the plasma processing is performed under the following conditions, that is, the insulating film layer 23 is etched, and the wafer W is unloaded from the processing vessel 11. In this state, by-products containing F were removed (cleaning), and the wafer W was loaded again into the processing container 11 to perform the asshing of the mask 24. Then, the influence of the presence or absence of the cleaning step on the etching rate of each barrier layer 22 was observed. .
  • DRM rotation speed 20 rpm Frequency of high frequency power applied to susceptor: 13.56MHz High frequency power applied to susceptor: 1700W
  • Processing container pressure 150 mT 0 r r
  • Processing container pressure 150 mT 0 r r
  • Processing container pressure 50 mT or r
  • N 2 300 sccm
  • H 2 100 sccm
  • the cleaning process was omitted using the plasma processing apparatus shown in FIG. 1, and the plasma processing, that is, the etching of the insulating film layer 23 and the etching of the mask 24 were performed under the following conditions. Then, the relationship between the flow rates of N 2 and H 2 used in the assing process, the etching rate of the mask, and the selectivity of the barrier layer 22 to the mask 24 was observed.
  • Processing vessel pressure 150 mT or r
  • the mask 24 was removed (asshing) by changing the flow rate ratio of the processing gas (N 2 / (N 2 + H 2)) under the following conditions.
  • Processing vessel pressure 50 mT 0 r r
  • N 2 Da N 2 + H 2
  • Three types of processing vessel pressure Four types of 60, 100, 200, 400 mTorr
  • the photo resist for SiN Selectivity Mosk etching rate / SiN etching rate
  • the photo resist for SiN Selectivity is 15 to 21, 10 OmT 0 rr 17 to 23, 200 mT orr 30 to 36, 40 OmT orr 45 to 52
  • the selection ratio was high in each case o
  • the F-containing by-product generated in the step of exposing the barrier layer is removed before removing the mask.
  • the mask is removed in a processing container different from the processing container used in the step of exposing the barrier layer instead of cleaning, so that the removal of the barrier layer when removing the mask is suppressed. It is possible to provide a plasma processing method that can be used.
  • the Si-containing barrier layer in the object to be processed is exposed.
  • a plasma processing method capable of selectively removing the mask from the barrier layer can be provided.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

L'invention concerne un procédé de traitement au plasma comprenant les étapes suivantes : attaque d'un film isolant présent sur un film contenant du Si (couche barrière); nettoyage dans une chambre de traitement et calcination d'un résist ; ou bien les étapes suivantes : attaque d'un film isolant présent sur la couche barrière et calcination d'un résist dans des chambres de traitement séparés. Dans chaque cas, la calcination d'un résist est effectuée avec un plasma d'un mélange gazeux comprenant en majorité du N2 et une faible quantité de H2. Dans le cas où l'attaque d'un film isolant présent sur un film situé sur la couche barrière est directement suivie par la calcination d'un résist sur le film isolant, un matériau (un radical F ou similaire) réagissant avec la couche barrière est produit à partir de sous-produits formés lors de l'étape d'attaque et appliqué sur un article (une pièce) dans la chambre de traitement, ce qui a pour effet d'attaquer la couche barrière.
PCT/JP2002/013861 2002-01-07 2002-12-27 Procede de traitement au plasma WO2003058700A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2002359950A AU2002359950A1 (en) 2002-01-07 2002-12-27 Plasma treatment method

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2002000933 2002-01-07
JP2002-933 2002-01-07
JP2002104160A JP4326746B2 (ja) 2002-01-07 2002-04-05 プラズマ処理方法
JP2002-104160 2002-04-05

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WO2003058700A1 true WO2003058700A1 (fr) 2003-07-17

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JP (1) JP4326746B2 (fr)
AU (1) AU2002359950A1 (fr)
TW (1) TWI270137B (fr)
WO (1) WO2003058700A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100352014C (zh) * 2004-06-08 2007-11-28 东京毅力科创株式会社 蚀刻方法

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4889199B2 (ja) * 2003-11-05 2012-03-07 株式会社アルバック 低誘電率層間絶縁膜のドライエッチング方法
US20050101135A1 (en) * 2003-11-12 2005-05-12 Lam Research Corporation Minimizing the loss of barrier materials during photoresist stripping
JP5036143B2 (ja) * 2004-06-21 2012-09-26 東京エレクトロン株式会社 プラズマ処理装置およびプラズマ処理方法、ならびにコンピュータ読み取り可能な記憶媒体
JP4672455B2 (ja) * 2004-06-21 2011-04-20 東京エレクトロン株式会社 プラズマエッチング装置およびプラズマエッチング方法、ならびにコンピュータ読み取り可能な記憶媒体
US7951262B2 (en) 2004-06-21 2011-05-31 Tokyo Electron Limited Plasma processing apparatus and method
KR101247833B1 (ko) * 2004-06-21 2013-03-26 도쿄엘렉트론가부시키가이샤 플라즈마 처리 방법
US7740737B2 (en) 2004-06-21 2010-06-22 Tokyo Electron Limited Plasma processing apparatus and method
US7988816B2 (en) 2004-06-21 2011-08-02 Tokyo Electron Limited Plasma processing apparatus and method
JP4523351B2 (ja) * 2004-07-14 2010-08-11 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP4616605B2 (ja) * 2004-09-27 2011-01-19 東京エレクトロン株式会社 プラズマ処理方法、プラズマ処理装置及び記憶媒体
US8193096B2 (en) 2004-12-13 2012-06-05 Novellus Systems, Inc. High dose implantation strip (HDIS) in H2 base chemistry
US8129281B1 (en) 2005-05-12 2012-03-06 Novellus Systems, Inc. Plasma based photoresist removal system for cleaning post ash residue
US7244313B1 (en) * 2006-03-24 2007-07-17 Applied Materials, Inc. Plasma etch and photoresist strip process with intervening chamber de-fluorination and wafer de-fluorination steps
US8435895B2 (en) 2007-04-04 2013-05-07 Novellus Systems, Inc. Methods for stripping photoresist and/or cleaning metal regions
US20110143548A1 (en) 2009-12-11 2011-06-16 David Cheung Ultra low silicon loss high dose implant strip
KR101770008B1 (ko) 2009-12-11 2017-08-21 노벨러스 시스템즈, 인코포레이티드 고주입량 주입 박리 전에 실리콘을 보호하기 위한 개선된 패시베이션 공정
US9613825B2 (en) 2011-08-26 2017-04-04 Novellus Systems, Inc. Photoresist strip processes for improved device integrity
US9514954B2 (en) 2014-06-10 2016-12-06 Lam Research Corporation Peroxide-vapor treatment for enhancing photoresist-strip performance and modifying organic films

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11214356A (ja) * 1998-01-29 1999-08-06 Sony Corp シリコン基板のドライエッチング方法
JP2000195830A (ja) * 1998-12-28 2000-07-14 Mitsubishi Electric Corp 半導体製造装置、半導体製造装置のクリ―ニング方法、半導体装置の製造方法及び半導体装置
EP1098189A2 (fr) * 1999-11-05 2001-05-09 Axcelis Technologies, Inc. Méthode de détection du point d'achèvement d'un traitement par plasma en l'absence d'oxygène
JP2001135630A (ja) * 1999-11-10 2001-05-18 Matsushita Electronics Industry Corp 半導体装置の製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11214356A (ja) * 1998-01-29 1999-08-06 Sony Corp シリコン基板のドライエッチング方法
JP2000195830A (ja) * 1998-12-28 2000-07-14 Mitsubishi Electric Corp 半導体製造装置、半導体製造装置のクリ―ニング方法、半導体装置の製造方法及び半導体装置
EP1098189A2 (fr) * 1999-11-05 2001-05-09 Axcelis Technologies, Inc. Méthode de détection du point d'achèvement d'un traitement par plasma en l'absence d'oxygène
JP2001135630A (ja) * 1999-11-10 2001-05-18 Matsushita Electronics Industry Corp 半導体装置の製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100352014C (zh) * 2004-06-08 2007-11-28 东京毅力科创株式会社 蚀刻方法

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JP4326746B2 (ja) 2009-09-09
TW200306625A (en) 2003-11-16
AU2002359950A1 (en) 2003-07-24
JP2003264170A (ja) 2003-09-19

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