Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
  • H04N25/70—SSIS architectures; Circuits associated therewith
  • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
  • H04N25/767—Horizontal readout lines, multiplexers or registers
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
  • H04N25/70—SSIS architectures; Circuits associated therewith
  • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
  • H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

Definitions

• the present invention relates to imaging systems. More specifically, the
• present invention is related to an architecture for high speed analog to digital conversion
• FIG. 1 is an illustration of a CMOS active pixel sensor (APS) imaging system
• the system 100 includes a pixel array 110, shown in Fig. 3 as including a row
• system 100 is a color system, the pixels P would be made sensitive to the
• alternating rows are comprised of alternating green and red pixels and alternating
• Fig. 2 illustrates one exemplary architecture for a pixel P.
• the pixel P includes
• photodiode 210 which converts optical energy into an electrical signal.
• the photodiode 210 is coupled to node-A, which is also coupled to a
• the transistor 220 has another source/drain terminal of transistor 220.
• the transistor 220 has another source/drain
• Node -A is coupled to the gate of a source following transistor 230, which has one
• source/drain terminal coupled to the Ndd potential source and another source/drain
• 240 has its gate coupled to a ROW control signal, and its other source/drain terminal
• the pixel P produces a voltage at node-A related to the brightness of the light
• transistor 230 is coupled to the output line 250 at node-B.
• the output line 250 is also
• pixels including those which utilize, for example, reset transistors and output a
• differential signal comprising a photo signal component and a reset signal component.
• a block 130 for further processing in the digital domain (e.g., color interpolation) and storage.
• a block 130 for further processing in the digital domain (e.g., color interpolation) and storage.
• control circuit 140 coordinates the activities of the pixel array 110, analog processing and
• FIG. 3 is a more detailed diagram of the pixel array 110 and the analog
• the pixel array 110 includes an array 111
• the row decoder 112 receives a row address from, for
• the row decoder 112 decodes the row
• Each analog processing and digitizing circuit 120b, 120t is contain a plurality
• sample-and-hold circuits 121 and an analog-to-digital converters 123.
• sample-and-hold circuits 121 in the bottom circuit 120b are
• sample-and-hold circuit 121 is also coupled to signal line 122b (for bottom circuit 120b)
• control signal SHEb and SHEt determines when the sample-and-hold circuits
• Each sample-and-hold circuit 121 is associated with a corresponding analog-
• Each analog-to-digital converter 123 accepts as its input, the
• signal line 124b accepts, on signal line 124b (for bottom circuit 120b) or signal line 124t (for top
• top circuits 120b to sample-and-hold their corresponding pixels signals.
• analog-to-digital converters 124 the analog-to-digital converters 124.
• pixels are converted into a digital signal.
• the ADEb and ADEt signals then go back low.
• each pixel P in the array 110 has been processed and the process may be
• the present invention is directed to a high speed architecture for performing
• the pixel array is
• top and bottom analog processing and digitization circuits associated with a top and bottom analog processing and digitization circuits.
• bottom circuits are each coupled to both even and odd pixels.
• FIG. 1 is a block diagram of a prior art image processing system
• FIG. 2 is a block diagram of a prior art pixel for using in the image processing
• FIG. 3 is a detailed block diagram of the pixel array and the bottom and top
• FIG. 4 is a timing diagram showing the operation of the apparatus illustrated
• FIG. 5 is a block diagram of an image processing system according to the
• FIG. 6 is a block diagram of a pixel array and analog processing
• FIG. 7 is a timing diagram showing the operation of the apparatus illustrated
• FIG. 8 is a detailed block diagram of a holographic storage device using the
• FIG. 5 an portion of an imaging system 500 incorporating the
• the imaging system includes a modified pixel array
• circuits 120a', 120b' While the description of the invention uses terms such as “top” and
• the imaging system also includes a
• digital processing and storage system 130 As with imaging system 100 of Fig. 1, the pixels
• analog processing and digitizing circuits 120a', 120b' and further processed and stored in
• 120a' 120b' are coupled to the digital processing and storage system via data bus 181.
• a controller 140 is coupled to the analog processing and digitizing circuits 120a',
• a single bus may be used to carry both data and control
• control and/or data signals may be routed by point-to-point links as
• the sample-and-hold circuits 121 are each coupled to an output line 250
• circuits 121 of both analog processing and digitizing circuits 120a', 120b' are coupled to
• Each column also has a sample-
• Each sample-and-hold circuit 121 is also coupled to
• control signals SHEa, SHEb determines when
• the sample-and-hold circuit 121 samples-and-holds its input signal.
• Each analog-to-digital converter 123 accepts as its input, the
• Each analog- to-digital converter 123 Each analog- to-digital converter 123
• the other signal lines 260 are also set to a low logical state. This is reflected
• the SHEa signal which was low, is also driven high.
• the SHEb signal is also driven high.
• circuit 140 sends a new row address to the row decoder 112.
• the APEa and SHEb signals are driven high.
• circuit 140 sends another row address to the row decoder 112.
• control signals SHEa and ADEb are both driven high. This causes the sample-and-
• circuit 140 sends another row to the row address decoder 112.
• Control signals APEa and SHEb are both driven high, thereby permitting the
• processing and digitization circuits 120a', 120b' to become capable of receiving signals
• Processing throughput is doubled by using one of the
• Fig. 8 is an
• the holographic memory system 800 includes a laser
• the reference beam is focused using
• controllable optics path 802 to form a focused beam R', which illuminates a holographic
• the holographic recording medium in response to the focused
• a controller 805 coordinates the operation of the laser 801, controllable optics 802, positioning of the holographic recording medium 803,
• FIG. 9 is an illustration of a modified analog processing and digitizing
• circuit 120a The modified circuit 120a, which is designed to be operated in
• circuit 120b' now utilizes
• the original circuits 121, 123 are respectively controlled by control
• control signals SHEa2 and ADEa2 are controlled by control signals SHEa2 and ADEa2.
• the row decoder is operated at double speed and
• the two sets of circuits 121, 123 are operated in an interleaved fashion. In this manner, the
• speed of the imaging system may be doubled, or further increased (based on the degree of

Landscapes

• Engineering & Computer Science (AREA)
• Multimedia (AREA)
• Signal Processing (AREA)
• Transforming Light Signals Into Electric Signals (AREA)
• Analogue/Digital Conversion (AREA)
• Solid State Image Pick-Up Elements (AREA)

Priority Applications (3)

Applications Claiming Priority (2)

Publications (2)

Family

ID=23214451

Family Applications (1)

Country Status (6)

Cited By (2)

Families Citing this family (52)

Family Cites Families (24)

• 2002
  • 2002-08-16 WO PCT/US2002/026061 patent/WO2003017648A2/en not_active Ceased
  • 2002-08-16 CN CNB028202902A patent/CN1252987C/zh not_active Expired - Lifetime
  • 2002-08-16 CN CNB2005101085614A patent/CN100480897C/zh not_active Expired - Lifetime
  • 2002-08-16 EP EP02761388A patent/EP1428380A2/en not_active Withdrawn
  • 2002-08-16 US US10/219,771 patent/US7565033B2/en not_active Expired - Lifetime
  • 2002-08-16 JP JP2003521608A patent/JP4532899B2/ja not_active Expired - Fee Related
  • 2002-08-16 KR KR1020047002359A patent/KR100886308B1/ko not_active Expired - Lifetime
• 2007
  • 2007-01-31 JP JP2007021698A patent/JP4521411B2/ja not_active Expired - Fee Related

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