Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P50/00—Etching of wafers, substrates or parts of devices
  • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
  • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
  • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
  • H10W10/01—Manufacture or treatment
  • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
  • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
  • H10W10/0143—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations comprising concurrently refilling multiple trenches having different shapes or dimensions
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
  • H10W10/10—Isolation regions comprising dielectric materials
  • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10S438/00—Semiconductor device manufacturing: process
  • Y10S438/978—Semiconductor device manufacturing: process forming tapered edges on substrate or adjacent layers

Definitions

• the present invention relates to a dry etching method for manufacturing a semiconductor device, and more particularly to a dry etching method for etching a single crystal silicon in a shallow trench isolation (STI) to form a groove (trench) having a desired shape.
• STI shallow trench isolation
• SiI shallow trench isolation
• Steps of the STI is, the S i of the silicon substrate, digging Therefore groove dry etching (g wrench), the insulating material in the groove such as S i 0 2 crowded filled due CVD, last example This is the step of flattening by CMP.
• Such an STI requires a trench etching step for forming a trench (trench) in single-crystal silicon by anisotropic etching.
• a silicon substrate made of Si is used prior to this trench etching step.
• a thermal oxidation film such as an oxide Kei element (S i 0 2) to the surface, for example Shirikon'na form a Lee tri-de (S i N) film, a registry pattern is formed by the Photo lithography technique commonly used, it The SiN film and the thermal oxide film are patterned as a mask.
• the SiON film and the thermal oxide film are removed. Then, a trench etching step of anisotropically etching the opening of the mask by dry etching is performed.
• Such trench etching process conventionally, C 1 2, C 1 2 0 2 mixed-gas, a mixed gas of C 1 2 and HB r, mixed gas of C l 2 and HB r and 0 2, etc. It is performed by plasma etching or the like used as an etching gas.
• the side wall of the groove is often formed in a tapered shape having a predetermined angle that gradually widens from the groove bottom toward the upper opening.
• the side wall shape of the groove tends to change, for example, even within a single wafer, due to differences in the position of the center portion and the periphery, differences in the width of the groove, and the like. There is a problem that it is difficult to obtain a desired shape.
• miniaturization of various elements formed on a silicon substrate has been cited as one of the technical requirements.
• the etching process in the STI process as described above is performed, the etched area is reduced, so that the processed portion on the silicon substrate is easily sharpened and formed for element isolation.
• the groove also has a smaller frontage, making it difficult to embed an insulator in the groove. For this reason, as the miniaturization of various devices progresses, the shape of the groove in which an insulator can be easily embedded is required.
• the shape of the groove easy to embed an insulator, the efficiency of isolation is increased, and the leakage current and the stress after embedding can be reduced.
• the shape of such a groove is, for example, the bottom of the groove. It is preferable that the shape is as sharp as possible and rounded. It is also preferable that the boundary between Si and the mask of the SiN film and the thermal oxide film on the side wall of the groove is round.
• an object of the present invention is to provide a dry etching method that can form a groove having a desired shape of the side wall of the groove even when the width of the groove is different, and that can form a groove that is easy to embed an insulator.
• the present invention relates to a dry etching method for forming a groove of a desired shape in a silicon single crystal via a mask layer, wherein a substrate is arranged on one of a pair of counter electrodes provided in an etching chamber.
• An etching gas is introduced into the etching chamber by using an apparatus that supplies high-frequency power to both of the counter electrodes and performs etching by plasma, and supplies high-frequency power to be applied to the counter electrode on the side where the substrate is disposed.
• an apparatus that supplies high-frequency power to both of the counter electrodes and performs etching by plasma, and supplies high-frequency power to be applied to the counter electrode on the side where the substrate is disposed.
• the side wall shape of the groove is controlled.
• the present invention is characterized in that the etching gas is a mixed gas of a gas containing at least C1 and a gas containing Br.
• the present invention the gas including a C 1, characterized in that a C 1 2.
• the present invention is characterized in that the gas containing Br is HBr.
• the present invention is characterized in that the etching gas contains oxygen. Further, the present invention is characterized in that a total flow rate of the etching gas is adjusted to control a side wall shape of the groove.
• the present invention is characterized in that the amount of Cl 2 in the etching gas is adjusted to control the shape of the side wall of the groove.
• the present invention is characterized in that the high-frequency power applied to the counter electrode on the side where the substrate is disposed is in a range of 0.157 to 1.57 W / cm2.
• the present invention is characterized in that a plurality of types of the grooves having different groove widths are formed in the substrate.
• the present invention also provides a dry etching method for forming a groove on a silicon substrate by introducing a processing gas into an airtight processing chamber and performing a plasma process on silicon of the silicon substrate.
• the first step may be configured so that at least the pressure in the processing chamber is 6.7 Pa (50 mTorr) or less, and the ratio of the flow rate of HBr to the flow rate of N 2 of the processing gas is 3 or more.
• the plasma processing is performed under the condition that a high frequency power for bias applied to an electrode provided in the processing chamber to generate plasma is set to 100 W or more.
• the present invention the third step, with the pressure in the processing chamber 20 P a (1 50 mTorr) or less, the flow rate ratio of HB r against the C 1 2 of the flow rate of the processing gas 2 or more,
• the high frequency power for bias applied to the electrode provided in the processing chamber to generate plasma is set to 50 W or more. It is characterized in that plasma treatment is performed depending on conditions.
• the present invention is characterized in that the time for performing the plasma processing in the first step is shorter than the time for performing the plasma processing in the second step.
• the plasma processing is performed for a time of 0.15 to 0.5 with respect to the time. Is performed.
• the present invention is characterized in that the time for performing the plasma processing in the third step is shorter than the time for performing the plasma processing in the second step.
• the plasma treatment is performed for a time of 0.3 to 0.7 with respect to the time. Is performed.
• the present invention also provides a dry etching method for forming a groove on the silicon substrate by introducing a processing gas into an airtight processing chamber and performing a plasma process on the silicon on the silicon substrate. Prior to performing the step of forming the groove, performing an etching process for forming a round portion at a boundary portion between the etching mask and silicon on the side wall of the groove; and forming the groove in silicon of the silicon substrate. Performing an etching process for forming roundness at the bottom of the groove after performing the forming process.
• FIG. 1 is a diagram schematically showing a configuration of a cross section of a wafer for explaining an embodiment of the present invention.
• FIG. 2 is a diagram showing an example of the configuration of an apparatus used in an embodiment of the present invention.
• Fig. 3 is a graph showing the relationship between the lower power and the taper angle of a groove with a groove width of 0.24 ⁇ m.
• FIG. 4 is a graph showing the relationship between the lower power and the taper angle of a groove having a groove width of 1.00.
• FIG. 5 is a graph showing the relationship between the upper power and the taper angle of a groove having a groove width of 0.24 ⁇ m.
• FIG. 6 is a graph showing the relationship between the upper power and the taper angle of a groove having a groove width of 1.00 inch.
• Figure 7 is a graph showing the ratio of the relationship between the etching depth and the C 1 2.
• FIG. 8 is a graph showing the relationship between the taper angle and the ratio of C 12.
• Figure 9 is a graph showing the relationship between the etching depth and the total flow rate of the etching gas.
• FIG. 10 is a graph showing a relationship between a taper angle and a total flow rate of an etching gas.
• FIG. 11 is a diagram schematically showing a cross-sectional configuration of a wafer for explaining another embodiment of the present invention.
• FIG. 12 is a diagram schematically showing a part of a side wall of a groove when plasma processing is performed by a conventional main process.
• FIG. 13 is a diagram schematically showing a part of a side wall of a groove when plasma processing is performed in a pre-process (first process) and a main process (second process) in the embodiment.
• FIG. 14 is a diagram schematically showing a bottom portion of a groove when plasma processing is performed by a conventional main process.
• FIG. 15 is a diagram schematically showing a bottom portion of a groove when a plasma process is performed in a post-process (third process) after the main process (second process) in the embodiment.
• FIG. 1 schematically shows an enlarged vertical cross-section of a semiconductor wafer (silicon substrate) in order to explain one embodiment of the present invention.
• a silicon dioxide layer 102 having a thickness of, for example, about 9 nm and a nitride layer having a thickness of, for example, about 160 nm are formed on a semiconductor wafer (silicon substrate) 101.
• a silicon layer 103 is formed, and these are patterned into a predetermined shape so as to have an opening for forming a groove, thereby forming a so-called hard mask.
• a semiconductor wafer 1 0 1 made of single crystal silicon, at least as an etching gas and a C 1 2 and HB r Etching is performed by plasma etching using a gas containing gas, and grooves (trench) 104a and 104b are formed in the semiconductor wafer 101 as shown in FIG.
• the above-mentioned grooves 104a and 104b are formed to have predetermined widths, respectively.
• the width of the groove 104a shown on the left side in the figure is, for example, 0.24 / zm, and the right side in the figure.
• the width of the groove 104b shown in FIG. 7 is, for example, 1.00 m, and the width is different.
• the side walls 105a, 105b of these grooves 104a, 104b are formed to have substantially the same taper angle, and the depths are also formed to be substantially the same.
• FIG. 2 schematically shows an example of a configuration of a plasma processing apparatus used in the embodiment of the present invention.
• the plasma processing apparatus 1 is configured as a capacitively-coupled parallel plate etching apparatus in which electrode plates are vertically opposed to each other, and a high-frequency power source is connected to both of them.
• the etching apparatus 1 includes a chamber formed into a cylindrical shape made of aluminum whose surface is anodized (anodized), for example. 2 and this chamber 1 is grounded.
• a substantially cylindrical susceptor support 4 for mounting the wafer W thereon is provided at the bottom of the chamber 12 via an insulating plate 3 such as a ceramic.
• the susceptor evening support 4 includes a high-pass filter one is the susceptor evening 5 is (is this susceptor evening 5 provided with a lower electrode (HPF) 6 is connected (susceptor evening support 4
• a temperature control medium chamber 7 In this temperature control medium chamber 7, a temperature control medium is introduced and circulated through an inlet pipe 8, and is discharged from a discharge pipe 9 to be susceptible.
• the susceptor 5 is controlled to a desired temperature
• the susceptor 5 has an upper central part formed into a convex disk shape, and an electrostatic chuck 11 having substantially the same shape as the wafer W is provided thereon.
• the electrostatic chuck 11 has a structure in which an electrode 12 is interposed between insulating materials, and a DC power supply 13 connected to the electrode 12 has a DC voltage of, for example, 1.5 kV.
• a voltage is applied, the wafer W is electrostatically attracted by Coulomb force.
• a gas passage 14 for supplying a heat transfer medium, such as He gas is formed on the back surface of the wafer W to be processed. Then, heat is transferred between the susceptor 5 and the wafer W via the heat transfer medium, and the wafer W is maintained at a predetermined temperature.
• An annular focus ring 15 is arranged around the upper edge of the susceptor 5 so as to surround the wafer W placed on the electrostatic chuck 11.
• the focus ring 15 is made of an insulating material such as ceramics or quartz, and improves the uniformity of etching.
• An upper electrode 21 is provided above the susceptor 5 so as to face the susceptor 5 in parallel.
• the upper electrode 21 is supported inside the chamber 12 via an insulating material 22.
• the upper electrode 21 is composed of an electrode plate 24 (for example, made of quartz) having a large number of discharge holes 23 and an electrode plate 24. And a supporting electrode support 25 (conductive material, for example, aluminum whose surface is anodized). The distance between the susceptor 5 and the upper electrode 21 is adjustable.
• a gas inlet 26 is provided at the center of the electrode support 25 in the upper electrode 21.
• a gas supply pipe 27 is connected to the gas inlet 26.
• a processing gas supply unit 30 is connected to the gas supply pipe 27 via a valve 28 and a mass flow controller 29. Then, an etching gas for plasma etching is supplied from the processing gas supply unit 30.
• FIG. 2 shows only one processing gas supply system including the processing gas supply unit 30 described above, but a plurality of these processing gas supply systems are provided. , Cl 2 , O 2 , N 2, and the like can be supplied to the inside of the chamber 12 by independently controlling the flow rate thereof.
• an exhaust pipe 31 is connected to the bottom of the chamber 12, and an exhaust device 35 is connected to the exhaust pipe 31.
• the evacuation device 35 is provided with a vacuum pump such as a turbo molecular pump, which can evacuate the chamber 2 to a predetermined reduced pressure atmosphere, for example, a predetermined pressure of 1 Pa (7.5 mTorr) or less. It is configured as follows.
• a gate valve 32 is provided on a side wall of the chamber 12. Then, with the gate valve 32 opened, the wafer W is transferred between the chamber 12 and an adjacent load lock chamber (not shown).
• a first high-frequency power supply 40 is connected to the upper electrode 21, and a matching box 41 is interposed in the power supply line. Further, a mouth-to-pass filter (LPF) 42 is connected to the upper electrode 21.
• the first high-frequency power supply 40 has a frequency in the range of 50 to 150 MHz. By applying such a high frequency, a favorable dissociation state is obtained in the chamber 12. In addition, high-density plasma can be formed, and plasma processing can be performed under lower pressure conditions than before.
• the frequency of the first high-frequency power supply 40 is preferably 50 to 80 MHz, and typically the frequency shown in FIG.
• a second high-frequency power supply 50 is connected to the susceptor 5 as a lower electrode, and a matching device 51 is interposed in the power supply line.
• the second high-frequency power supply 50 has a frequency in the range of several hundred to several tens of MHz. By applying a frequency in such a range, an appropriate ion action can be given to the wafer W to be processed without damaging the wafer W.
• a frequency such as 13.56 MHz or 800 kHz is typically employed.
• the wafer W on which the mask layer including the silicon dioxide layer 102 and the silicon nitride layer 103 is formed is opened into the chamber 12 from the load lock chamber (not shown) by opening the gate valve 32. And place it on the electrostatic chuck 11. Then, by applying a DC voltage from the high-voltage DC power supply 13, the wafer W is electrostatically attracted onto the electrostatic chuck 11. Then, the gate valve 32 is closed, and the inside of the chamber 2 is predetermined by the exhaust device 35. Vacuum to a vacuum of Thereafter, the the valve 28 is opened. Processing gas supply unit 30 from the etching gas for the main etch (eg.
• HB r and C l 2, or HB r and C l 2 0 2) by a mass flow con preparative roller 29 While adjusting the flow rate, through the processing gas supply pipe 27, the gas inlet 26, the hollow part of the upper electrode 21, and the discharge hole 23 of the electrode plate 24-as shown by the arrow in FIG. To be discharged.
• the pressure in the chamber 12 is maintained at a predetermined pressure, for example, a pressure of about 13 Pa (100 mTorr).
• a high-frequency voltage is applied from the first high-frequency power supply 40 and the second high-frequency power supply 50 to the susceptor 5 serving as the upper electrode 21 and the lower electrode, and the etching gas is turned into plasma, thereby forming a wafer W. Perform etching.
• the graphs in FIGS. 3 and 4 are the second power in the etching of an 8-inch diameter wafer W using the etching apparatus 1 described above.
• Fig. 3 shows the relationship between the power supplied from the high-frequency power source 50 to the susceptor 5 as the lower electrode and the taper angle of the side wall of the groove. Indicates the case where the groove width is 1.0 ⁇ m.
• solid lines A and C indicate the central portion of the wafer W
• dotted lines B and D indicate the taper angles of the grooves in the peripheral portion of the wafer W.
• FIGS. 5 and 6 show the graphs in FIGS. 5 and 6 (vertical axis is the taper angle, horizontal axis is the upper power (power supplied to the upper electrode)) are obtained by etching the 8-inch wafer W using the etching apparatus 1 described above.
• Fig. 5 shows the relationship between the power supplied from the high-frequency power supply 40 to the upper electrode 21 and the taper angle of the side wall of the groove, and Fig. 5 shows the case where the groove width is 0.24 ⁇ m. The figure shows the case where the groove width is 1.0 ⁇ m.
• solid lines E and G indicate the central portion of the wafer W
• dotted lines F: H indicate the taper angles in the grooves in the peripheral portion of the wafer W.
• the power is set to about 500 W at the maximum. Also, if the value is much lower than the above-mentioned 100 W and becomes less than 50 W, the etching rate is reduced, so the lower power is about 50 to 500 W for an 8-inch diameter wafer. Therefore, the electric power per unit area is preferably in the range of 0.157 to 1.57 W / cm 2 .
• the graph in Figure 7 (the vertical axis is the etching depth (therefore, the etching speed is substantially Degrees), the horizontal axis represents C 1 2 ratio in the etching gas (C 1 2 flow rate / total flow)), in the etch ing of the wafer W 8 Inchi diameter using the etching apparatus 1, the etching depth and C shows a second ratio relationship, the solid line I is, when the groove width is 0.5 24 ⁇ M, dotted J is, the groove width indicates a case 1. 00 ⁇ M.
• a graph (ordinate taper angle, the horizontal axis represents C 1 2 ratio (C 1 2 flow rate / total flow rate of the etching gas)) in FIG. 8, a wafer of 8-inch diameter, which had use of the etching apparatus 1 in the etching of W, shows the relationship between the ratio of the taper angle and C 1 2, a solid line K is, in the case of groove width 0.5 24 ⁇ M, dotted when L groove width of 1. 0 0 / m Is shown.
• Etching gas C 12 + ⁇ ⁇ (total flow 200 SCCM)
• He pressure He pressure / sensor: 400/400 Pa (3 Torr)
• the taper angle changes when the groove width is 0.24 ⁇ m (solid line) and when the groove width is 1. In the case of 00 m (dotted line L), it is not uniform.
• the groove width is wide groove, different Te
• the angle will be one angle.
• the graph of FIG. 9 (the vertical axis is the etching depth (and therefore substantially the etching rate), and the horizontal axis is the total flow rate of the etching gas) is shown in the etching of the 8-inch diameter wafer W using the etching apparatus 1 described above.
• the solid line M shows the relationship between the etching depth and the total flow rate of the etching gas.
• the solid line M shows the case where the groove width is 0.24 ⁇ m
• the dotted line N shows the case where the groove width is 1.00 ⁇ m. I have.
• the graph of FIG. 9 (the vertical axis is the etching depth (and therefore substantially the etching rate), and the horizontal axis is the total flow rate of the etching gas) is shown in the etching of the 8-inch diameter wafer W using the etching apparatus 1 described above.
• the solid line M shows the relationship between the etching depth and the total flow rate of the etching gas.
• the solid line M shows the case where the groove width
• FIG. 10 (vertical axis is the taper angle, horizontal axis is the total flow of the etching gas) shows the taper angle and the etching gas in the etching of the 8-inch diameter wafer W using the etching apparatus 1.
• the solid line 0 indicates the case where the groove width is 0.24 / ⁇ 1
• the dotted line P indicates the case where the groove width is 1.00 m.
• High frequency power applied to upper electrode 1 000 W
• High frequency power applied to lower electrode 200 W
• the etching rate changes and the taper angle also changes. Furthermore, as shown in the graph of Fig. 10, the change in the taper angle is as follows when the groove width is 0.24 ⁇ m (solid line K) and when the groove width is 1.0m (dotted line). Then it is not uniform.
• the total flow rate of the etching gas, with C 1 2 amount (ratio) or the like in the etching gas, by adjusting the lower power is grooves of different groove width coexist Even in such a case, the shape of the side wall of these grooves can be a predetermined shape so as to have a desired taper angle. Therefore, it is possible to satisfactorily embed the dielectric material thereafter, and to satisfactorily perform element isolation by STI.
• the illustrated example shows a step of forming a groove for embedding an insulator such as SiO 2 for element isolation in the STI step.
• a thermal oxide film 204 such as silicon oxide (Si0 2 ) of about 1 O nm and a silicon nitride (Si) are formed on the surface of a silicon substrate 202 made of Si.
• An SiN) film 206 is formed, a resist pattern is formed by a commonly used photolithography technique, and the SiN film 206 and the thermal oxide film 204 are patterned using the resist pattern as a mask. Then, the remaining photoresist layer is asked to remove the resist pattern.
• the opening is anisotropically etched by dry etching using the SiN film 206 and the thermal oxide film 204 as a mask to form a trench for burying an insulator for element isolation.
• a boundary portion between the mask and Si on the sidewall of the groove is provided.
• Perform post-process (third step) is performed.
• the above pre-process is to S i N film 206 and the thermal oxide film 204 is a mask, to etch the S i by plasma treatment in the process gas comprising a mixed gas containing HB r and N 2.
• At least the pressure in the chamber 12 depends on the etching.
• a reaction product (depot) is easily formed and a round shape is easily formed, specifically, 6.7 Pa (50 mTorr) or less, more preferably 2.7 Pa (20 mTorr) from a practical viewpoint. or more and 6.
• the high-frequency power for the bias applied to the susceptor 5 as the lower electrode is such that it does not etch stop, specifically 100 W or more, preferably 150 W or more, and more preferably 200 W Thus, it is preferable to perform the plasma processing.
• etching is performed by plasma processing in the main process.
• Si is anisotropically etched.
• the etching conditions in this case are the same as in the conventional case.
• the pressure inside the chamber 12 is 2.7 Pa (20 mTorr), and the high frequency applied to the upper electrode 21 is high.
• power 6 0 0 W, the high-frequency power 2 0 W applied to the let-flop evening 5 as a lower electrode, spacing 1 1 5 mm between the upper electrode 2 1 a susceptor evening 5, process gas C 1 2 0 2 gas flow rate ratio of (C 1 2 gas flow rate / 0 2 gas flow rate) is set to 1 6 8 sccm / 3 2 sccm , Chiya for setting the temperature of members in the 2 susceptor evening 5 4 0 ° C, the upper electrode 21 is 80 ° C and the side wall is 60 ° C.
• FIG. 11 When etching is performed by such a main process of plasma processing, FIG. 11
• the bottom portion 214 of the groove 210 is dug deeper, and a round portion (round) remains at the boundary portion 212 between the mask and Si on the side wall of the groove 210.
• the taper angle of the groove 210 can be controlled by setting conditions as in the above-described embodiment.
• etching is performed by a plasma process in a later step.
• This post-process is performed to round the bottom portion 214 of the groove 210 because the bottom portion of the groove is still sharp even after the etching in the pre-process and the main process.
• the pressure in the chamber 12 should be at least such that a large amount of depot can easily generate a round, specifically, 20 Pa (150 mTorr) or more.
• the high-frequency power for the bias applied to the susceptor 5 as the lower electrode is preferably plasma-treated at a level that does not cause an etch stop, specifically, 50 W or more.
• the conjunction is further dug bottom portion of the groove 2 1 0, the bottom part 2 1 4 grooves 2 1 0 dug with its rounded (Round) is formed (thus, The shape of the groove 210 in which the insulator is easily buried in Si of the silicon substrate is formed.
• the plasma processing in the pre-process and the post-process is performed for a shorter time than the plasma processing in the main process.
• plasma processing in the main process Assuming that the time for applying is 1, the plasma processing in the preceding step is performed for a time of 0.15 to 0.5, and the plasma processing in the subsequent step is performed for a time of 0.3 to 0.7.
• the pre-process is performed for about 5 to 15 seconds
• the post-process is performed for 10 to 20 seconds.
• Si can be dug in the pre-process only to the extent that roundness (round) is formed at the boundary portion 212 between the mask and Si on the side wall of the groove 210, and in the post-process, the groove 2 Si can be dug to such an extent that roundness is formed in the bottom part 2 14 of 10.
• the shape of the groove formed by the etching process according to the present invention will be described in comparison with the conventional case.
• the shapes of the sidewalls of the groove when the etching is actually performed only in the conventional main process and when the etching is performed in the previous process and the main process are shown in FIGS. 12 and 13, respectively.
• Figure 1 2 is a conventional main step, using a Ru process gas name from a mixed gas containing C 1 2 0 2, the pressure in the chamber one 2 2.
• 7 P a (2 0 mTorr) an upper electrode 21 High-frequency power applied to 1 is 60 OW, high-frequency power applied to susceptor 5 as lower electrode is 200 W, interval between upper electrode 21 and susceptor 5 is 115 mm, process gas C 1 2 0 2 gas flow rate ratio (C 1 2 gas flow rate / O 2 gas flow rate) is set to 1 6 8 sccm / 3 2 sccm , susceptor evening 5 4 0 ° for setting the temperature in Chang bars 2 C, the plasma treatment was performed under the conditions that the upper electrode 21 was at 80 ° C and the side wall was at 60 ° C.
• FIG. 13 shows a case where the etching in the pre-process and the main process according to the present invention was performed.
• the pressure in the chamber 12 was set to 2.7 Pa (20 mTorr), and the upper electrode 2 was formed.
• the high-frequency power applied to 1 is 700 W, 3 0 0 W RF power applied to the susceptor evening 5 as a lower electrode, spacing 1 1 5 mm between the upper electrodes 2 1 and susceptor evening 5, process gas HB r and N 2 gas flow rate ratio (the HB r Gas flow rate / gas flow rate of N 2 ) was set to 300 sccm / 100 O sccm.
• the temperature of the susceptor 5 was 50 ° C
• the upper electrode 21 was 60 ° C
• the side wall was set.
• the plasma treatment was performed only for a short time of about 5 to 15 seconds under the condition that the temperature of the part was 60 ° C.
• the main process is a process in which plasma treatment is performed for about 30 seconds under the same conditions as the above.
• Figures 14 and 15 show the shapes of the bottom of the groove when the etching is actually performed only in the conventional main process and when the etching is performed in the later process.
• FIG. 14 shows the shape of the bottom portion 314 of the groove 310 formed by performing etching in the main process under the same conditions as in FIG.
• FIG. 15 shows the result of performing the same main process as in FIG. 13 and then performing the etching in the post-process according to the present invention.
• the pressure inside the chamber 12 is 20 Pa (150 mTorr)
• the high-frequency power applied to the upper electrode 21 is 500 W
• the susceptor 5 is used as the lower electrode.
• the flow rate is 2 25 sccm / 75 sccm
• the set temperature inside the chamber 1 is about 10 to 20 seconds depending on the conditions of 40 ° C for the susceptor 5, 80 ° C for the upper electrode 21 and 60 ° C for the side wall. For a short time.
• the groove 2 1 0 embedding an insulating material, for example, film formation, such as S i 0 2, the film forming the groove 2 1 0 Since the layers are stacked one by one on the surface of the structure, there is a disadvantage that when the layers are combined, a stress is generated or a nest (void) is formed, resulting in a leak current.
• the etching method according to the present invention since the formed groove 210 is rounded and has no sharp portion, the insulator can be easily embedded. In other words, the efficiency of the isolation increases, and the leakage current and the stress after embedding are less likely to be applied.
• the etching by the main process (second process) is performed.
• the shape of the groove 210 is different from that of the mask on the side wall of the groove 210.
• Boundary part with Si upper part of the side surface of groove 210)
• a round shape is formed in 2 12 and a round part is formed in bottom part 214 of groove 210, and there is no sharp part Can be
• the groove 210 having such a shape can be formed, the efficiency of isolation is increased, and the leakage current ⁇ ⁇ ⁇ the stress after embedding can be reduced. Thereby, further miniaturization of various elements can be achieved.
• the present invention is not necessarily limited to this.
• the present invention may be applied to a plasma etching apparatus that applies high-frequency power only to the lower electrode.
• the dry etching method according to the present invention can be used in the semiconductor manufacturing industry for manufacturing semiconductor devices. Therefore, it has industrial applicability.

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• 2002
  • 2002-06-07 KR KR1020067004635A patent/KR100702723B1/ko not_active Expired - Fee Related
  • 2002-06-07 WO PCT/JP2002/005636 patent/WO2003001577A1/ja not_active Ceased
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