WO2001021411A1 - Circuit integre pilote et tete d'impression optique - Google Patents

Circuit integre pilote et tete d'impression optique Download PDF

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Publication number
WO2001021411A1
WO2001021411A1 PCT/JP2000/006333 JP0006333W WO0121411A1 WO 2001021411 A1 WO2001021411 A1 WO 2001021411A1 JP 0006333 W JP0006333 W JP 0006333W WO 0121411 A1 WO0121411 A1 WO 0121411A1
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WO
WIPO (PCT)
Prior art keywords
light emitting
driving
data
circuit
units
Prior art date
Application number
PCT/JP2000/006333
Other languages
English (en)
Japanese (ja)
Inventor
Mitsuhiro Omae
Original Assignee
Sanyo Electric Co., Ltd.
Tottori Sanyo Electric Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP26590499A external-priority patent/JP2001088345A/ja
Application filed by Sanyo Electric Co., Ltd., Tottori Sanyo Electric Co., Ltd. filed Critical Sanyo Electric Co., Ltd.
Priority to EP00961037A priority Critical patent/EP1215050A4/fr
Priority to US10/088,266 priority patent/US6853396B1/en
Publication of WO2001021411A1 publication Critical patent/WO2001021411A1/fr
Priority to HK03101154.7A priority patent/HK1048968A1/zh

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Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/435—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of radiation to a printing material or impression-transfer material
    • B41J2/447—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of radiation to a printing material or impression-transfer material using arrays of radiation sources
    • B41J2/45—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of radiation to a printing material or impression-transfer material using arrays of radiation sources using light-emitting diode [LED] or laser arrays

Definitions

  • the present invention relates to an optical printhead used for a recording head such as a printer, and in particular, drives a light-emitting element configured to be able to perform time-division driving within the element.
  • a light emitting element (array) used in a conventional optical print head has individual electrodes corresponding to a plurality of light emitting parts on a one-to-one basis. Since it is provided on the front side of the element and a common electrode for each light emitting section is provided on the back side of the element, it was not possible to perform time-division driving within one element. Since it is not possible to perform time-division driving, it is necessary to provide the same number of individual electrodes as the number of light-emitting parts. There was a problem that it became difficult to connect.
  • Japanese Patent Application Laid-Open No. 6-163980 proposes a light emitting device capable of time-division driving within the device. That is, the plurality of light-emitting portions on the light-emitting element are divided into two or three groups p, and a plurality of common electrodes are provided so as to be connected to the light-emitting portions of each group, and connected to p light-emitting portions belonging to different groups.
  • a light-emitting element having pXn light-emitting portions by providing n individual electrodes has been proposed. According to this light emitting element, the number of individual electrodes can be reduced to the conventional] P by selecting the p common electrodes in a time-division manner. Connection can be facilitated.
  • Such a light-emitting element can be driven in a time-division manner using the same drive IC as before, but in this case, a separate drive circuit is required to select the common electrode in a time-division manner. Therefore, development of a versatile driving IC suitable for time-division driving is desired.
  • the present applicant has proposed a driving IC in consideration of the above points. 2 2 6 1 () Proposed in Japanese Patent Publication No. 2, but the configuration shown in this publication requires processing to change the data input order for time-division driving, which complicates data processing. There was a problem of becoming. Further, since the same number of driving ICs as light emitting elements is required, there is a problem that the number of driving ICs is large and expensive. Also, when this driving IC is applied to light emitting elements having different resolutions, there is a problem that data processing becomes complicated. Disclosure of the invention
  • An object of the present invention is to provide a versatile driving IC suitable for driving a light emitting element corresponding to time division driving. Another object of the present invention is to provide a driving IC capable of supporting a plurality of types of light emitting elements having different resolutions. Further, the present invention is, in the c present invention for the purpose that you provide a driving IC capable and this to input the data at high speed, optical purine Tohe' de is the n X p pieces of light emitting portion, It is provided with: n first electrodes connected to one terminal of the light emitting unit for every p units; and p second electrodes connected to the other terminal of the light emitting unit for every n units.
  • a driving TC device comprising: m second output terminals connected to the second electrode of the light emitting element; and q driving light emitting elements are provided for one driving IC device.
  • the number q of the light emitting elements provided, the number p of the second electrodes of the light emitting elements, and the number of the driving 1 C devices It is determined by the number m of the second output terminals.
  • the driving IC device having a first driving unit connected to the first output terminal, the first driving unit sequentially transmits the signals through r input terminals.
  • a data signal storage circuit for storing at least n X m data signals to be processed, a data selection circuit for selecting and taking out data signals stored in the data signal storage circuit in n units, And a driving circuit that outputs a driving signal to each of the first output terminals based on the data signal selected by the data selection circuit.
  • an optical print head comprising: a light emitting element having a plurality of light emitting portions; and a driving IC device for supplying a drive current to the light emitting portion of the light emitting device
  • a driving IC device for supplying a drive current to the light emitting portion of the light emitting device
  • one terminal of a plurality of light emitting units is connected to each of the n first electrodes
  • the driving TC device is connected to each of the first electrodes of the light emitting device.
  • a first drive unit that outputs the drive current from the first output terminal, and the first drive unit sequentially transmits the signal through r input terminals.
  • a data signal storage circuit for storing at least n X m data signals to be output, a data selection circuit for selecting and extracting the data signals stored in the data signal storage circuit in n units, Based on the data signal selected by the data selection circuit, the first output Are the earthenware pots by comprising a drive circuit for outputting a drive signal to the terminal.
  • FIG. 1 is a circuit block diagram of a driving IC according to the first and second embodiments of the present invention.
  • FIG. 2 is a circuit block diagram showing a main part of the first and second embodiments
  • FIG. 3 is a timing chart of the first and second embodiments
  • FIG. 4 is a plan view of a main part of the optical print head according to the first embodiment
  • FIG. 5 is a plan view showing a main part of the optical print head according to the first embodiment
  • FIG. 6 is a plan view showing a main part of the light emitting device according to the embodiment
  • FIG. 7 is a circuit block diagram of the optical printhead according to the first and second embodiments.
  • FIG. 8 is a plan view showing a main part of the optical print head according to the second embodiment.
  • FIG. 9 is a plan view showing a main part of the light emitting device according to the second embodiment.
  • FIG. 10 is a circuit block diagram of the driving IC according to the third embodiment
  • FIG. 11 is a circuit block diagram showing a main part of the driving IC of the same embodiment
  • FIG. 12 is a circuit diagram showing a main part (divided timing signal generation circuit) of the embodiment
  • FIG. 13 is a timing chart of the embodiment.
  • FIG. 14 is a plan view of a main part of the optical print head according to the embodiment
  • FIG. 15 is a circuit block diagram of the optical printhead according to the embodiment
  • FIG. 16 is a schematic configuration diagram schematically showing a characteristic portion of the embodiment.
  • FIG. 17 is a schematic configuration diagram schematically showing a characteristic portion when applied to a light-emitting element having a different form from the embodiment.
  • FIG. 18 is a schematic configuration diagram schematically showing a characteristic portion when applied to a light-emitting element having a different form from the embodiment.
  • FIG. 19 is a schematic configuration diagram schematically showing a characteristic portion when applied to a light-emitting element having a different form from the embodiment.
  • FIG. 20 is a schematic configuration diagram schematically showing a characteristic portion when applied to a light-emitting element having a different form from the embodiment.
  • FIG. 21 is a schematic configuration diagram schematically showing a characteristic portion when applied to a light emitting element having a different form from the embodiment.
  • FIG. 22 is a timing chart showing the operation of the optical printhead shown in FIG.
  • FIG. 23 is a timing chart showing the operation of the optical print head shown in FIG.
  • FIG. 24 is a timing chart showing the operation of the optical printhead of FIG. 20.
  • FIG. 25 is a timing chart showing the operation of the optical printhead of FIG.
  • FIG. 26 is a circuit block diagram showing a main part of the driving IC of the fourth embodiment, and FIG. 27 is a timing chart of the same embodiment.
  • FIG. 28 is a circuit diagram showing a main part (divided timing signal generation circuit) of the same embodiment.
  • FIG. 1 is a circuit block diagram showing a basic configuration of the driving ICs of the first and second embodiments. It is a lock diagram.
  • Fig. 2 shows the main part of the circuit block diagram extracted from the circuit block diagram shown in Fig. 1 focusing on the part related to one output terminal DO1 of the plurality of output terminals DO1 to DO48.
  • FIG. 1 a description will be given with reference to these figures.
  • the driving IC 1 has an individual terminal section DO composed of a plurality (n) of output terminals DO 1 to DO 48 for element driving (for individual electrodes 28 described later). , Connected to the output terminals DO ⁇ to D 8, and to which a predetermined current output as a drive signal is given: 1st drive unit 2, for group selection (for common electrodes 27 to be described later) ) Is connected to a common terminal section CD composed of a plurality of (m) output terminals CD1 to CD40, and to each of the output terminals CD1 to CD40.
  • a second drive unit 3 for switching to a ground potential VSS is provided.
  • the first drive unit 2 includes a data signal storage circuit 4 for temporarily storing a serial input data signal sequentially supplied from a data input terminal SI, and a data signal output from the data signal storage circuit 4.
  • a drive circuit 5 for outputting a drive signal to each of the output terminals DO 1 to D ⁇ 48, a current supply circuit 6 for supplying a constant current to the drive circuit 5, a first drive unit 2 and a second drive unit 3;
  • a timing control circuit 7 for supplying a predetermined timing signal to each section is provided.
  • the data signal storage circuit 4 captures the data signal serially input from the data input terminal ST in synchronization with the clock signal CLK1, and serially outputs the data signal from the data output terminal SO.
  • the shift register 8 in bit configuration and the data signal loaded in the shift register 8 are loaded in parallel based on the load signal LOAD1.
  • Switch circuit 9. The shift register 8 outputs n X m (192 0) data signals output in parallel so that they can be supplied to the storage circuit 1 () without passing through the latch circuit 9. ing.
  • the configuration of the shift register 8 and the latch circuit 9 can be changed accordingly.
  • the address of the shift register 8 can be specified. It may be configured with a memory of the system.
  • the drive circuit 5 receives n X m (1900) data signals output from the latch circuit 9. Then, a first selection circuit 11A for sequentially selecting and outputting data signals in units of n units, and a first! Selection circuit 1]
  • a first drive circuit 12A of n (48) -bit configuration that outputs a constant current through the output terminals DO1 to DO48 based on the output of A It has a simple configuration.
  • the drive circuit 5 stores correction data for storing n X m (192 O) correction data for correction of output current (light quantity) as necessary.
  • a second selection circuit 11B for data and an output of a current value increased or decreased based on the output of the selection circuit 11B for correction data are output through the output terminals DO: 1 to D ⁇ 48.
  • a second drive circuit 12B for correcting an n (48) -bit configuration output as a drive signal is provided.
  • the storage circuit 10 is configured to store, for example, SX n X so that ⁇ X m (1900) pieces of correction data composed of a plurality of (S) bits (for example, a 3-bit configuration) can be stored. It can be configured with an m-bit latch circuit. Then, writing of the correction data to each correction data storage circuit 10 is performed based on n ⁇ m units of signals supplied in parallel from the shift register 8.
  • Writing to the correction data storage circuit 10 can be performed in advance. That is, the operation of storing only each bit of the acquired data via the shift register 8 with only the memory circuit 1 () in the write state is repeated S times (three times).
  • a plurality of (four in this example) current amplifiers 12a to 12d with different current outputs for one output terminal DO1 are grouped as one set. Then, it is configured to have the same number (48 in this example) as the output terminals of the individual terminal section D ⁇ .
  • the four current amplifiers 12a to 12d which are supplied with current from the current supply circuit 6, individually control their working states, so that the total output current is 3 to 5 based on 4 mA. It can be changed in the range of about mA.
  • the selection circuit 11 selects n ⁇ m data and correction data stored in the latch circuit 9 and the correction data storage circuit 10 in order to perform time-division driving in units of n and takes m times.
  • This circuit is composed of multiple logic gate circuits.
  • This selection circuit 11 is a division timing signal that forms a part of the timing control circuit 7. The opening and closing of the gate is controlled by the generation circuit 14.
  • this division timing signal generation circuit 14 is provided with a small number (one in this example) of signal lines from the outside so as to regulate the time division timing.
  • a circuit for generating m types of divided timing signals DIV 1 to DIV 4 () based on the control signal DIVSEL supplied by the control circuit DIVSEL, for example, can be constituted by a counter.
  • Divided timing signal generation circuit] .4 outputs m kinds of divided timing signals DIV 1 to DIV 40 based on a control signal D ⁇ VSEL consisting of a binary number of a predetermined bit in addition to the counter.
  • the division timing generation circuit 14 can be configured by a decoder or the like that generates m (40 types) division timing signals based on one or a small number of control signals DTVSEL. (DIV 1 to DTV 40). That is, since the control signal DIVSEL is supplied using a smaller number of signal lines than the number of divided timing signals, the number of control signal terminals to be connected to the outside can be reduced to reduce the size of the IC. As much as possible, the number of external wires such as wire bond wires can be reduced.
  • the divided timing signal generation circuit 14 can be reset in synchronization with the input of a data signal for one line, and can be used in addition to the reset using the reset signal RESET.
  • the reset can be performed using the load signal LOAD 1.
  • One 1-C data (1900 ON / OFF data) stored in the latch circuit 9 is generated by sequentially switching the division timing signals DIV1 to DIV40 to the H level.
  • the divided timing signals D ⁇ ⁇ ⁇ ⁇ V 1 to DIV 40 and the 40 AND gate circuits in the first selection circuit ⁇ 1 A connected to the latch circuit 9 are sequentially opened one by one.
  • the three-bit correction data stored in the correction data storage circuit 10 is also selectively output through the opened AND gate circuit, and the divided timing signals DIV ⁇ to DIV 40 are sequentially output in the same manner.
  • a set of three AND gate circuits (composed of 40 sets in this example) in the second selection circuit 11B is opened, and as a result, the open set Selectively output through the AND gate circuit.
  • the output of the correction data storage circuit .10 is supplied to the drive circuit 12, where the data supplied from the latch circuit 9 through the first selection circuit 11A and the data In cooperation, the three current amplifiers 12b to 12d are selectively operated.
  • the second drive unit 3 is a circuit for selectively switching one of the output terminals CD1 to CD40 to the ground potential VSS, and is configured to be switched by the divided timing signals DIVL to DIV40. However, it is also possible to adopt a configuration in which the switching is performed using another signal synchronized with the division timing signals DIV to DIV40.
  • the driving IC 1 has terminals DO 1 to DO 48 arranged on one side, and terminals CD 1 to CD 40 arranged in half on two opposite sides, and the data are arranged. Terminals with similar functions are collected on one side by arranging the remaining terminals for power, clock, power supply, etc. on the other side. Terminals D 01 to D 048 are arranged at a density of around 150 DPI (DOT / INCH). This arrangement density is set based on a critical density of a fine wiring pattern formed on the substrate 21 described later. That is, since the wiring pattern density of the first and second wirings 23-1 and 23-2 formed on the substrate 21 is set to about 150 DPI, the density is almost the same as this value. It is set.
  • FIG. 4 is a schematic plan view of an essential part showing an optical print head 20 provided with the driving [C 1], _, and this optical print head 20 is:
  • the driving ICs 1 are arranged in a line.
  • the driving ⁇ C 1 is arranged at a ratio of one to the predetermined number q (5 in this example) of the light emitting elements 22, and the driving ⁇ C 1 and the corresponding q light emitting elements 2 2 are one. Create a block (b).
  • a wiring 23 is provided between the light emitting element 22 and the driving electrode C 1 to connect them.
  • Wiring 23 is a multiplex that connects one end to the output terminals D ⁇ 1 to D ⁇ 48 of the driving 1C1 and connects the other end to the individual electrodes of each light emitting element 22 in the same block.
  • One end is connected to the first wiring 23-1 and the output terminal CD 1 to CD 40 for group selection of the driving IC 1, and the other end is connected to each light emitting element 2 2 in the same block.
  • the second wiring 23-2 that is selectively connected to the common electrode of the second line.
  • the first wiring 2 3 — 1 is It is composed of a multiplex wiring pattern formed by multilayer wiring on the substrate 21, and wire bond wires connecting this pattern with the driving IC 1 and between the light emitting elements 22.
  • the second wiring 23-2 also comprises a wiring pattern formed by multi-layer wiring on the substrate 21 and a wire bond line connecting the pattern with the driving IC 1 and between the light emitting elements 22.
  • the wiring having the same length as the array length of the light emitting elements 22 of the first wiring 23-1 and the second wiring 23-2 wiring pattern is divided on both sides of the row of the light emitting elements 22. Are arranged separately. By doing so, wire bonding with a plurality of light emitting elements 22 described later can be easily performed.
  • the pattern of the wiring 23 divided on both sides of the row of the light-emitting elements 22 and separately arranged on the substrate 21 is the second wiring 23-2 rather than the first wiring 23-1.
  • the width of the pattern per wire and the space between them are wider for the second wiring 23-2, so the total width of the pattern on the second wiring 23-2 side is the first wiring 2 3 — wider than the 1 side.
  • the connection between the driving 1 C 1 and the light emitting element 22 is made, and the wiring 23 1, 2 3 2 are arranged on both sides of the light emitting element 2 2.
  • the light emitting element 22 can be arranged closer to the center in the width direction of the substrate 21c.
  • the arrangement linearity of the light emitting elements 22 (especially when the substrate 21 is made of glass epoxy) ) Can be improved, and optical characteristics can be improved.
  • the substrate 21 besides a glass epoxy substrate, a ceramic or insulated metal substrate or the like can be used, but in this example, multilayer wiring and elongation are easy, and Also, a low-cost glass epoxy substrate is used. Regardless of the substrate made of glass epoxy, ceramic, or metal, the current limit is to form a fine wiring of about 150 DP1 on the same surface.
  • the wiring 23 in addition to a combination of the multilayer wiring of the substrate 21 and a wire bond wire such as a gold wire, a high-density flexible wiring is connected using an anisotropic conductive adhesive. Etc. can also be used.
  • a plurality of wiring patterns 24 for signal and power supply are formed so as to extend along the arrangement direction of the light emitting elements 22. .
  • data signals etc. are exchanged between the terminals of the adjacent driver IC 1 Cascade connection wiring for the connection.
  • a wire bond wire 25 made of a gold wire is provided between the drive TC 1 and the wiring pattern 24.
  • Each of the plurality of light emitting units 26 is independently formed so as to be able to be driven in a time-division manner, and the plurality of light emitting units 26 are driven so as to be able to be driven in groups of n light emitting units 26. p)).
  • the arrangement order of the light emitting units 26 is shown such that the first, ninth, and 17th light emitting units 26 are the first group, the second, 10.10, and 18th are the second group, and so on.
  • An example is shown in which the numbers are divided into eight groups based on the remainder when the numbers are divided by the number of divisions p (8).
  • the light emitting element 22 includes a common electrode 27-1, which is commonly wired to the light emitting unit 26 belonging to the second group, and a light emitting unit 26 belonging to the second group.
  • a common electrode 27-1 which is commonly wired to the light emitting unit 26 belonging to the second group
  • a light emitting unit 26 belonging to the second group In addition to the common electrodes 2 7 — 2, '..., and the common electrodes 2 7-8, which are commonly wired, n is connected to the eight adjacent light-emitting portions 26, and (48) individual electrodes 28 are provided.
  • the common electrodes 27 are arranged at a density of about 25 DP 1, which is lower than the maximum wiring density (150 DPI) of the board 21, but the individual electrodes 28 are They are arranged at a density of about 150 DPI to maintain the same placement density as the highest wiring density (15 () DP1).
  • the common electrode 27 and the individual electrode 28 are divided on both sides of the light emitting section 26 in order to reduce the number of multilayer wirings formed on the surface of the light emitting element 22, and are arranged in the longitudinal direction of the light emitting element 22. Are arranged along.
  • the light-emitting element 22 includes a light-emitting portion 26 composed of an LED at an intersection of matrix wirings connected to p (8) common electrodes 27 and n (48) individual electrodes 28, respectively. Is located. Therefore, by providing a data signal to the n individual electrodes 28 and selecting one of the common electrodes 27, the n light emitting units 26 can be driven simultaneously, and this is repeated p times. By repeating, one light emitting element 22 can be driven.
  • the individual electrodes 28 are connected to the output terminals DO 1 to D 04 8 of the driving IC 1 via the first wiring 23-1, respectively, and the common electrode 27 is connected to the second wiring 23-2 , And are selectively connected to eight of the output terminals CD 1 to CD 4 (). As shown in Fig.
  • one driving IC 1 that constitutes one block and q (5 in this example) light emitting elements 22 corresponding to the driving IC 1 are output from the driving IC 1
  • the terminals DO 1 to DO 48 are connected via the first wiring 23-1 so that the terminals DO 1 to DO 48 are commonly connected to the individual electrodes 28 of the q light emitting elements 22.
  • the output terminals CD 1 to CD 40 of the driving IC 1 are individually connected to the respective common electrodes 27 of the q (5) light emitting elements 22 via the second wiring 23-2.
  • the correction data to be stored in the storage circuit 1 () uses light amount correction data obtained in advance in order to make the light amounts of the light emitting portions 26 of the light emitting elements 22 uniform, and these data are It is assumed that the information is already stored in the storage circuit 1 ().
  • a reset signal RSET is supplied, whereby each unit is set to an initial state. Subsequently, the setting signal SET is switched from L level to H level. As a result, writing to the storage circuit 1 () is prohibited.
  • a data signal (7680) for one line is sequentially supplied to the data input terminal ST of the driving 1 C 1 located at the end, and this is sequentially driven in synchronization with the clock signal CLK 1. Is taken into shift register 8. When a predetermined number of data has been fetched, a data signal is sequentially applied to the cascade-connected next IC shift register 8 via the data output terminal SO.
  • the shift of all driving ICs] is shifted.
  • the load signal L ⁇ AD 1 is held at the H level for a predetermined time, and the n ⁇ m data signals held in the shift register 8 of each driving IC 1 are held. Is input.
  • the latch circuit 9 is selected (latched) at the falling of the load signal LOAD 1, and the n X m data signals taken into the shift register 8 are sent to the latch circuit 9. Entered and stored.
  • the division timing signal is output to the correct path 14 based on the division timing signal D 1 VSEL supplied from the external force.
  • the division timing signals DIV1 to DIV40 are selectively switched from L level to H level. During this timing period, the strobe signal (STB inverted) is held at the L level for a predetermined period from the H level.
  • the position of the data signal which the selection circuit 11 selects and outputs from the latch circuit 9 or the storage circuit 10 is sequentially switched.
  • the first, ninth,... Data are selected by the division timing signal D 1 V 1.
  • the second, 1 () th,... Data is selected by the division timing signal DIV2.
  • the drive circuit 12 selectively operates the four current amplifiers 12a to 12d based on the data signal and the correction data added thereto, and outputs the output current to the output terminal in the individual terminal section DO. It is supplied to each individual electrode 28 of the light emitting element 22 via the light emitting element 22.
  • a current corresponding to the data signal and the correction data can be supplied to the individual electrodes 28 of all the light emitting elements 22, but only the n light emitting parts 26 selected by the group selection terminal are the common electrodes
  • one light-emitting element 22 is selected for each block, and only every eight light-emitting portions 26 selectively emit light in this example.
  • each drive ⁇ C1 for driving the light emitting element 22 corresponding to the in-element time-division driving controls the second drive unit 3 that operates in synchronization with the timing in units of groups. Since the light emitting element 22 corresponding to the driving IC 1 is time-divisionally driven by the driving IC 1, the load can be distributed. Therefore, the maximum load applied to the second driving unit 3 for performing the time-division driving can be determined based on the number of the light emitting units 26 belonging to one group of the corresponding light emitting elements 22.
  • time-division driving for all light-emitting elements is performed.
  • the load applied to the divided drive circuit can be reduced.
  • the driving IC 1 drives the plurality of light emitting elements 22 in a time-division manner, the number of internal circuits is reduced as compared with the case where the light-emitting element 22 and the time-division driving IC are arranged at a ratio of 1: 1. Can be reduced.
  • q X n is required when the light emitting element and the time-sharing drive 1 C are arranged in a 1: 1 ratio, but in the above configuration, n It was possible to achieve a reduction rate of 1 / (5).
  • the driving IC 1 can be formed in the same shape as the conventional static IC, it is possible to achieve a reduction in the overall circuit configuration.
  • time-division drive configuration data can be sequentially input in the same way as in the static method, so that the data needed for conventional time-division drive can be rearranged. Circuit becomes unnecessary. Also, even if the number of time divisions is increased, the timing signal for time division DIV :! is used by using a smaller number of control signal signal lines than the number of divisions. ⁇ DIV 40 is generated, so that the number of IC terminals and the number of assembly operations can be reduced.
  • the drive [C] is compatible with time-division drive, it can store correction data for all light emitting elements in the same block and select and output it. When performing time-division driving using data for Data signals can be easily corrected.
  • one driving IC and a plurality of light emitting elements connected to the driving IC are regarded as one block, and this block is duplicated in the same direction as the arrangement direction of the light emitting elements. It is suitable for an optical print head having a plurality of optical heads, but is also applicable to other optical heads. For example, an optical print head having only one block as a basic structure, and the like. It can be applied to all printing devices.
  • the configuration of the light emitting element connected to the driving TC can be changed according to the specifications required for the optical print head. That is, the number of individual electrodes (n) of the light emitting element 22 is kept constant, and the number of groups (p) in the light emitting element 22 and the number (q) of the light emitting elements 22 in one block are calculated as
  • the product can be changed as appropriate so that the product is the same as the number (m) of the group selection terminals of the driving IC 1.
  • one block can be formed by arranging eight light-emitting elements each having a division number (p) of five. Also, the number of divisions
  • the number of time divisions (m) is set to 40, but by devising the way of inputting data, the printing required for the optical print head can be improved.
  • the apparent number of time divisions (effective number of time divisions) can be changed according to the speed, etc. For example, if a high printing speed is required and the number of time divisions needs to be changed to a value k smaller than m accordingly, the data processing circuit that supplies the signal to the drive TC 1 must use a division timer. What is necessary is just to perform the process which substantially reduces the number of the mining signals DIV to k.
  • the division timing signal generation circuit 14 when the division timing signal generation circuit 14 is of the up-counter type, when the division number k is exceeded, the clock frequency of the control signal DIVSEL is increased and the remaining timing signals D [V k + 1 to D ⁇ V 40 is generated in an extremely short period of time, and the strobe signal (inverted STB) is held at the ⁇ level to inhibit data printing during the shortened period. be able to.
  • the division timing signal generation circuit 14 is of a decoder type, the timing signal is changed by adding a change corresponding to the desired division number k to the multi-bit control signal DIVSEL provided from the data processing circuit. ⁇ ⁇ DIV 1 to D [It is good if only V k is selectively generated.
  • the time division number (m) of the active IC 1 is changed to set the substantial time division number (k) to, for example, 16 and the driving IC 1 has the light emitting element 2 2 shown in FIG.
  • the driving IC 1 has the light emitting element 2 2 shown in FIG.
  • an optical print head having 768 light emitting units is constructed.
  • FIG. 8 is a plan view of a principal part showing an optical printhead of the present embodiment
  • FIG. 9 is a plan view of a principal part showing a light emitting device of the present embodiment.
  • the configuration of the driving IC is the configuration shown in FIGS. 1 and 2 as in the first embodiment, and the operation is the same as that of the second embodiment.
  • the same parts as those in FIGS. 5 and 6 are denoted by the same reference numerals, and description thereof is omitted.
  • the wiring connected between the driving IC 1 and the light emitting element 2 2 is the first embodiment.
  • the first wiring 2 3 — 1 is provided under the light emitting element 22 as shown in FIG.
  • the second wiring 23-2 is provided on the upper side of the light emitting element 22 and is connected to the light emitting element 22 by wire bond lines on both sides.
  • 2 3 — 2 is for driving further below this second wiring 2 3 — 2
  • a first wiring 2311 connected to the output terminals DO1 to D ⁇ 48 of 1C1 is provided, and the light emitting element 22 is connected on one side by a wire bond line. That is, the wiring having the same length as the arrangement length of the light emitting element 22 in the wiring pattern of the first wiring 23-: 1 and the second wiring 23-2 is Separate only one side and arrange / ⁇ '.
  • the light emitting element 22 electrically connected to the driving 1 C 1 via the first wiring 23-1 and the second wiring 23-2 is similar to the first embodiment.
  • Each of the plurality of light emitting portions 26 is formed independently so as to be able to be driven in a time-division manner, and a plurality (p) is provided so that a group of n light emitting portions 26 can be driven as a unit. It is divided into groups. Further, in the present embodiment, as in the first embodiment, the numbers indicating the arrangement order of the light emitting units 26 are divided into eight groups based on the remainder when the number is divided by the division number p (8). A case will be exemplified.
  • this light emitting element 22 has a common electrode 27 commonly wired to a light emitting section 26 belonging to the first group. And eight common electrodes 27 of common electrodes 27 — 2,..., And common electrodes 27 — 8 that are commonly wired to the light emitting unit 26 belonging to the second group. There are provided n (48) individual electrodes 28 connected to eight adjacent light emitting portions 26.
  • the common electrode 2 7 and the individual electrode 2 8 power 5, Ni would Yo of Figure 6, is divided on both sides of the light-emitting unit 2 6, along the longitudinal direction of the light emitting element 2 2
  • the light emitting sections 26 are arranged on one side along the longitudinal direction of the light emitting elements 22.
  • FIG. 10 is a circuit block diagram showing a basic configuration of a driving TC according to the third embodiment.
  • Fig. 11 is a block diagram of the circuit block diagram shown in Fig. 10, which is extracted mainly from the part related to one output terminal DO1 of the plurality of output terminals DO1 to D ⁇ 96.
  • FIG. 10 a description will be given with reference to these figures.
  • the driving 1 C 1 shown in FIG. 1 () is different from the driving 1 C 1 in FIG. 1 in that the data signal storage circuit 54 is input to the serial from the data input terminals SI 1 to S [4. It has a multi-input shift register 58 with an n X m bit configuration that captures the data signal in synchronization with the clock signal CLK1 and serially outputs it from the data output terminals SO1 to SO4. different. Therefore, the same portions as those in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted.
  • the individual terminal portion DO is composed of a plurality of (n) output terminals DO ⁇ to DO96 for driving the elements.
  • the terminal section CD is composed of a plurality (m) of output terminals CD1 to CD4 for group selection.
  • the data signal has a 384-bit configuration to capture data in parallel in 384-bit units based on the load signal LOAD1.
  • a first drive circuit 12A that outputs a constant current via the output terminals D01 to D096 based on the output of the selection circuit 11A is an n (6) bit G configuration.
  • the correction data storage circuit 10 stores n X m (384) pieces of correction data corresponding to the output correction
  • the second selection circuit 11 B stores the correction data.
  • the correction data signals are sequentially selected in ⁇ ⁇ units from the n X m (384 4) correction data signals output from the data storage circuit 10.
  • the drive circuit 12 B of this configuration has n (96) bits.
  • the storage circuit 10 is configured to store n X m (384) pieces of correction data composed of .S bits (for example, a 3-bit configuration).
  • n X m 384) pieces of correction data composed of .S bits (for example, a 3-bit configuration).
  • it can be configured by a latch circuit having an SX n X m bit configuration.
  • the correction data is written to each correction data storage circuit 10 from the shift register 58. This is performed based on n X m units of signals supplied in parallel.
  • the division timing signal generation circuit 14 is provided with an external circuit so as to specify the time division timing as shown in the circuit diagram of FIG. 12 and the truth table of Table 1.
  • a divided timing signal (DIVV1 to DIV4) is generated based on two external signals, DIVSEL1 and DIVSEL2, which are one of the control signals supplied from the controller.
  • the 3-bit correction data stored in the correction data storage circuit 10 is similarly switched to the H level by the divided timing signals DIV1 to DIV4, so that the second selection circuit 11B As a result of opening the set of three gate circuits in, the signals are selectively output through the opened set of gate circuits.
  • the output of the correction data storage circuit] 0 is supplied to the drive circuit 12 and the three current amplifiers 1 2b cooperate with the data supplied from the latch circuit 9 through the first selection circuit 11A.
  • ⁇ L 2 d is selectively operated.
  • the second drive unit 3 is a circuit for selectively switching one of the output terminals CD1 to CD4 to the ground potential VSS, and is configured to switch by one of the divided timing signals DIVI to DIV4.
  • the selection circuit may be configured to switch using another signal synchronized with the selection timing of 11.
  • FIG. 14 is a plan view of a main part showing an example of the optical print head 20.
  • the driving IC 1 the driving ICs described in the third and fourth embodiments are used.
  • the optical print head 2 () is composed of a plurality of, for example, 20 light emitting elements 22 arranged in a line on an insulating substrate 21, and a driving IC arranged adjacent to one side of the light emitting element 22. 1 are arranged in a line so as to correspond to the light emitting elements 22 in a one-to-one correspondence.
  • the driving ⁇ C 1 is arranged on one side of the light emitting element 22 .
  • the driving IC 1 when the driving IC 1 is arranged on both sides of the light emitting element 22, the light emitting element 22 and the driving TC 1 are connected. It may be arranged in a one-to-two correspondence.
  • a wiring 23 for connecting the light emitting element 22 and the driving IC 1 is provided.
  • a direct connection structure using a wire bond wire such as a gold wire or an indirect connection structure using a wire bond wire with a relay pattern interposed can be used. May be connected using an anisotropic conductive adhesive.
  • a plurality of signal and power supply wiring patterns 24 are formed on the substrate 21 along the direction in which the light emitting elements 22 are arranged.
  • a wiring 25 similar to the wiring 23 is provided between the driving IC 1 and the wiring pattern 24.
  • Each of the plurality of light emitting units 26 is independently formed so as to be able to perform time-division driving, and is divided into a plurality of m groups so as to be able to perform time-division driving in groups.
  • the first, fifth, and ninth of the light emitting units 26 are the first group
  • the second, sixth, and tenth are the second group
  • the third, the seventh, and the first are the third group.
  • This example illustrates a case where the first and second groups are divided into four groups based on the number of remainders obtained by dividing the number indicating the arrangement order of the light emitting units 26 by 4, such as a fourth group.
  • the light emitting element 22 has a common electrode 27-1 commonly connected to the light emitting unit 26 belonging to the second group, and a common electrode 27 commonly connected to the light emitting unit 26 belonging to the second group.
  • -Two common electrodes 27-3 and two common electrodes 27-4 are provided, and at the same time, n (9 6) Individual electrodes 28 are provided. These individual electrodes 28 are connected to the output terminals DO 1 To D096, and the common electrode 27 is connected to the output terminals CD], CD2, CD3, and CD4. Then, if the common electrode 27 is selected and an electric current is supplied to an arbitrary individual electrode DO, one quarter of the light emitting section 26 emits light in a time-division manner.
  • FIG. 15 is a circuit block diagram of the optical print head 20.
  • 20 light emitting elements 22 are arranged in a row.
  • the number with # is the serial number of the light emitting part 26 of the entire optical print head 2 ().
  • Each of the individual electrodes 28 is commonly connected to one of the four groups of light emitting sections 26 (the anodes thereof), and the power source of each of the light emitting sections 26 belonging to each group is a common electrode 2 7 — 1, 2, 7 — 2, 2, 7 — 3, 2 7 — 4 are connected.
  • the individual electrodes 28 are connected to the individual terminals DO 1 to DO 96 of the driving IC 1.
  • the common electrodes 2 7 — 1, 2 7 — 2, 2 7 — 3, and 2 7 — 4 are connected to output terminals CD 1, CD 2, CD 3, and CD 4, respectively.
  • the data input terminals SI 1 to SI 4 of the first driving IC 1 are connected to the data output terminals SO 1 to S ⁇ 4 of the second driving TC 1.
  • the second to ninth drive [C 1 data input terminals SI 1 to SI 4 are respectively connected to the data output terminals SO 1 to S ⁇ 4 of the drive IC 1 with the largest number.
  • the data signal from the outside is input to the data input terminal S11 to SI4 of the 2 () th drive IC 1.
  • Each drive TC 1 has the power supply voltage VDD 1 and the external signal DIVSEL 1 , 2 and a load signal are input, such as OAD 1.
  • SI force: SI 1 to S SI4, and SO denotes S 01 to S 04.
  • the setting signal SET is switched from L level to H level. As a result, writing to the storage circuit 10 is prohibited.
  • Data input terminals SI 1 to S ⁇ 4 of the 0th drive IC 1 8 () pieces are sequentially given in r units, and these are sequentially taken into the multi-input shift register 58 of each driving IC 1 in synchronization with the clock signal C 1.
  • the data signals given to the data input terminals SI1 to SI4 are the first, fifth and ninth data at the input terminal SI], and the second, sixth and tenth data at the input terminal S [2].
  • the input is preliminarily sorted into the forms corresponding to the four groups of light emitting elements.
  • the data signal is sent to the shift register 58 of the adjacent drive C1 via its output terminals S01 to SO4. Is given.
  • the data input time can be significantly reduced as compared with the case of one input.
  • the load signal LOAD 1 is held at the H level for a predetermined time, and the input of the n X m data signals held in the shift register 8 of each driving IC 1 is performed. Done.
  • the latch circuit 9 is selected (latched) at the time of the falling of the load signal LOAD 1, so that n X m data signals taken into the shift register 8 are sent to the latch circuit 9. Entered and stored.
  • the external signals DIVSEL 1 and 2 indicating the light emission timing are both held at the L level, and accordingly, the divided timing signal generation circuit is generated. Only DIV 1 of the division timing signal output by 14 switches from the low level to the H level. Immediately after that, the external strobe signal (STB inverted), which indicates the timing of light emission, is held at the L level for a predetermined period from the H level. During that time, the light emitting element selectively emits light.
  • the position of the data signal that the selection circuit 11 selects and outputs from the latch circuit 9 or the storage circuit 1 () is sequentially switched. For example, the first, fifth,... 677 7th data is selected by the division timing signal DIV1, and the second, sixth,... The eighth data is selected.
  • the drive circuit 12 selectively activates the four current amplifiers 12a to 12d based on the data signal and the correction data added thereto, and outputs the output current through the output terminal DO to the light emitting element 2 2 to each individual electrode 2 8.
  • a current corresponding to the data signal and the correction data can be supplied to the individual electrodes 28 of all the light emitting elements 22, but only the light emitting part 26 of i / 4 is grounded through the common electrode 27. In this example, only every fourth light emitting section 26 selectively emits light during the L-level period of the strobe signal (inverted STB).
  • one line of selective light emission is performed by time-division driving by switching every quarter of a quarter, and by repeating this sequentially, one screen of exposure can be performed.
  • the data signal for one line can be input in a single processing operation, even though the configuration is such that time-division driving is performed, so the same number of divisions as in the conventional circuit is performed.
  • the process of repeatedly inputting a data signal is not required.
  • the number of groups (m) and the number of data input terminals (r) are set to be the same, so that data can be sorted in advance and data can be input in each county, making data input processing easy. You can do it.
  • FIGS. 16 to 21 show these examples. This will be described below with reference to the schematic configuration diagram shown in Fig. 2 and the timing chart shown in Fig. 22 to Fig. 25.
  • FIG. 16 is a schematic configuration diagram corresponding to the configuration of the optical print head described above.
  • the driving IC 1 performs one line of data input in 1920 clocks, and the other two inputs SI3 and S12.
  • S14 data input for the next one line can be performed simultaneously.
  • 3- I try to do it.
  • the timing of two lines of data is acquired by a single data input process, and then the divided timing signal DIVI
  • the first group (odd data) on the first line is selected, the second group (even data) on the first line is selected by the divided timing signal DIV2, and the second group is selected by the divided timing signal I] IV3.
  • the first group (odd data) on the line can be selected, and the second group (even data) on the second line can be selected by the division timing signal DIV4.
  • the 1200 DPI-compatible drive 1C1 can be used to drive the 60 () DPI light-emitting element 22.
  • the data signal to be input to the driving IC 1 can be used to input four lines of data, as shown in Figure 23. Perform in 20 clocks. It is necessary to change the input form of the signal according to these changes. The other configuration except for these changes is the same as that of the optical print head 20 (FIG. 16).
  • the driving 1 C 1 uses one input SI 1 to input the odd-numbered data signal of one light-emitting element, and the next input SI 2 To input the even-numbered data signal of one light-emitting element, use the next input SI 3 to input the odd-numbered data signal of the other light-emitting element, and connect the next input SI 4 By using it to input the even-numbered data signal of the other light emitting element, data input for one line is performed in 960 clocks. It is necessary to change the input form of the signal according to these changes. Other configurations except for these changes are the same as those of the optical print head 20 (FIG. 16). By doing so, the driving IC 1 corresponding to 1200 DPI can be used for driving the light emitting element 22 of 6 () 0 DPI.
  • the driving IC and the light emitting element can be arranged as one unit (block) maintaining a 1: 2 relationship in the longitudinal direction of the substrate 21, the number of driving ICs can be reduced.
  • the driving IC 1 uses one input SI 1 to input the data signal of the second light-emitting element, and uses the next input SI 2 Input the data signal of the second light-emitting element, input the data signal of the third light-emitting element using the next input SI3, and input the data signal of the third light-emitting element using the next input SI4.
  • the driving IC 1 supporting 1200 DPI can be used to drive the light emitting element 22 of 30 ODPI.
  • the driving IC and the light emitting element can be arranged as one unit (block) maintaining a 1: 4 relationship in the longitudinal direction of the substrate 21, the driving IC and the light emitting element can be arranged. The number can be reduced.
  • FIG. 26 is a main part of the driving IC 1 according to the fourth embodiment, which is mainly extracted from a portion related to one output terminal DO 1 of a plurality of output terminals D 01 to D 096. It is a circuit block diagram. In the present embodiment, a latch circuit 11C that stores a smaller number of data than the number of data stored in the shift register 58 is used. Hereinafter, the present embodiment will be described with reference to FIGS. 26 and 27.
  • a latch circuit 11 C for storing the same number of data as that of 6) and a selection circuit 11 ⁇ ⁇ for selectively inputting data to the latch circuit 11 C are used.
  • the latch circuit 11C is composed of n (96) -bit latches that store the same number of data as the number of output terminals DOl to DO96. Capture data.
  • the data stored in shift register 58 is applied to sequential latch circuit 11C by repeating such selection processing m times.
  • the n data output from the latch circuit 11 C are supplied to the driver circuit 12 while the strobe signal (inverted STB) is at the L level (the divided timing signal generation circuit 14 is shown in FIG. 12).
  • a counter-type circuit configuration that counts and outputs one external timing signal DIVSEL pulse is used, as shown in Fig. 28.
  • two flip-flops FF1 and FF2 and a power counter combining a plurality of (four) logic gate circuits G1 to G4 are used. Configure You can.
  • the power supply voltage VDD1 which is at H level, is input to the input terminals J and K of the JK flip-flop FF1, and the external signal D ⁇ ⁇ VSEL is input to the clock input terminal CL.
  • the reset signal RESET is input to the set input terminal R.
  • the signal QA is output from the output terminal Q of the flip-flop FF1, and the signal ⁇ "X is output from the output terminal Q.
  • JK The signal is input to the input terminals J and K of the flip-flop FF2 QA is input, the external signal DIVSEL is input to the clock input terminal CL, and the reset signal RESET is input to the reset input terminal R.
  • the output terminal Q of the flip-flop FF 2 Signal QB is output from the output terminal Q.
  • the logic gate circuit G1 uses the external signal D ⁇ VSEL and the AND of the signals QA and QB to divide the timing signal DIV].
  • the logic gate circuit G2 outputs the external signal DIV.
  • the logic gate circuit G3 outputs the division timing signal DIV3 by using the external signal DIVSEL, the signal QA, and the signal QB.
  • the logic gate circuit G4 outputs a division timing signal DIV4 by using the AND signal of the external signal DIVSEL and the signals QA and QB.
  • this embodiment is shown in the timing chart of FIG. As shown in this figure, after fetching one line of data via the 1.0.92 clock via the four inputs SI1 to SI4, the drive of that one line of data is started. Until the process is completed, the next line of data cannot be fetched, so the processing speed will be slower, but the number of circuit elements inside the driving IC will be reduced to reduce the size and cost of the IC be able to. Therefore, this embodiment is suitable for an optical printhead in which downsizing and cost reduction are prioritized over processing speed.
  • a light emitting element in which a light emitting portion having another structure such as a light emitting diode (light emitting thyristor) having a PNPN junction is used in addition to a light emitting diode having a PN junction.
  • a light emitting portion having another structure such as a light emitting diode (light emitting thyristor) having a PNPN junction.
  • the arrangement in which the light-emitting portions are arranged in one line
  • the arrangement in which the light-emitting portions are arranged in a zigzag pattern, or the arrangement in which two or more light-emitting sections are arranged in a plurality of rows can be used.
  • a driving IC is arranged on one side of the light emitting element.
  • driving ICs may be arranged on both sides of the light emitting element.
  • the driving IC may be configured such that only one of the first driving unit 2 and the second driving unit 3 is opened by opening one of the individual terminal unit and the common terminal unit or by another method. Can also be used selectively.
  • a multi-input shift register in which data is input in parallel from a plurality of input terminals may be used.
  • the present invention it is possible to perform the drive corresponding to the time-division drive while maintaining the same data processing procedure as the conventional static drive, and the compatibility with the static drive is improved. You can keep it.
  • time-division driving since time-division driving is supported, the number of driving TCs can be reduced, and the number and density of wire bonds can be reduced.
  • various combinations of the driving 1 C and the light emitting element connected thereto can be set. Also, it is easy to change the printing speed by changing the number of time divisions by changing the input data. Also, even if the density (resolution) of the wiring patterns arranged on the substrate is low, a high-resolution optical printhead can be provided.
  • a driving IC capable of supporting a plurality of types of light emitting elements having different resolutions.
  • a driving IC and an optical printhead that can input data at high speed. Further, the size and cost of the optical print head can be reduced, and the printing speed can be increased.

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  • Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Health & Medical Sciences (AREA)
  • General Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Led Devices (AREA)
  • Printers Or Recording Devices Using Electromagnetic And Radiation Means (AREA)

Abstract

L'invention porte sur une tête d'impression optique comprenant un émetteur de lumière (22) possédant n électrodes (28) individuelles, p électrodes (27) communes et une pluralité de (nxp) parties (26) luminescentes sélectionnées par ces électrodes, et un circuit intégré (1) pilote possédant des électrodes individuelles et m bornes (CD1-CD40) de sélection de groupe. Cette invention se caractérise en ce qu'un circuit intégré pilote est pourvu d'un nombre (q) d'une pluralité d'éléments (22) luminescents, le nombre q étant déterminé par le nombre p d'électrodes (27) communes et le nombre m de bornes (CD) de sélection de groupe.
PCT/JP2000/006333 1999-09-20 2000-09-14 Circuit integre pilote et tete d'impression optique WO2001021411A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP00961037A EP1215050A4 (fr) 1999-09-20 2000-09-14 Circuit integre pilote et tete d'impression optique
US10/088,266 US6853396B1 (en) 1999-09-20 2000-09-14 Driving ic and optical print head
HK03101154.7A HK1048968A1 (zh) 1999-09-20 2003-02-18 驅動ic和光學打印頭

Applications Claiming Priority (4)

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JP26590499A JP2001088345A (ja) 1999-09-20 1999-09-20 光プリントヘッド
JP11/265904 1999-09-20
JP29406999 1999-10-15
JP11/294069 1999-10-15

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CN (1) CN1374906A (fr)
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Cited By (1)

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Publication number Priority date Publication date Assignee Title
US6853396B1 (en) 1999-09-20 2005-02-08 Sanyo Electric Co., Ltd. Driving ic and optical print head

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JP4192987B2 (ja) * 2006-11-02 2008-12-10 セイコーエプソン株式会社 光ヘッド、露光装置、および画像形成装置。

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JPS61228973A (ja) * 1985-04-03 1986-10-13 Alps Electric Co Ltd Ｌｅｄプリンタの光書込みヘツド
JPH0691933A (ja) * 1992-09-17 1994-04-05 Tokyo Electric Co Ltd 端面発光型ラインヘッドの駆動装置

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US5307089A (en) * 1989-08-07 1994-04-26 Sanyo Electric Co., Ltd. Optical printing head
JP3696276B2 (ja) * 1995-01-11 2005-09-14 沖電気工業株式会社 一次元配列有機ｅｌ発光素子アレイヘッド及びその製造方法
JP3219263B2 (ja) * 1995-05-23 2001-10-15 キヤノン株式会社 発光装置
JP3703234B2 (ja) * 1996-12-24 2005-10-05 キヤノン株式会社 画像記録装置
JP3357810B2 (ja) * 1997-01-28 2002-12-16 三洋電機株式会社 光プリントヘッド
JP3357811B2 (ja) * 1997-02-13 2002-12-16 三洋電機株式会社 駆動用ｉｃ及び光プリントヘッド
JP2001088345A (ja) * 1999-09-20 2001-04-03 Sanyo Electric Co Ltd 光プリントヘッド

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JPS61228973A (ja) * 1985-04-03 1986-10-13 Alps Electric Co Ltd Ｌｅｄプリンタの光書込みヘツド
JPH0691933A (ja) * 1992-09-17 1994-04-05 Tokyo Electric Co Ltd 端面発光型ラインヘッドの駆動装置

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6853396B1 (en) 1999-09-20 2005-02-08 Sanyo Electric Co., Ltd. Driving ic and optical print head

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HK1048968A1 (zh) 2003-04-25
EP1215050A4 (fr) 2003-03-26
CN1374906A (zh) 2002-10-16
EP1215050A1 (fr) 2002-06-19

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