Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
  • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
  • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
  • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
  • H03K19/09425—Multistate logic
  • H03K19/09429—Multistate logic one of the states being the high impedance or floating state
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
  • H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
  • H03K19/0175—Coupling arrangements; Interface arrangements
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
  • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
  • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
  • H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
  • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
  • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
  • H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
  • H03K19/0823—Multistate logic
  • H03K19/0826—Multistate logic one of the states being the high impedance or floating state

Definitions

• Televisions and other electronic devices have various complex electronic circuits that may be analog, digital, or a combination of analog and digital. Because of their complexity, good design characteristics or criteria dictate that the fewer the components the better. As well, some of these electronic circuits require different state conditions during various stages of operation. In a power- up condition, for example, it may be desirous to provide a signal to a common circuit that is not to be provided after steady state is reached, and/or vice versa.
• the television apparatus 1 0 may or may not include a monitor or other similar display device 1 2.
• the television apparatus 1 0 as well, may or may not include a micro controller (" ⁇ C") or control circuitry 14 for providing general control of the various components of the television apparatus 1 0, memory 1 6, an audio reproduction section 24, appropriate processing circuitry 1 8, and a tuner 22.
• ⁇ C micro controller
• the various components depicted in Fig. 1 are only exemplary, as other and/or different components may be part of the television apparatus 1 0. Additionally, other devices may have different components.
• the term television apparatus 1 0 should hereinafter be construed to cover all types of electrical devices each having various components unless indicated otherwise.
• the television apparatus 1 0 typically includes appropriate circuitry, software, and other components to support/provide a display, an integral control system, a user-interface and on-screen display (OSD) functionality. It should be appreciated that the television apparatus 1 0 may take other forms and have additional capabilities and/or functionality other than those shown and/or discussed through appropriate circuitry, software, and/or other components. As well, it should be appreciated that the various connections and/or interconnections depicted in Fig. 1 are exemplary, and thus, such connections/interconnections may vary.
• the television apparatus 1 0 may require different states or signals during a power-up condition (i.e. the television apparatus 10 has been turned "on"). This may be accomplished with a circuit producing an output signal having at least three logic states (e.g., logic 0 (or low level state), logic 1 (or high level state), high-impedance (or high-Z state)) such as a tri-state circuit per the principles of the present invention, an example of which is depicted in Fig. 2.
• logic states e.g., logic 0 (or low level state), logic 1 (or high level state), high-impedance (or high-Z state)
• a tri-state circuit per the principles of the present invention, an example of which is depicted in Fig. 2.
• the logic state of the output produced by a buffer circuit included in the tri-state circuit is determined in response to the logic state of the input signal to the buffer circuit.
• the output of the buffer circuit is in a high- impedance condition, or high Z, state independent of the logic state of
• the enable 46 changes from the low state to a high state.
• the control circuit 50 will continue to provide a voltage sufficient to keep the enable 46 in a high state for a predetermined period of time.
• the predetermined period of time is a function of the time constant ( ⁇ ) of the control circuit 50, which is a function of the various components of the control circuit 50, the connection scheme of the various components, and the value of the various components.
• the control circuit 50 generates a control signal, or enable, causing the buffer circuit to selectively operate in one of the first and second modes of operation.
• the first mode of operation corresponds to the buffer circuit operating to produce an output signal having one of first and second logic states that are produced in response to respective logics states of the input signal to the buffer circuit.
• the second mode of operation corresponds to the output signal exhibiting a third logic state, e.g., a high impedance state, independent of the logic state of the input signal.
• the control circuit generates the control signal only directly in response to operating power being applied to the control circuit.
• the control circuit generates the control signal causing the buffer circuit to operate in the second mode of operation only for a predetermined interval subsequent to operating power being applied to the control circuit.
• the control circuit generates the control signal causing the buffer circuit to operate in the first mode of operation at all times other than the predetermined interval.
• the control circuit generates the control signal to change the operating mode of the buffer circuit only in response to operating power being applied to the control circuit.
• the operating mode of the buffer circuit does not change at other times, i.e., not at any time during normal operation of the apparatus.
• the third, or high-impedance, state of the buffer circuit output is produced only directly in response to operating power being applied, i.e., during power up, and only for a predetermined finite time period thereafter.
• the high-impedance state of the buffer circuit output is not produced at other times, i.e., not at any time during normal operation of the apparatus.
• the buffer circuit is utilized only during power-up to provide a high-impedance condition of predetermined duration.
• the output signal of the buffer circuit is coupled to operational circuitry that responds to the third logic state, or high impedance condition, by entering a normal mode of operation. Without the high- impedance condition, the operational circuitry would not enter normal operating mode properly.
• the control circuit 50 comprises a capacitor C electrically coupled in series with a resistor R.
• the capacitor C is electrically coupled to the voltage source (designated in Fig. 2 as " + 5V"), while the resistor R is electrically coupled to ground 60.
• the control circuit 50 depicted in Fig. 2 is a series R-C circuit.
• the enable 46 is electrically coupled to the control circuit 50 at point A (between the series coupled capacitor C and the resistor R) .
• the voltage at point A is graphically depicted in Fig. 3. With reference to Fig. 3, there is depicted a graph, generally designated
• the voltage on the capacitor C (and thus point A) reaches a maximum value.
• the voltage at point A begins to decay.
• the enable 46 is changed from high to low.

Landscapes

• Engineering & Computer Science (AREA)
• Computer Hardware Design (AREA)
• Physics & Mathematics (AREA)
• Computing Systems (AREA)
• General Engineering & Computer Science (AREA)
• Mathematical Physics (AREA)
• Power Engineering (AREA)
• Logic Circuits (AREA)
• Electronic Switches (AREA)
• Television Receiver Circuits (AREA)
• Dc-Dc Converters (AREA)

Priority Applications (6)

Applications Claiming Priority (2)

Publications (1)

Family

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Family Applications (1)

Country Status (8)

Families Citing this family (2)

Citations (4)

Family Cites Families (5)

• 2000
  • 2000-07-14 KR KR1020027000030A patent/KR100727570B1/ko not_active Expired - Lifetime
  • 2000-07-14 EP EP00948677A patent/EP1196995B1/en not_active Expired - Lifetime
  • 2000-07-14 WO PCT/US2000/019258 patent/WO2001006655A1/en not_active Ceased
  • 2000-07-14 CN CN008103992A patent/CN1218486C/zh not_active Expired - Lifetime
  • 2000-07-14 MX MXPA02000553A patent/MXPA02000553A/es active IP Right Grant
  • 2000-07-14 JP JP2001510991A patent/JP4891504B2/ja not_active Expired - Lifetime
  • 2000-07-14 AU AU62147/00A patent/AU6214700A/en not_active Abandoned
  • 2000-07-14 DE DE60006967T patent/DE60006967T2/de not_active Expired - Lifetime

Patent Citations (4)

Non-Patent Citations (1)

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