AU6214700A - Tristate circuit for power up conditions - Google Patents

Tristate circuit for power up conditions

Info

Publication number
AU6214700A
AU6214700A AU62147/00A AU6214700A AU6214700A AU 6214700 A AU6214700 A AU 6214700A AU 62147/00 A AU62147/00 A AU 62147/00A AU 6214700 A AU6214700 A AU 6214700A AU 6214700 A AU6214700 A AU 6214700A
Authority
AU
Australia
Prior art keywords
conditions
power
tristate circuit
tristate
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU62147/00A
Other languages
English (en)
Inventor
Yefim Vayl
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thomson Licensing SAS
Original Assignee
Thomson Licensing SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson Licensing SAS filed Critical Thomson Licensing SAS
Publication of AU6214700A publication Critical patent/AU6214700A/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/09425—Multistate logic
    • H03K19/09429—Multistate logic one of the states being the high impedance or floating state
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
    • H03K19/0823—Multistate logic
    • H03K19/0826—Multistate logic one of the states being the high impedance or floating state

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)
  • Television Receiver Circuits (AREA)
  • Electronic Switches (AREA)
  • Dc-Dc Converters (AREA)
AU62147/00A 1999-07-16 2000-07-14 Tristate circuit for power up conditions Abandoned AU6214700A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14442299P 1999-07-16 1999-07-16
US60144422 1999-07-16
PCT/US2000/019258 WO2001006655A1 (en) 1999-07-16 2000-07-14 Tristate circuit for power up conditions

Publications (1)

Publication Number Publication Date
AU6214700A true AU6214700A (en) 2001-02-05

Family

ID=22508525

Family Applications (1)

Application Number Title Priority Date Filing Date
AU62147/00A Abandoned AU6214700A (en) 1999-07-16 2000-07-14 Tristate circuit for power up conditions

Country Status (8)

Country Link
EP (1) EP1196995B1 (enExample)
JP (1) JP4891504B2 (enExample)
KR (1) KR100727570B1 (enExample)
CN (1) CN1218486C (enExample)
AU (1) AU6214700A (enExample)
DE (1) DE60006967T2 (enExample)
MX (1) MXPA02000553A (enExample)
WO (1) WO2001006655A1 (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103746681B (zh) * 2013-12-24 2017-06-30 北京时代民芯科技有限公司 一种cmos器件电源上下电输出三态控制电路
US10345832B1 (en) * 2018-05-14 2019-07-09 Asm Ip Holding B.V. Insulation system and substrate processing apparatus

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5915208B2 (ja) * 1978-06-06 1984-04-07 日本電信電話株式会社 パワ−・オン・リセツト回路
US4210829A (en) * 1978-10-02 1980-07-01 National Semiconductor Corporation Power up circuit with high noise immunity
JPS60116223A (ja) * 1983-11-28 1985-06-22 Hitachi Ltd ドライステ−トゲ−トの保護回路
US4871926A (en) * 1988-09-06 1989-10-03 Motorola, Inc. Low power, three state power up circuit
JPH05184066A (ja) * 1992-01-07 1993-07-23 Mitsubishi Electric Corp 出力ドライブ回路
JP2803448B2 (ja) * 1992-04-02 1998-09-24 日本電気株式会社 出力回路
JPH0675668A (ja) * 1992-08-25 1994-03-18 Nec Corp 出力回路
JP3287248B2 (ja) * 1996-12-20 2002-06-04 富士通株式会社 半導体集積回路
JP3779486B2 (ja) * 1999-03-23 2006-05-31 株式会社東芝 半導体集積回路

Also Published As

Publication number Publication date
DE60006967T2 (de) 2004-10-21
CN1361944A (zh) 2002-07-31
WO2001006655A1 (en) 2001-01-25
KR100727570B1 (ko) 2007-06-14
EP1196995B1 (en) 2003-12-03
JP2003533903A (ja) 2003-11-11
DE60006967D1 (de) 2004-01-15
KR20020027460A (ko) 2002-04-13
JP4891504B2 (ja) 2012-03-07
MXPA02000553A (es) 2002-07-02
EP1196995A1 (en) 2002-04-17
CN1218486C (zh) 2005-09-07

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase