US8189391B2 - Non-volatile semiconductor storage device including a control circuit - Google Patents

Non-volatile semiconductor storage device including a control circuit Download PDF

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US8189391B2
US8189391B2 US12/620,986 US62098609A US8189391B2 US 8189391 B2 US8189391 B2 US 8189391B2 US 62098609 A US62098609 A US 62098609A US 8189391 B2 US8189391 B2 US 8189391B2
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wiring
voltage
selection transistor
gate
layer
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US20100172189A1 (en
Inventor
Kiyotaro Itagaki
Yoshihisa Iwata
Hiroyasu Tanaka
Masaru Kidoh
Masaru Kito
Ryota Katsumata
Hideaki Aochi
Akihiro Nitayama
Takashi Maeda
Tomoo Hishida
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Kioxia Corp
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Toshiba Corp
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits

Definitions

  • the present invention relates to an electrically rewritable non-volatile semiconductor storage device.
  • Lamination-type non-volatile semiconductor storage devices have columnar semiconductor layers, MONOS layers formed to surround the columnar semiconductor layers, and conductive layers formed to surround the MONOS layers.
  • the erase operation is performed by increasing the substrate potential corresponding to a channel to an erase voltage so that electrons are removed from relevant MONOS layers.
  • the above-mentioned lamination-type non-volatile semiconductor storage devices should involve columnar semiconductor layers as their channels. Thus, it is inefficient and infeasible to perform the erase operation in the lamination-type non-volatile semiconductor storage devices in the same manner as in the planar-type devices.
  • One aspect of the present invention provides a non-volatile semiconductor storage device comprising: a memory string including a plurality of memory cells connected in series; a first selection transistor having one end connected to one end of the memory string; a first wiring having one end connected to the other end of the first selection transistor; a second wiring connected to a gate of the first selection transistor; and a control circuit configured to perform erase operation to erase data from the memory cells
  • the memory string comprising: a first semiconductor layer having a columnar portion extending in a vertical direction to a substrate; an electric charge storage layer formed to surround the first semiconductor layer; and a first conductive layer surrounding the electric charge storage layer and extending parallel to the substrate
  • the first selection transistor comprising: a second semiconductor layer in contact with a top or bottom surface of the columnar portion and extending in the vertical direction to the substrate; a first gate insulation layer formed to surround the second semiconductor layer; and a second conductive layer surrounding the first gate insulation layer and extending parallel to the substrate
  • the control circuit being configured to boost voltages of the second
  • FIG. 1 is a circuit diagram of a non-volatile semiconductor storage device according to a first embodiment of the present invention
  • FIG. 2 is a circuit diagram of one memory string MS according to the first embodiment
  • FIG. 3 is a circuit diagram of a word-line driving circuit 110 a ( 110 b ) according to the first embodiment
  • FIG. 4 is a circuit diagram of a selection-gate-line driving circuit 120 a ( 120 b ) according to the first embodiment
  • FIG. 5 is a circuit diagram of boost circuits 140 A to 140 C according to the first embodiment
  • FIG. 6A is a timing chart illustrating operations of the boost circuits 140 A to 140 C;
  • FIG. 6B is a timing chart illustrating operations of the boost circuits 140 A to 140 C;
  • FIG. 8 is a circuit diagram of a sense amplifier circuit 150 according to the first embodiment
  • FIG. 9 is a schematic perspective view illustrating a part of a memory cell array AR 1 in the non-volatile semiconductor storage device according to the first embodiment
  • FIG. 10 is a partial cross-sectional view of FIG. 9 ;
  • FIG. 11 is a flowchart illustrating an erase operation according to the first embodiment
  • FIG. 12 is a schematic diagram illustrating the erase operation according to the first embodiment
  • FIG. 13 is a diagram for illustrating the GIDL current according to the first embodiment
  • FIG. 14A is a timing chart illustrating an erase operation according to the first embodiment
  • FIG. 14B is a timing chart illustrating the erase operation according to the first embodiment
  • FIG. 15 is a circuit diagram of a non-volatile semiconductor storage device according to a second embodiment
  • FIG. 16 is a circuit diagram of a sense amplifier circuit 150 a according to the second embodiment.
  • FIG. 17 is a diagram for illustrating the GIDL current according to the second embodiment.
  • FIG. 18 is a timing chart illustrating an erase operation according to the second embodiment
  • FIG. 19 is a circuit diagram of a non-volatile semiconductor storage device according to a third embodiment.
  • FIG. 20 is a circuit diagram of one memory string MSa according to the third embodiment.
  • FIG. 21 is a schematic perspective view illustrating a part of a memory cell array AR 1 a in the non-volatile semiconductor storage device according to the third embodiment
  • FIG. 22 is a partial cross-sectional view of FIG. 21 ;
  • FIG. 23 is a diagram for illustrating the GIDL current according to the third embodiment.
  • FIG. 24 is a circuit diagram of a non-volatile semiconductor storage device according to a fourth embodiment.
  • FIG. 25 is a circuit diagram of a selection-gate-line driving circuit 120 c ( 120 d ) according to the fourth embodiment
  • FIG. 26A is a circuit diagram of a boost circuit 140 D according to the fourth embodiment.
  • FIG. 26B is a circuit diagram of an oscillation circuit 141 D according to the fourth embodiment.
  • FIG. 26C is a circuit diagram of a level shifter 143 Db 1 according to the fourth embodiment.
  • FIG. 27 is a circuit diagram of a source-line driving circuit 160 a according to the fourth embodiment.
  • FIG. 28A is a circuit diagram of transfer circuits 186 e and 185 f according to the fourth embodiment
  • FIG. 28B is a circuit diagram of the transfer circuits 186 e and 185 f according to the fourth embodiment
  • FIG. 29 is a flowchart illustrating an erase operation according to the fourth embodiment.
  • FIG. 30 is a schematic diagram illustrating the erase operation according to the fourth embodiment.
  • FIG. 31A is a timing chart illustrating the erase operation according to the fourth embodiment.
  • FIG. 31B is a timing chart illustrating the erase operation according to the fourth embodiment.
  • FIG. 1 is a circuit diagram of the non-volatile semiconductor storage device in the first embodiment.
  • the non-volatile semiconductor storage device in the first embodiment comprises a memory cell array AR 1 and a control circuit AR 2 provided on the periphery thereof.
  • the memory cell array AR 1 has electrically rewritable memory transistors MTr 1 to MTr 8 (memory cells).
  • the control circuit AR 2 includes control circuits for controlling voltage applied to the memory transistors MTr 1 to MTr 8 and so on.
  • the memory cell array AR 1 has m columns of memory blocks MB.
  • Each memory block MB comprises n rows and 2 columns of memory strings MS, source-side selection transistors SSTr each connected to one end of the memory string MS, and drain-side selection transistors SDTr each connected to the other end of the memory string MS.
  • the first column is denoted by (1) and the second column by (2).
  • each memory string MS has memory transistors MTr 1 to MTr 8 and a back-gate transistor BTr.
  • the memory transistors MTr 1 to MT 4 are connected in series.
  • the memory transistors MTr 5 to MTr 8 are connected in series.
  • the back-gate transistor BTr is provided between the memory transistors MTr 4 and MTr 5 .
  • the memory transistors MTr 1 to MTr 8 which include a MONOS structure, cause electric charges to be accumulated in respective control gates. Through the accumulation of electric charges, the non-volatile semiconductor storage device in the first embodiment store data.
  • control gates of the memory transistors MTr 1 to MTr 8 are connected to the word lines WL 1 to WL 8 .
  • the control gate of the back-gate transistor BTr is connected to the back-gate line BG.
  • each back-gate line BG is provided in common to the control gates of the back-gate transistors BTr aligned in the row direction, and formed to extend in the row direction across the memory strings MS.
  • each source-side selection transistor SSTr is connected to one end of a memory transistor MTr 8 .
  • the other end of each source-side selection transistor SSTr is connected to a first source line SLA.
  • the control gate of each source-side selection transistor SSTr is connected to a source-side selection gate line SGS.
  • each first source line SLA is provided in common to the sources of the source-side selection transistors SSTr aligned in the row direction, and formed to extend in the row direction across a plurality of memory strings MS.
  • the first source lines SLA aligned in the column direction are commonly connected to single second source line SLB extending in the column direction.
  • Each source-side selection gate line SGS is provided in common to the control gates of the source-side selection transistors SSTr aligned in the row direction, and formed to extend in the row direction across a plurality of memory strings MS.
  • each drain-side selection transistor SDTr is connected to one end of a memory transistor MTr 1 .
  • the other end of each drain-side selection transistor SDTr is connected to a bit line BL.
  • the control gate of each drain-side selection transistor SDTr is connected to a drain-side selection gate line SGD.
  • each bit line BL is provided in common to the drains of the drain-side selection transistors SDTr aligned in the column direction, and formed to extend in the column direction across a plurality of memory blocks MB.
  • Each drain-side selection gate line SGD is provided in common to the control gates of the drain-side selection transistors SDTr aligned in the row direction, and formed to extend in the row direction across a plurality of memory strings MS.
  • the control circuit AR 2 boosts the voltage of a source line SL and a source-side selection gate line SGS, while keeping the voltage of the source line SL (first and second source lines SLA and SLB) greater than that of the source-side selection gate line SGS by a certain potential difference.
  • the certain potential difference is a potential difference Vth that causes a GIDL current. This is one of the characteristics of this embodiment. Note that the certain potential difference is not limited to the potential difference Vth.
  • the control circuit AR 2 has an input/output circuit 100 , word-line driving circuits 110 a and 110 b , the selection-gate-line driving circuits 120 a and 120 b , an address decoder circuit 130 , boost circuits 140 A to 140 C, a sense amplifier circuit 150 , a source-line driving circuit 160 , aback-gate-line driving circuit 170 , a first row decoder circuit 180 a , a second row decoder circuit 180 b , and a sequencer 190 .
  • the input/output circuit 100 receives information to be input to the memory cell array AR 1 from the outside and inputs it to the sense amplifier circuit 150 . In addition, the input/output circuit 100 outputs the information from the sense amplifier circuit 150 .
  • the word-line driving circuit 110 a outputs signals V CG1 to V CG4 for driving word lines WL 1 to WL 4 .
  • the word-line driving circuit 110 b outputs signals V CG5 to V CG8 for driving word lines WL 5 to WL 8 .
  • the selection-gate-line driving circuit 120 a outputs signals V SGS1 , V SGD2 , and V SGOFF .
  • the selection-gate-line driving circuit 120 a outputs signals V SGS2 , V SGD1 , and V SGOFF .
  • the signals V SGS1 and V SGS2 are used in driving a source-side selection gate line SGS in a memory block that is selected (which is hereinafter referred to as a “selected memory block MB”).
  • the signals V SGD2 and V SGD1 are used in driving a drain-side selection gate line SGD in a selected memory block MB.
  • the signal V SGOFF is used in driving source-side selection gate lines SGS and drain-side selection gate lines SGD in memory blocks MB that are not selected (which is hereinafter referred to as “unselected memory blocks MB”).
  • the address decoder circuit 130 outputs a signal V BAD for specifying a block address.
  • the boost circuit 140 A boosts the voltage from a power supply voltage, and transfers the boosted voltage to the word-line driving circuits 110 a and 110 b .
  • the boost circuit 140 B boosts the voltage from a power supply voltage to obtain a signal V RDEC , which is output to the first and second row decoder circuits 180 a and 180 b .
  • the boost circuit 140 C boosts the voltage from a power supply voltage to obtain a signal V ERA , which is output to the source-line driving circuit 160 .
  • the signal V ERA is used in erasing data from memory transistors MTr 1 to MTr 8 .
  • the sense amplifier circuit 150 reads information based on the voltage of a bit line BL.
  • the sense amplifier circuit 150 provides a bit line BL with a signal at the same voltage as that of a signal V SL of the source line SL (first and second source lines SLA and SLB).
  • the sense amplifier circuit 150 receives a signal V BAD input from the address decoder circuit 130 .
  • the source-line driving circuit 160 outputs a signal V SL for driving a source line SL (first and second source lines SLA and SLB).
  • the back-gate-line driving circuit 170 outputs a signal V BG for driving a back-gate line BG.
  • the first and second row decoder circuits 180 a and 180 b are provided, one for each memory block MB, respectively. Each first row decoder circuit 180 a is provided at one end in the row direction of a respective memory block MB. Each second row decoder circuit 180 b is provided at the other end in the row direction of a respective memory block MB.
  • Each first row decoder circuit 180 a selectively inputs signals V CGl ⁇ i> to V CG4 ⁇ i> to the gates of memory transistors MTr 1 to MTr 4 , based on the signal V BAD output from the address decoder circuit 130 .
  • the first row decoder circuit 180 a selectively inputs a signal V SGS2 ⁇ i> to the gates of the source-side selection transistors SSTr in the second column.
  • the first row decoder circuit 180 a selectively inputs a signal V SGD1 ⁇ i> to the gates of the drain-side selection transistors SDTr in the first column.
  • Each first row decoder circuit 180 a has a voltage conversion circuit 180 aa , first transfer transistors 181 a to 186 a , and second transfer transistors 187 a and 188 a .
  • the voltage conversion circuit 180 aa generates a signal V SELa ⁇ i> based on the received signals V BAD and V RDEC , which in turn is output to the gates of the first transfer transistors 181 a to 186 a .
  • the voltage conversion circuit 180 aa controls the gates of the second transfer transistors 187 a and 188 a based on the voltage of the received signal V BAD .
  • the gates of the first transfer transistors 181 a to 184 a receive the signal V SELa ⁇ i> from the voltage conversion circuit 180 aa .
  • the first transfer transistors 181 a to 184 a are connected between the word-line driving circuit 110 a and the word lines WL 1 to WL 4 .
  • the first transfer transistors 181 a to 184 a output signals V CG1 ⁇ i> to V CG4 ⁇ i> to the word lines WL 1 to WL 4 based on the signals V CG1 to V CG4 and V SELa ⁇ i> .
  • the first transfer transistor 185 a is connected between the selection-gate-line driving circuit 120 a and the source-side selection gate line SGS of the source-side selection transistors SSTr in the second column.
  • the first transfer transistor 185 a outputs a signal V SGS2 ⁇ i> to the source-side selection gate line SGS based on the signals V SGS2 and V SELa ⁇ i> .
  • the first transfer transistor 186 a is connected between the selection-gate-line driving circuit 120 a and the drain-side selection gate lines SGD of the drain-side selection transistors SDTr in the first column.
  • the first transfer transistor 186 a outputs a signal V SGD1 ⁇ i> to the drain-side selection gate lines SGD based on the signals V SGD1 and V SELa ⁇ i> .
  • the gates of the second transfer transistors 187 a and 188 a receive a signal from the voltage conversion circuit 180 aa .
  • the second transfer transistor 187 a has one end that is connected to the source-side selection gate line SGS of the source-side selection transistors SSTr in the second column, and the other end to which a signal V SGOFF is input.
  • the second transfer transistor 188 a has one end that is connected to the drain-side selection gate line SGD of the drain-side selection transistors SDTr in the first column, and the other end to which a signal V SGOFF is input.
  • Each second row decoder circuit 180 b selectively inputs signals V CG5 ⁇ i> to V CGB ⁇ i> to the gates of memory transistors MTr 5 to MTr 8 , based on the signal V BAD output from the address decoder circuit 130 .
  • the second row decoder circuit 180 b selectively inputs a signal V SGS1 ⁇ i> to the gates of the source-side selection transistors SSTr in the first column.
  • the second row decoder circuit 180 b selectively inputs a signal V SGD2 ⁇ i> to the gates of the drain-side selection transistors SDTr in the second column.
  • the second row decoder circuit 180 b selectively inputs a signal V BG ⁇ i> to the gates of the back-gate transistors BTr.
  • Each second row decoder circuit 180 b has a voltage conversion circuit 180 bb , first transfer transistors 181 b to 187 b , and second transfer transistors 188 b and 189 b .
  • the voltage conversion circuit 180 bb generates a signal V SELb ⁇ i> based on the voltages of the received signals V BAD and V RDEC , and outputs it to the gates of the first transfer transistors 181 b to 187 b .
  • the voltage conversion circuit 180 bb controls the gates of the second transfer transistors 188 b and 189 b based on the received signal V BAD .
  • the gates of the first transfer transistors 181 b to 187 b receive the signal V SELb ⁇ i> from a voltage conversion circuit 180 bb .
  • the first transfer transistors 181 b to 184 b are connected between the word-line driving circuit 110 b and the word lines WL 5 to WL 8 , respectively.
  • the first transfer transistors 181 b to 184 b input signals V CG5 ⁇ 1> to V CG8 ⁇ i> to the word lines WL 5 to WL 8 based on the signals V CG5 to V CG8 and V SELb ⁇ i> .
  • the first transfer transistor 185 b is connected between the selection-gate-line driving circuit 120 b and the source-side selection gate lines SGS of the source-side selection transistors SSTr in the first column.
  • the first transfer transistor 185 b outputs a signal V SGS1 ⁇ i> to the source-side selection gate lines SGS based on the signals V SGS1 and V SELb ⁇ i> .
  • the first transfer transistor 186 b is connected between the selection-gate-line driving circuit 120 b and the drain-side selection gate lines SGD of the drain-side selection transistors SDTr in the second column.
  • the first transfer transistor 186 b outputs a signal V SGD2 ⁇ i> to the drain-side selection gate lines SGD based on the signals V SGD2 and V SELb ⁇ i> .
  • the first transfer transistor 187 b is connected between the back-gate-line driving circuit 170 and the back-gate lines BG.
  • the first transfer transistor 187 b inputs a signal V BG ⁇ i> to the back-gate lines BG based on the signals V BG and V SELb ⁇ i> .
  • the gates of the second transfer transistors 188 b and 189 b receive signals from the voltage conversion circuit 180 bb .
  • the second transfer transistor 188 b has one end that is connected to the source-side selection gate lines SGS of the source-side selection transistors SSTr in the first column, and the other end to which a signal V SGOFF is input.
  • the second transfer transistor 189 b has one end that is connected to the drain-side selection gate lines SGD of the drain-side selection transistors SDTr in the second column, and the other end to which a signal V SGOFF is input.
  • the sequencer 190 inputs control signals to the word-line driving circuits 110 a and 110 b , the selection-gate-line driving circuits 120 a and 120 b , and the source-line driving circuit 160 .
  • each word-line driving circuit 110 a includes first to fourth word-line driving circuits 110 A to 110 D.
  • the first word-line driving circuit 110 A outputs a signal V CG1 .
  • the second word-line driving circuit 110 B outputs a signal V CG2 .
  • the third word-line driving circuit 110 C outputs a signal V CG3 .
  • the fourth word-line driving circuit 110 D outputs a signal V CG4 .
  • each word-line driving circuit 110 b includes first to fourth word-line driving circuits 110 A to 110 D.
  • the first word-line driving circuit 110 A outputs a signal V CG5 .
  • the second word-line driving circuit 110 B outputs a signal V CG6 .
  • the third word-line driving circuit 110 C outputs a signal V CG7 .
  • the fourth word-line driving circuit 110 D outputs a signal V CG8 .
  • each first word-line driving circuit 110 A has voltage conversion circuits 111 A to 111 C and transfer transistors 112 A to 112 C.
  • the voltage conversion circuits 111 A to 111 C have input terminals that receive control signals input from the sequencer 190 .
  • the voltage conversion circuits 111 A to 111 C have output terminals connected to the gates of the transfer transistors 112 A to 112 C.
  • the output terminals of the transfer transistors 112 A to 1120 are commonly connected.
  • the input terminal of the transfer transistor 112 A is connected to the output terminal of the boost circuit 140 A.
  • the input terminal of the transfer transistor 112 B is connected to the ground voltage Vss.
  • the input terminal of the transfer transistor 112 C is connected to the power supply voltage Vdd.
  • the second to fourth word-line driving circuits 110 B to 110 D have the same configuration as the first word-line driving circuit 110 A.
  • each selection-gate-line driving circuit 120 a 120 b includes first to third selection-gate-line driving circuits 120 A to 120 C.
  • the first selection-gate-line driving circuit 120 A outputs a signal V SGOFF .
  • the second selection-gate-line driving circuit 120 B outputs a signal V SGS1 (V SGS2 ).
  • the third selection-gate-line driving circuit 120 C outputs a signal V SGD2 (V SGD1 ).
  • the first selection-gate-line driving circuit 120 A has voltage conversion circuits 121 A and 1212 and transfer transistors 122 A and 122 B.
  • the voltage conversion circuits 121 A and 121 B have input terminals that receive signals from the sequencer 190 .
  • the voltage conversion circuits 121 A and 121 B have output terminals connected to the gates of the transfer transistors 122 A and 122 B.
  • the output terminals of the transfer transistors 122 A and 122 B are commonly connected.
  • the input terminal of the transfer transistor 122 A is connected to the ground voltage Vss.
  • the input terminal of the transfer transistor 122 B is connected to the power supply voltage Vdd.
  • the second and third selection-gate-line driving circuits 120 B and 1200 have the same configuration as the first selection-gate-line driving circuit 120 A.
  • the boost circuits 140 A to 140 C generate voltages higher than the power supply voltage Vdd by means of charge and discharge of capacitors. As illustrated in FIG. 5 , the boost circuits 140 A to 140 C have diodes 143 a to 143 n as well as charge and discharge circuits 144 a to 1441 . Note that the boost circuits 140 A to 140 C may have more diodes and charge and discharge circuits.
  • the diodes 143 a to 143 e are connected in series.
  • the diodes 143 f to 143 n are connected in series.
  • One end of the diode 143 a is connected to one end of the diode 143 f .
  • One end of the diode 143 e is connected to one end of the diode 143 n.
  • the charge and discharge circuits 144 a to 144 d have their output terminals connected between the diodes 143 a to 143 e .
  • the charge and discharge circuits 144 e to 1441 have their output terminals connected between the diodes 143 f to 143 n .
  • Each of the charge and discharge circuits 144 a to 144 l involves an AND circuit 144 A, an inverter 144 B, and a capacitor 144 C connected in series.
  • the input terminals at one ends of the AND circuits 144 A alternately receive signals ⁇ 1 or ⁇ 2 .
  • the input terminals at the other ends of the AND circuits 144 A receive signals V PASS .
  • the input terminals at one ends of the AND circuits 144 A alternately receive signals ⁇ 1 or ⁇ 2 .
  • the input terminals at the other ends of the AND circuits 144 A receive signals V PRG .
  • FIGS. 6A and 6B are timing charts illustrating operations of the boost circuits 140 A to 140 C.
  • the boost circuits 140 A to 140 C set signals V PASS or signals V PRG to the power supply voltage Vdd or the ground voltage Vss, depending on the generated signals.
  • the source-line driving circuit 160 has voltage conversion circuits 161 A to 161 C and transfer transistors 162 A to 162 C.
  • the voltage conversion circuits 161 A to 161 C and the transfer transistors 162 A to 162 C are connected in the same manner as the voltage conversion circuits 111 A to 111 C and transfer transistors 112 A to 112 C in the word-line driving circuit 110 a .
  • the voltage conversion circuits 161 A to 161 C have input terminals that receive signals input from the sequencer 190 .
  • the input terminal of the transfer transistor 162 A is connected to the output terminal of the boost circuit 140 C.
  • the input terminal of the transfer transistor 162 B is connected to the ground voltage Vss.
  • the input terminal of the transfer transistor 1620 is connected to the power supply voltage Vdd.
  • the sense amplifier circuit 150 has a plurality of selection circuits 151 and voltage conversion circuits 152 A and 152 B.
  • Each selection circuit 151 selectively connects a bit line BL to a source lines SL, and sets the bit line BL to have the same potential as the source line SL.
  • each selection circuit 151 has a page buffer 151 a and transistors 151 b and 151 c .
  • the page buffer 151 a has one end connected to one end of the transistor 151 b that receives a signal from a bit line BL, and inputs an output based on that signal to the input/output circuit 100 and the address decoder circuit 130 .
  • the transistor 151 b has the other end connected to the bit line BL.
  • the transistor 151 b also has a control gate that receives a signal VCUT output from the voltage conversion circuit 152 A.
  • the transistor 151 c has one end connected to the bit line BL.
  • the transistor 151 c has the other end connected to a source line SL.
  • the transistor 151 c also has a control gate that receives a signal VRST output from the voltage conversion circuit 152 B.
  • the voltage conversion circuit 152 A receives a signal from the sequencer 190 and outputs a signal VCUT based on that signal.
  • the voltage conversion circuit 152 B receives a signal from the sequencer 190 and outputs a signal VEST based on that signal.
  • FIG. 9 is a schematic perspective view illustrating a part of a memory cell array AR 1 in the non-volatile semiconductor storage device in the first embodiment.
  • FIG. 10 is a partial cross-sectional view of FIG. 9 .
  • a memory cell array AR 1 is provided on a substrate 10 .
  • the memory cell array AR 1 has a back-gate transistor layer 20 , a memory transistor layer 30 , a selection transistor layer 40 , and a wiring layer 50 .
  • the back-gate transistor layer 20 functions as back-gate transistors BTr.
  • the memory transistor layer 30 functions as memory transistors MTr 1 to MTr 8 (memory strings MS).
  • the selection transistor layer 40 functions as source-side selection transistors SSTr and drain-side selection transistors SDTr.
  • the wiring layer functions as source lines SL and bit lines BL.
  • the back-gate transistor layer 20 has a back-gate hole 22 .
  • the back-gate hole 22 is formed to dig into the back-gate conductive layer 21 .
  • Each back-gate hole 22 is formed in a substantially rectangular shape, as viewed from above, having its longitudinal direction in the column direction.
  • the back-gate holes 22 are formed in a matrix form in the row and column directions.
  • the memory transistor layer 30 is formed on the back-gate transistor layer 20 .
  • the memory transistor layer 30 has word-line conductive layers 31 a to 31 d .
  • the word-line conductive layers 31 a to 31 d are laminated with interlayer insulation layers (not illustrated) sandwiched therebetween.
  • the word-line conductive layers 31 a to 31 d are formed in a stripe pattern extending in the row direction at a certain pitch in the column direction.
  • the word-line conductive layers 31 a to 31 d comprise polysilicon (p-Si).
  • the word-line conductive layers 31 a to 31 d function as word lines WL 1 to WL 8 .
  • the word-line conductive layers 31 a to 31 d function as the control gates of memory transistors MTr 1 to MTr 8 .
  • the back-gate transistor layer 20 and the memory transistor layer 30 have a block insulation layer 33 a , an electric charge storage layer 33 b , a tunnel insulation layer 33 c , and a U-shaped semiconductor layer 34 .
  • the U-shaped semiconductor layer 34 functions as the body of a memory string MS.
  • the block insulation layers 33 a and the tunnel insulation layers 33 c comprise silicon oxide (SiO 2 ).
  • the electric charge storage layers 33 b comprise silicon nitride (SiN).
  • the U-shaped semiconductor layers 34 comprise polysilicon (p-Si).
  • the block insulation layers 33 a , the electric charge storage layers 33 b , the tunnel insulation layers 33 c , and the U-shaped semiconductor layers 34 function as the MONOS of the memory transistors MTr 1 to MTr 8 .
  • the tunnel insulation layer 33 c is formed to surround the joining portion 34 b .
  • the back-gate conductive layer 21 is formed to surround the joining portion 34 b.
  • the tunnel insulation layer 33 c is formed to surround the columnar portions 34 a .
  • the electric charge storage layer 33 b is formed to surround the tunnel insulation layer 33 c .
  • the block insulation layer 33 a is formed to surround the electric charge storage layer 33 b .
  • the word-line conductive layers 31 a to 31 d are formed to surround the block insulation layer 33 a and the columnar portions 34 a.
  • Each source-side conductive layer 41 a is formed above one of the columnar portions 34 a included in a respective U-shaped semiconductor layer 34
  • each drain-side conductive layer 41 b is formed above the other of the columnar portions 34 a included in the U-shaped semiconductor layer 34 .
  • the selection transistor layer 40 has a source-side hole 42 a and a drain-side hole 42 b .
  • the source-side hole 42 a is formed to penetrate the source-side conductive layer 41 a .
  • the source-side hole 42 a is formed at a position matching the memory hole 32 .
  • the drain-side hole 42 b is formed to penetrate the drain-side conductive layer 41 b .
  • the drain-side hole 42 b is formed at a position matching the memory hole 32 .
  • the source-side gate insulation layers 43 a and the drain-side gate insulation layers 43 b comprise silicon oxide (SiO 2 ).
  • the source-side columnar semiconductor layers 44 a and the drain-side columnar semiconductor layers 44 b comprise polysilicon (p-Si).
  • the source-side gate insulation layer 43 a is formed to surround the source-side columnar semiconductor layer 44 a .
  • the source-side conductive layer 41 a is formed to surround the source-side gate insulation layer 43 a and the source-side columnar semiconductor layer 44 a .
  • the drain-side gate insulation layer 43 b is formed to surround the drain-side columnar semiconductor layer 44 b .
  • the drain-side conductive layer 41 b is formed to surround the drain-side gate insulation layer 43 b and the drain-side columnar semiconductor layer 44 b.
  • the wiring layer 50 is formed on the selection transistor layer 40 .
  • the wiring layer 50 has a source-line layer 51 , a plug layer 52 , and a bit-line layer 53 .
  • the source-line layer 51 is formed in a plate-like form extending in the row direction.
  • the source-line layer 51 is formed in contact with the top surfaces of a pair of source-side columnar semiconductor layers 44 a adjacent in the column direction.
  • the plug layer 52 is formed to come in contact with the top surface of the drain-side columnar semiconductor layer 44 b and extend in a vertical direction to the substrate 10 .
  • the bit-line layers 53 are formed in a stripe pattern extending in the column direction at a certain pitch in the row direction.
  • the control circuit AR 2 raises the source-side selection gate lines SGS and the drain-side selection gate lines SGD to a certain voltage Vdd-Vth, as well as the source lines SL and the bit lines BL to a power supply voltage Vdd (step S 11 ).
  • the power supply voltage Vdd is a voltage that is higher than the certain voltage Vdd-Vth by Vth and that causes a GIDL current due to the potential difference Vth.
  • a GIDL current is caused by creating a higher electric field at the end of the source-side conductive layer 41 a (the source-side selection gate line SGS) on the source-line layer 51 (the source line SL) side.
  • a GIDL current is also caused by creating a higher electric field at the end of the drain-side conductive layer 41 b (the drain-side selection gate line SGD) on the bit-line layer 53 (the bit line BL) side. Due to the GIDL currents, holes H and electrons E are generated.
  • step S 11 as indicated by the label “s 11 ” in FIG. 12 , the control circuit AR 2 raises the word lines WL 1 to WL 8 and the back-gate line BG to the power supply voltage Vdd.
  • the control circuit AR 2 boosts the source line SL and the bit line BL from the power supply voltage Vdd to an erase voltage Vera (step S 12 ).
  • the other wirings are maintained in the same controlled state as that described in step S 11 .
  • the source-side selection gate line SGS, the drain-side selection gate line SGD, the word lines WL 1 to WL 8 , and the back-gate line BG are set in floating states. Then, the respective potentials of the source-side selection gate line SGS, the drain-side selection gate line SGD, the word lines WL 1 to WL 8 , and the back-gate line BG rise due to the coupling with the body of the memory string MS.
  • the control circuit AR 2 sets the word lines WL 1 to WL 8 and the back-gate line BG at the ground voltage Vss (step S 13 ), and feeds the holes H caused by the GIDL currents into the gates of the memory transistors MTr 1 to MTr 8 . In this way, data is erased.
  • FIGS. 14A and 14B are timing charts illustrating an erase operation.
  • a signal V BAD is inverted as illustrated in FIG. 14A .
  • signals V SELa ⁇ i> and V SELb ⁇ i> rise from the ground voltage Vss to the power supply voltage Vdd in the selected memory block MB. That is, the first transfer transistors 181 a to 186 a ( 181 b to 187 b ) are set in ON states.
  • the ground voltage Vss is applied to the gates of the second transfer transistors 187 a and 188 a ( 188 b and 189 b ). This allows the second transfer transistors 187 a and 188 a ( 188 b and 189 b ) to be set in OFF states.
  • the word lines WL 1 to WL 4 and WL 5 to WL 8 are set in floating states in the unselected memory blocks MB.
  • the source-side selection gate line SGS and the drain-side selection gate line SGD are connected to the selection-gate-line driving circuits 120 a and 120 b via the second transfer transistors 188 a , 187 a , 188 b , and 189 b .
  • the back-gate line BG is set in a floating state.
  • the signals V SGS1 , V SGS2 , V SGD1 , V SGD2 , V SGOFF , V CG1 to V CG8 , and V BG are raised from the ground voltage Vss to the power supply voltage Vdd.
  • the signals V SGD1 ⁇ i> , V SGD2 ⁇ i> , V SGS1 ⁇ i> , V SGS2 ⁇ i> , V CG1 ⁇ i> to V CG8 ⁇ i> , and V BG ⁇ i> are raised to a certain voltage Vdd-Vth in the selected memory block MB.
  • the signal V SL is raised to the power supply voltage Vdd at the source-line driving circuit 160 .
  • the signal VRST is raised to a voltage Vpp at the sense amplifier circuit 150 . Due to the change of the signal VRST, at time t 12 , the voltage of the signal V BL is set at the power supply voltage Vdd.
  • the signal V SL begins to rise toward the erase voltage Vera at the source-line driving circuit 160 . Accordingly, the signal V BL also begins to rise toward the erase voltage Vera.
  • the signals V CG1 ⁇ i> to V CG8 ⁇ i> and V BG ⁇ i> are set at the ground voltage Vss in the selected memory block MB.
  • the holes H caused by the GIDL currents are fed into the gates of the memory transistors MTr 1 to MTr 8 , after which execution of the erase operation begins.
  • the following cycle will occur: (1) the source line SL and the bit line BL are boosted; (2) GIDL currents are caused between the source line SL and the source-side selection gate line SGS, as well as between the bit line BL and the drain-side selection gate line SGD; (3) the potential of the body of the memory string MS rises; and (4) the respective potentials of the source-side selection gate line SGS and the drain-side selection gate line SGD rise due to the coupling with the body of the memory string MS.
  • the potential of the body of the memory string MS, the potential of the source-side selection gate line SGS, and the potential of the drain-side selection gate line SGD also rise.
  • the non-volatile semiconductor storage device in the first embodiment does not need to boost the corresponding source-side selection gate line SGS and drain-side selection gate line SGD in time with the source line SL and the bit line BL being boosted. That is, this non-volatile semiconductor storage device does not require any circuits for controlling the timing when source-side selection gate lines SGS and drain-side selection gate lines SGD are boosted. Therefore, it may suppress the increase in its occupation area.
  • FIG. 15 is a circuit diagram of the non-volatile semiconductor storage device according to the second embodiment.
  • FIG. 16 is a circuit diagram of a sense amplifier circuit 150 a according to the second embodiment. Note that the same reference numerals represent the same components as the first embodiment, and description thereof will be omitted in the second embodiment.
  • the non-volatile semiconductor storage device in the second embodiment is only different from the first embodiment in the sense amplifier circuit 150 a.
  • each transistor 151 c included in the sense amplifier circuit 150 a according to the second embodiment.
  • Each transistor 151 c has one end connected to a bit line BL and the other end to the ground.
  • a GIDL current is caused by creating a higher electric field at the end of the source-side conductive layer 41 a (a source-side selection gate line SGS) on the source-line layer 51 (the source line SL) side, as indicated by a label “A” in FIG. 17 . That is, according to the second embodiment, as indicated by time t 12 to t 15 in FIG. 18 , the voltage of the source line SL is only controlled, without controlling the voltage of the bit line BL.
  • the erase operation in the second embodiment is otherwise the same as that described in the first embodiment.
  • the non-volatile semiconductor storage device has the same features and advantages as the first embodiment.
  • FIG. 19 is a circuit diagram of the non-volatile semiconductor storage device in the third embodiment. Note that the same reference numerals represent the same components as the first and second embodiments, and description thereof will be omitted in the third embodiment.
  • the non-volatile semiconductor storage device in the third embodiment has a memory cell array AR 1 a and a control circuit ARa 2 that are different from the first and second embodiments.
  • the memory cell array AR 1 a has m columns of memory blocks MBa.
  • Each memory block MBa comprises n rows and 4 columns of memory strings MSa, source-side selection transistors SSTra each connected to one end of the memory string MSa, and drain-side selection transistors SDTra each connected to the other end of the memory string MSa.
  • the first column is denoted by (1), the second column by (2), the third column by (3), and the fourth column by (4).
  • each memory string MSa has memory transistors MTra 1 to MTra 4 .
  • the memory transistors MTra 1 to MTra 4 are connected in series.
  • the memory transistors MTra 1 to MTra 4 which include a MONOS structure, cause electric charges to be accumulated in respective control gates.
  • each source-side selection transistor SSTra is connected to the source of a memory transistor MTra 1 .
  • the source of each source-side selection transistor SSTra is connected to a first source line SLAa.
  • the control gate of each source-side selection transistor SSTra is connected to a source-side selection gate line SGSa.
  • each first source line SLAa is provided in common to the sources of the source-side selection transistors SSTra aligned in the row direction, and formed to extend in the row direction across a plurality of memory strings MSa.
  • the first source lines SLAa aligned in the column direction are commonly connected to a single second source line SLBa extending in the column direction.
  • Each source-side selection gate line SGSa is provided in common to the control gates of the source-side selection transistors SSTra aligned in a matrix form in the row and column directions.
  • each drain-side selection transistor SDTra is connected to one end of a memory transistor MTra 4 .
  • the other end of each drain-side selection transistor SDTra is connected to a bit line BLa.
  • the control gate of each drain-side selection transistor SDTra is connected to a drain-side selection gate line SGDa.
  • each bit line BLa is provided in common to one ends of the drain-side selection transistors SDTra aligned in the column direction, and formed to extend in the column direction across a plurality of memory blocks MBa.
  • Each drain-side selection gate line SGDa is provided in common to the control gates of the drain-side selection transistors SDTra aligned in the row direction, and formed to extend in the row direction across a plurality of memory strings MSa.
  • a control circuit AR 2 a has an input/output circuit 100 , a word-line driving circuit 110 c , a selection-gate-line driving circuit 120 a ′, an address decoder circuit 130 , boost circuits 140 A to 140 C, a sense amplifier circuit 150 , a source-line driving circuit 160 , a first row decoder circuit 180 c , a second row decoder circuit 180 d , and a sequencer 190 .
  • the word-line driving circuit 110 c outputs signals V CG1 to V CG4 for driving word lines WLa 1 to WLa 4 .
  • the word-line driving circuit 110 c has substantially the same configuration as the word-line driving circuits 110 a and 110 b in the first and second embodiments (see FIG. 3 ).
  • the selection-gate-line driving circuit 120 a ′ outputs signals V SGS , V SGD1 to V SGD4 , and V SGOFF .
  • the signal V SGS is used in driving a source-side selection gate line SGSa in a selected memory block MBa.
  • the signals V SGD1 to V SGD4 are used in driving drain-side selection gate lines SGDa 1 to SGDa 4 in a selected memory block MBa.
  • the signal V SGOFF is used in driving source-side selection gate lines SGSa and drain-side selection gate lines SGDa 1 to SGDa 4 in unselected memory blocks MBa.
  • the first and second row decoder circuits 180 c and 180 d are provided, one for each memory block MBa, respectively. Each first row decoder circuit 180 c is provided at one end in the row direction of a respective memory block MBa. Each second row decoder circuits 180 d is provided at the other end in the row direction of a respective memory block MBa.
  • Each first row decoder circuit 180 c selectively inputs signals V CG1 ⁇ i> to V CG4 ⁇ i> to the gates of memory transistors MTra 1 to MTra 4 , based on a signal V BAD output from the address decoder circuit 130 .
  • Each first row decoder circuit 180 c has a voltage conversion circuit 180 cc and first transfer transistors 181 c to 184 c .
  • the voltage conversion circuit 180 cc generates a signal V SELL ⁇ i> based on the received signals V BAD and V RDEC , which in turn is output to the gates of the first transfer transistors 181 c to 184 c.
  • the gates of the first transfer transistors 181 c to 184 c receive the signal V SELL ⁇ i> from the voltage conversion circuit 180 cc.
  • the first transfer transistors 181 c to 184 c are connected between the word-line driving circuit 110 c and the word lines WLa 1 to WLa 4 .
  • the first transfer transistors 181 c to 184 c output signals V CG1 ⁇ 1> to V CG4 ⁇ i> to the word lines WLa 1 to WLa 4 based on the signals V CG1 to V CG4 and V SELL ⁇ i> .
  • Each second row decoder circuit 180 d has a voltage conversion circuit 180 dd , first transfer transistors 181 d to 185 d , and second transfer transistors 181 d ′ to 185 d ′.
  • the voltage conversion circuit 180 dd generates a signal V SELR ⁇ i> based on the voltages of the received signals V BAD and V RDEC , and outputs it to the gates of the first transfer transistors 181 d to 185 d .
  • the voltage conversion circuit 180 dd controls the gates of the second transfer transistors 181 d ′ to 185 d ′ based on the received signals V BAD and V RDEC .
  • the gates of the first transfer transistors 181 d to 185 d receive the signal V SELR ⁇ i> from the voltage conversion circuit 180 dd .
  • the first transfer transistor 181 d is connected between the selection-gate-line driving circuit 120 a ′ and a source-side selection gate line SGSa.
  • the first transfer transistors 182 d to 185 d are connected between the selection-gate-line driving circuit 120 a ′ and the drain-side selection gate lines SGDa aligned in tour columns, respectively.
  • the first transfer transistor 181 d inputs a signal V SGS ⁇ i> to the source-side selection gate line SGSa based on the signals V SGS and V SELR ⁇ i> .
  • the first transfer transistors 182 d to 185 d input signals V SGD1 ⁇ i> to V SGD4 ⁇ i> to the drain-side selection gate lines SGDa aligned in four columns based on the signals V SGD1 to V SGD4 and V SELR ⁇ i> .
  • the gates of the second transfer transistors 181 d ′ to 185 d ′ receive a signal from the voltage conversion circuit 180 dd .
  • the second transfer transistor 181 d ′ is connected between the selection-gate-line driving circuit 120 a ′ and the source-side selection gate line SGSa.
  • the second transfer transistors 182 d ′ to 185 d ′ are connected between the selection-gate-line driving circuit 120 a ′ and the drain-side selection gate lines SGDa aligned in four columns.
  • the second transfer transistor 181 d ′ inputs a signal V SGS ⁇ i> to the source-side selection gate line SGSa based on the signal V SGOFF .
  • the second transfer transistors 182 d ′ to 185 d ′ input signals V SGD1 ⁇ i> to V SGD4 ⁇ i> to the drain-side selection gate lines SGDa aligned in four columns.
  • FIG. 21 is a schematic perspective view illustrating a part of a memory cell array AR 1 a in the non-volatile semiconductor storage device according to the third embodiment.
  • FIG. 22 is a partial cross-sectional view of FIG. 21 .
  • the memory cell array AR 1 a is provided on a substrate 10 a .
  • the memory cell array AR 1 a has a source-side selection transistor layer 60 , a memory transistor layer 70 , a drain-side selection transistor layer 80 , and a wiring layer 90 .
  • the substrate 10 a functions as first source lines SLAa (source lines SLa).
  • the source-side selection transistor layer 60 functions as source-side selection transistors SSTra.
  • the memory transistor layer 70 functions as memory transistors MTra 1 to MTra 4 (memory strings MSa).
  • the drain-side selection transistor layer 80 functions as drain-side selection transistors SDTra.
  • the wiring layer 90 functions as bit lines BLa.
  • the substrate 10 a has a diffusion layer 11 a on its surface.
  • the diffusion layer 11 a functions as first source lines SLAa (source lines SLa).
  • the source-side selection transistor layer 60 has source-side conductive layers 61 .
  • Each source-side conductive layer 61 is formed in a plate-like form expanding in the row and column directions parallel to the substrate 10 a .
  • the source-side conductive layers 61 are separated for each memory block MBa.
  • the source-side conductive layers 61 comprise polysilicon (p-Si). Each source-side conductive layer 61 functions as a source-side selection gate line SGSa. Each source-side conductive layer 61 also functions as the gate of a source-side selection transistor SSTra.
  • the source-side selection transistor layer 60 also has a source-side hole 62 .
  • the source-side hole 62 is formed to penetrate the source-side conductive layer 61 .
  • the source-side holes 62 are formed at positions matching the diffusion layer 11 a in a matrix form in the row and column directions.
  • the source-side selection transistor layer 60 also has a source-side gate insulation layer 63 and a source-side columnar semiconductor layer 64 .
  • the source-side gate insulation layer 63 is formed with a certain thickness on a sidewall of the source-side hole 62 .
  • the source-side columnar semiconductor layer 64 is formed to come in contact with a side surface of the source-side gate insulation layer 63 and fill up the source-side hole 62 .
  • the source-side columnar semiconductor layer 64 is formed in a columnar shape extending in a vertical direction to the substrate 10 a and in contact with the diffusion layer 11 a.
  • the source-side gate insulation layer 63 is formed to surround the source-side columnar semiconductor layer 64 .
  • each source-side conductive layer 61 is formed to surround the source-side gate insulation layer 63 .
  • the memory transistor layer 70 has laminated word-line conductive layers 71 a to 71 d .
  • Each of the word-line conductive layers 71 a to 71 d is formed in a plate-like form expanding in the row and column directions parallel to the substrate 10 a .
  • the word-line conductive layers 71 a to 71 d are separated for each memory block MBa.
  • the word-line conductive layers 71 a to 71 d comprise polysilicon (p-Si).
  • the word-line conductive layers 71 a to 71 d function as word lines WLa 1 to WLa 4 .
  • the word-line conductive layers 71 a to 71 d also function as the gates of memory transistors MTra 1 to MTra 4 .
  • the memory transistor layer 70 also has a memory hole 72 .
  • the memory hole 72 is formed to penetrate the word-line conductive layers 71 a to 71 d .
  • the memory holes 72 are formed at positions matching the source-side holes 62 in a matrix form in the row and column directions.
  • the memory transistor layer 70 also has a block insulation layer 73 a , an electric charge storage layer 73 b , a tunnel insulation layer 73 c , and a memory columnar semiconductor layer 74 .
  • the memory columnar semiconductor layer 74 functions as the body of a memory string MSa.
  • the block insulation layer 73 a is formed with a certain thickness on a sidewall of the memory hole 72 .
  • the electric charge storage layer 73 b is formed with a certain thickness on a sidewall of the block insulation layer 73 a .
  • the tunnel insulation layer 73 c is formed with a certain thickness on a sidewall of the electric charge storage layer 73 b .
  • the memory columnar semiconductor layer 74 is formed to come in contact with a sidewall of the tunnel insulation layer 73 c and fill up the memory hole 72 .
  • the memory columnar semiconductor layer 74 is formed to come in contact with the top surface of the source-side columnar semiconductor layer 64 and the bottom surface of a drain-side columnar semiconductor layer 84 described below, and extend in a vertical direction to the substrate 10 a.
  • the block insulation layers 73 a and the tunnel insulation layers 73 c comprise silicon oxide (SiO 2 ).
  • the electric charge storage layers 73 b comprise silicon nitride (SiN).
  • the memory columnar semiconductor layers 74 comprise polysilicon (p-Si).
  • the tunnel insulation layer 73 c is formed to surround the memory columnar semiconductor layer 74 .
  • the electric charge storage layer 73 b is formed to surround the tunnel insulation layer 73 c .
  • the block insulation layer 73 a is formed to surround the electric charge storage layer 73 b .
  • the word-line conductive layers 71 a to 71 d is formed to surround the block insulation layer 73 a.
  • the drain-side selection transistor layer 80 has a drain-side conductive layer 81 .
  • the drain-side conductive layer 81 is formed in a stripe pattern extending in the row direction at a certain pitch in the column direction.
  • the drain-side conductive layers 81 comprise polysilicon (p-Si). Each drain-side conductive layer 81 functions as a drain-side selection gate line SGDa. Each drain-side conductive layer 81 also functions as the gate of a drain-side selection transistor SDTra.
  • the drain-side selection transistor layer 80 also has a drain-side hole 82 .
  • the drain-side hole 82 is formed to penetrate the drain-side conductive layer 81 .
  • the drain-side holes 82 are formed at positions matching the memory holes 72 in a matrix form in the row and column directions.
  • the drain-side selection transistor layer 80 also has a drain-side gate insulation layer 83 and a drain-side columnar semiconductor layer 84 .
  • the drain-side gate insulation layer 83 is formed with a certain thickness on a sidewall of the drain-side hole 82 .
  • the drain-side columnar semiconductor layer 84 is formed in contact with a sidewall of the drain-side gate insulation layer 83 so as to fill up the drain-side hole 82 .
  • the drain-side columnar semiconductor layer 84 is formed to extend in a vertical direction to the substrate 10 a so as to come in contact with the top surface of the memory columnar semiconductor layer 74 .
  • the drain-side gate insulation layers 83 comprise silicon oxide (SiO 2 ).
  • the drain-side columnar semiconductor layers 84 comprise polysilicon (p-Si).
  • the wiring layer 90 has a bit-line layer 91 .
  • the bit-line layers 91 are formed in a stripe pattern extending in the column direction at a certain pitch in the row direction.
  • the bit-line layer 91 is formed in contact with the top surface of the drain-side columnar semiconductor layer 84 .
  • the bit-line layers 91 comprise polysilicon (p-Si). Each bit-line layer 91 functions as a bit line BLa.
  • a GIDL current is caused by creating a higher electric field at the end of a source-side conductive layer 61 (a source-side selection gate line SGSa) on the diffusion layer 11 a (a source line SLa) side.
  • a GIDL current is also caused by creating a higher electric field at the end of a drain-side conductive layer 81 (a drain-side selection gate line SGDa) on the bit-line layer 91 (a bit line BLa) side.
  • the erase operation in the third embodiment is otherwise the same as that described in the first embodiment.
  • the non-volatile semiconductor storage device has the same features and advantages as the first embodiment.
  • FIG. 24 is a circuit diagram of the non-volatile semiconductor storage device in the fourth embodiment. Note that the same reference numerals represent the same components as the first to third embodiments, and description thereof will be omitted in the fourth embodiment.
  • the non-volatile semiconductor storage device in the fourth embodiment has a control circuit AR 2 b that is different from the first to third embodiments.
  • the control circuit AR 2 b has selection-gate-line driving circuits 120 c and 120 d , a boost circuit 140 D, a source-line driving circuit 160 a , and first and second row decoder circuits 180 e and 180 f , instead of the selection-gate-line driving circuits 120 a and 120 b , the boost circuit 140 C, the source-line driving circuit 160 , and the first and second row decoder circuits 180 a and 180 b in the first to third embodiments.
  • the control circuit AR 2 b also has a boost circuit 140 E in addition to the configuration of the second embodiment. In this respect, the control circuit AR 2 b according to the fourth embodiment is different from the first to third embodiments.
  • each selection-gate-line driving circuit 120 c 120 d has first to third selection-gate-line driving circuits 120 D to 120 F.
  • the first selection-gate-line driving circuit 120 D outputs a signal V SGOFF .
  • the second selection-gate-line driving circuit 120 E outputs a signal V SGS1 (V SGS2 ).
  • the third selection-gate-line driving circuit 120 F outputs a signal V SGD2 (V SGD1 ).
  • the signals V SGOFF , V SGS1 (V SGS2 ), and V SGD2 (V SGD1 ) have the same potentials as the ground voltage Vss, the power supply voltage Vdd, and the signal Ve 2 , respectively.
  • each first selection-gate-line driving circuit 120 D has a first circuit 1210 and a second circuit 122 D.
  • the output terminal of the first circuit 121 D is connected to the output terminal of the second circuit 122 D.
  • the first circuit 121 D receives a signal Ve 2 from the boost circuit 140 D and a signal ERASE from the sequencer 190 . If the signal ERASE is in a “High” state, then the first circuit 121 D outputs the received signal Ve 2 .
  • the signal ERASE is set in a “High” state when performing erase operation.
  • the second circuit 122 D receives signals READ, SAi, ERASE, and PROGRAM from the sequencer 190 .
  • the signal READ is set in a “High” state when performing read operation.
  • the signal PROGRAM is set in a “High” state when performing write operation.
  • the second circuit 122 D outputs a signal at the power supply voltage Vdd or the ground voltage Vss based on the received signal. If the signals READ, SAi, and ERASE are in “High” states, then the second circuit 122 D outputs a signal at the power supply voltage Vdd. If the signals PROGRAM and ERASE are in a “Low” state, and if the signals READ and SAi are in “High” states, then the second circuit 1220 outputs a signal at the ground voltage Vss.
  • each boost circuit 140 D has an oscillation circuit 141 D, a first signal generation circuit 142 D, a second signal generation circuit 143 D, and a third signal generation circuit 144 D.
  • the oscillation circuit 141 D is a ring oscillator including a NOR circuit 141 Da and inverter circuits 141 Db to 141 De.
  • the oscillation circuit 141 D outputs an oscillation signal Vos based on a signal bEN from the third signal generation circuit 144 D.
  • the oscillation circuit 141 D outputs an oscillation signal Vos only when the signal bEN is in a “Low” state, and does not output an oscillation signal Vos when the signal bEN is in a “High” state.
  • the first signal generation circuit 142 D boosts the voltage of the signal Ve 1 based on the oscillation signal Vos from the oscillation circuit 141 D.
  • the first signal generation circuit 142 D switches between an operational state and a stop state depending on the oscillation signal Vos from the oscillation circuit 141 D.
  • the voltage of the signal Ve 1 is set at the ground voltage Vss or the power supply voltage Vdd.
  • the voltage of the signal Ve 1 is boosted from the power supply voltage Vdd to an erase voltage Vera 1 .
  • the signal Ve 1 is output to the source-line driving circuit 160 a.
  • the first signal generation circuit 142 D has a charge pump circuit 142 Da and a transistor 142 Db.
  • the charge pump circuit 142 Da boosts the signal Ve 1 from the power supply voltage Vdd to the erase voltage Vera 1 based on the oscillation signal Vos.
  • the transistor 142 Db has one end to which the power supply voltage Vdd is supplied.
  • the transistor 142 Db has a gate to which a signal RST 1 is input from the sequencer 190 , and the other end that is connected to the output terminal of the charge pump circuit 142 Da. If the signal RST 1 is in a “High” state, then the transistor 142 Db turns to an “ON” state. As a result, the signal Ve 1 is fixed at the power supply voltage Vdd.
  • the second signal generation circuit 143 D generates a signal Ve 2 based on the signal Ve 1 from the first signal generation circuit 142 D.
  • the second signal generation circuit 143 D switches between an operational state and a non-operational state depending on the signal bEN from the third signal generation circuit 144 D.
  • the voltage of the signal Ve 2 is set at the ground voltage Vss or the power supply voltage Vdd.
  • the voltage of the signal Ve 2 is boosted from the power supply voltage Vdd to a voltage Vera 2 (Vera 2 ⁇ Vera 1 ) after a certain delay time has elapsed since the signal Ve 1 is boosted.
  • the signal Ve 2 is boosted depending upon the boost of the signal Ve 1 .
  • the signal Ve 2 is output to the selection-gate-line driving circuits 120 c and 120 d.
  • the second signal generation circuit 143 D has a delay circuit 143 Da, a switch circuit 143 Db, and a transistor 143 Dc.
  • the delay circuit 143 Da delays the signal Ve 1 by a certain period of time and reduces the voltage of the signal Ve 1 by a certain amount, thereby generating a signal.
  • the switch circuit 143 Db controls whether or not to output the signal from the delay circuit 143 Da as a signal Ve 2 , based on the output signal bEN of the third signal generation circuit 144 D.
  • the switch circuit 143 Db has a level shifter circuit 143 Db 1 and a transistor 143 Db 2 .
  • the level shifter circuit 143 Db 1 outputs the received signal Ve 1 when the signal bEN is in a “Low” state.
  • the transistor 143 Db 2 has one end connected to the output terminal of the delay circuit 143 Da.
  • the transistor 143 Db 2 has a gate connected to the output terminal of the level shifter circuit 143 Db 1 .
  • the transistor 143 Db 2 turns to an “ON” state when the signal from the level shifter circuit 143 Db 1 is in a “High” state.
  • the transistor 143 Dc has a source connected to the output terminal of the switch circuit 143 Db (the source of the transistor 143 Db 2 ).
  • the transistor 143 Dc has a drain to which the power supply voltage Vdd is applied, and a gate that receives a signal RST 2 input from the sequencer 190 . If the signal RST 2 is in a “High” state, then the transistor 143 Dc turns to an “ON” state. As a result, the voltage of the output terminal of the switch circuit 143 Db is fixed at the power supply voltage Vdd.
  • the third signal generation circuit 144 D outputs a signal bEN.
  • the third signal generation circuit 144 D generates a signal Va based on the signal Ve 2 .
  • the signal Va has a voltage resulting from reducing the voltage of the signal Ve 2 by a certain amount.
  • the third signal generation circuit 144 D compares the voltage of the signal Va with a reference potential (reference voltage) Vref to output a signal bEN.
  • the signal Va has a certain relation to the signal Ve 1 .
  • the third signal generation circuit 1440 has a voltage drop circuit 144 Da, a reference potential generation circuit 144 Db, and a differential amplifier circuit 144 Dc.
  • the voltage drop circuit 144 Da generates a signal Va at a voltage resulting from reducing the voltage of the signal Ve 2 by a certain amount.
  • the input terminal of the voltage drop circuit 1440 a is connected to the output terminal of the switch circuit 143 Db (the source of the transistor 143 Db 2 ) in the second signal generation circuit 143 D.
  • the output terminal of the voltage drop circuit 144 Da is connected to one input terminal of the differential amplifier circuit 144 Dc.
  • the reference potential generation circuit 144 Db generates a reference potential Vref to be input to the other terminal of the differential amplifier circuit 144 Dc.
  • the differential amplifier circuit 144 Dc compares the signal Va with the signal Vref to output a signal bEN.
  • the boost circuit 140 E generates a signal Vhh resulting from boosting the power supply voltage Vdd to a certain voltage. As illustrated in FIG. 24 , the boost circuit 140 E inputs the signal Vhh to the first and second row decoder circuits 180 e and 180 f.
  • the source-line driving circuit 160 a receives the signal Ve 1 input from the boost circuit 140 D, and controls a signal V SL to be provided to the source line SL, based on the signals ERASE and READ from the sequencer 190 .
  • the source-line driving circuit 160 b sets the signal V SL at the ground voltage Vss if the signal READ is in a “High” state.
  • the source-line driving circuit 160 b provides a signal Ve 1 to the source line SL as a signal V SL if the signal ERASE is in a “High” state.
  • the first and second row decoder circuits 180 e and 180 f has transfer circuits 186 e and 185 f , respectively, instead of the first transfer transistors 186 a and 185 b according to the first embodiment.
  • each of the transfer circuits 186 e and 185 f has a voltage conversion circuit 185 A and a transistor 185 B.
  • the voltage conversion circuit 185 A receives signals V REDC2 and V SELa ⁇ i> (V SELb ⁇ i> ) from the boost circuit 140 D.
  • the transfer circuits 186 e and 135 f receive a signal Vhh from the boost circuit 140 E.
  • the voltage conversion circuit 185 A outputs a signal Vnodel based on the signal V SELa ⁇ i> (V SELb ⁇ i> ) and controls on/off of the transistor 185 B.
  • the transistor 185 B has one end connected to a selection-gate-line driving circuit 120 c ( 120 d ) and the other end to a source-side selection gate line SGS.
  • FIG. 29 is a flowchart illustrating an erase operation of the non-volatile semiconductor storage device in the fourth embodiment.
  • FIG. 30 schematically illustrates the erase operation.
  • the control circuit AR 2 b raises the source-side selection gate line SGS and the source line SL to a power supply voltage Vdd in a selected memory block MB (step S 31 ).
  • the word lines WL 1 to WL 8 and the back-gate line BG are raised to a certain voltage Vdd-Vth.
  • the control circuit AR 2 b starts boosting the source line SL to the erase voltage Vera 1 in the selected memory block MB, while supplying such a voltage to the source-side selection gate line SGS that results from delaying the voltage applied to that source line SL by a certain period of time and reducing it by a certain amount (which is the start of the voltage boost to an erase voltage Vera 2 ) (step S 32 ). That is, the control circuit AR 2 b starts boosting the source-side selection gate line SGS in time with the source line SL being boosted. This causes a GIDL current.
  • the word lines WL 1 to WL 8 , the back-gate line BG, and the drain-side selection gate line SGD are set in floating states.
  • the control circuit AR 2 b determines whether or not the voltage of the source line SL reaches the erase voltage Vera 1 in the selected memory block MB (step S 33 ). At this point, if it is determined that the voltage of the source line SL reaches the erase voltage Vera 1 (“Y” at step S 33 ), then the control circuit AR 2 b stops boosting that voltage (step S 34 ). At step S 34 , the control circuit AR 2 b also stops boosting the source-side selection gate line SGS. Note that at the point of the stoppage, the source-side selection gate line SGS has a lower potential than the source line SL.
  • the control circuit AR 2 b sets the word lines WL 1 to WL 8 and the back-gate line BG at the ground voltage Vss (step S 35 ), and feeds the holes H caused by the GIDL currents into the gates of the memory transistors MTr 1 to MTr 8 . In this way, data is erased.
  • FIGS. 31A and 31B are timing charts illustrating an erase operation.
  • a signal V BAD is inverted.
  • signals RST 1 and RST 2 fall from the power supply voltage Vdd to the ground voltage Vss. That is, the transistors 142 Db and 143 Dc in the boost circuit 140 D are set in OFF states and the signals Ve 1 and Ve 2 output from the boost circuit 140 D are set in floating states.
  • the signals V SELa ⁇ i> and V SELb ⁇ i> rise from the ground voltage Vss to the power supply voltage Vdd in the selected memory block MB. That is, the first transfer transistors 181 a to 185 a ( 181 b to 184 b , 186 b , and 187 b ) are set in ON states. On the other hand, the ground voltage Vss is applied to the gates of the second transfer transistors 187 a and 188 a ( 188 b and 189 b ).
  • the word lines WL 1 to WL 4 and WL 5 to WL 8 are connected to the word-line driving circuits 110 a and 110 b via the first transfer transistors 181 a to 184 a and 181 b to 184 b , respectively.
  • the drain-side selection gate line SGD is connected to the selection-gate-line driving circuits 120 c and 120 d via the first transfer transistors 185 a and 186 b , respectively.
  • the back-gate line BG is connected to the back-gate-line driving circuit 170 via the first transfer transistor 187 b.
  • the signals VnodeA of the transfer transistors 186 e and 185 f rise to the voltage Vpp in the selected memory block MB. That is, in the selected memory block MB, the transfer transistors 186 e and 185 f connect the source-side selection gate line SGS to the selection-gate-line driving circuits 120 c and 120 d.
  • the signals V SELa ⁇ x> and V SELb ⁇ x> are maintained at the voltage Vss in the unselected memory blocks MB. That is, the first transfer transistors 181 a to 186 a ( 181 b to 187 b ) are maintained in the OFF states.
  • the voltage VDD is applied to the gates of the second transfer transistors 187 a and 188 a ( 188 b and 189 b ). This allows the first transfer transistors 187 a and 188 a ( 188 b and 189 b ) to be set in ON states.
  • the word lines WL 1 to WL 4 and WL 5 to WL 8 are set in floating states in the unselected memory blocks MB.
  • the source-side selection gate line SGS and the drain-side selection gate line SGD are connected to the selection-gate-line driving circuits 120 c and 120 d via the second transfer transistors 188 a , 187 a , 188 b , and 189 b , respectively.
  • the back-gate line BG is set in a floating state.
  • the signals VnodeA of the transfer transistors 186 e and 185 f are maintained at the ground voltage Vss in the unselected memory blocks MB. That is, in the unselected memory blocks MB, the transfer transistors 186 e and 185 f keep the source-side selection gate line SGS unconnected to the selection-gate-line driving circuits 120 c and 120 d.
  • the signals V SGS1 and V SGS2 are raised from the ground voltage Vss to the power supply voltage Vdd.
  • the signals V SGD1 , V SGD2 , V SGOFF , V CG1 to V CG8 and V BG are raised from the ground voltage Vss to the certain voltage Vdd-Vth.
  • the signals V SGS1 ⁇ i> and V SGS2 ⁇ i> are raised to the power supply voltage Vdd in the selected memory block MB.
  • the signals V SGD1 ⁇ i> , V SGD2 ⁇ i> , V CG1 ⁇ i> to V CG8 ⁇ i> , and V BG ⁇ i> are raised to the certain voltage Vdd-Vth in the selected memory block MB.
  • the signal V SL is raised to the power supply voltage Vdd at the source-line driving circuit 160 .
  • the signal Vref is raised to a voltage Vera 3 at the boost circuit 140 D. Accordingly, at time t 33 , the oscillation circuit 141 D begins its operation and the first signal generation circuit 142 D starts boosting the signal Ve 1 . Then, after a certain period of time has elapsed since time t 33 , the second signal generation circuit 143 D starts boosting the signal Ve 2 .
  • the voltages of the signals V SGS1 and V SGS2 begin to rise according to the signal Ve 2 .
  • the voltages of the signals V SGS1 ⁇ i> and V SGS2 ⁇ i> begin to rise in the selected memory block MB.
  • the voltage of the signal V SL also begins to rise according to the signal Ve 1 .
  • the boost circuit 140 D determines that the signal Va is boosted to the voltage Vera 3 (i.e., the signal Ve 1 is boosted to a certain voltage). Then, the boost of the signals Ve 1 and Ve 2 is stopped and the signals Ve 1 and Ve 2 are set at the erase voltages Vera 1 and Vera 2 .
  • the boost of the signals V SGS1 and V SGS2 is stopped and the signals V SGS1 and V SGS2 are set at the erase voltage Vera 2 .
  • the boost of the signals V SGS1 ⁇ i> and V SGS2 ⁇ i> is stopped and the signals V SGS1 ⁇ i> and V SGS2 ⁇ i> are set at the erase voltage Vera 2 .
  • the boost of the signal V SL is also stopped and the signal V SL is set at the erase voltage Vera 1 .
  • the signals V CG1 to V CG8 and V BG are set at the ground voltage Vss.
  • the holes H caused by the GIDL currents are fed into the gates of the memory transistors MTr 1 to MTr 8 , after which execution of the erase operation begins.
  • the non-volatile semiconductor storage device in the fourth embodiment has a boost circuit 140 D.
  • the boost circuit 140 D generates signals Ve 1 and Ve 2 .
  • the signal Ve 2 is boosted after a certain period of time has elapsed since the signal Ve 1 is boosted, while maintaining a certain potential difference from the signal Ve 1 .
  • the signal Ve 1 is supplied to the source line SL and the signal Ve 2 is supplied to the source-side selection gate line SGS.
  • the non-volatile semiconductor storage device in the fourth embodiment may achieve efficient data erase operation with GIDL currents, as in the first to third embodiments.
  • the non-volatile semiconductor storage device in the fourth embodiment does not use the coupling ratio between the body of a memory string MS and a source line SL to generate a GIDL current. That is, the non-volatile semiconductor storage device in the fourth embodiment directly specifies the potentials of source-side selection transistors SSTr and source lines SL to generate a GIDL current. This allows the non-volatile semiconductor storage device in the fourth embodiment to perform an erase operation, independent of device parameters, such as coupling ratio or wiring capacitance. In addition, the non-volatile semiconductor storage device in the fourth embodiment may mitigate the stress on the gates of the source-side selection transistors SSTr as compared with the first to third embodiments.

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US8605508B2 (en) 2013-12-10
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