TW201029011A - Non-volatile semiconductor storage device - Google Patents

Abstract

A non-volatile semiconductor storage device includes: a memory string including a plurality of memory cells connected in series; a first selection transistor having one end connected to one end of the memory string; a first wiring having one end connected to the other end of the first selection transistor; a second wiring connected to a gate of the first selection transistor. A control circuit is configured to boost voltages of the second wiring and the first wiring in the erase operation, while keeping the voltage of the first wiring greater than the voltage of the second wiring by a certain potential difference. The certain potential difference is a potential difference that causes a GIDL current.

Description

201029011 VI. Description of the Invention: TECHNICAL FIELD The present invention relates to an electrically rewritable non-volatile semiconductor storage device. The present application is based on the prior Japanese Patent Application No. 2009-2376, the entire disclosure of which is incorporated herein by reference. [Prior Art] As an improved technique for improving the bit density of a non-volatile semiconductor storage device such as a NAND type flash memory is pushed to the limit, there is an ever-increasing demand for a stack of memory cells. As an example, it has been proposed that the memory unit be configured as such a non-volatile semiconductor storage device having a vertical transistor (see, for example, Japanese Patent Laid-Open Publication No. 2-7 266143). A stacked type nonvolatile semiconductor storage device has a columnar semiconductor layer, a striking layer formed to surround the columnar semiconductor layer, and a conductive layer formed to surround the MONOS layer. For a flat type non-volatile semiconductor memory device, the erase operation is performed by increasing the substrate potential of the channel to the erase voltage so that the electrons are removed from the associated helper layer. However, the above-mentioned laminated (four) non-volatile semi-conductive (four) storage device is attributed to its channel-like semi-conductive layer. Therefore, performing the erase operation in the stacked 5 non-volatile semiconductor storage device in the same manner as in the flat type device is inefficient and non-distributable

The class 0 J needs to provide a non-volatile semiconductor storage device in which the erase operation can be performed in an effective manner. The non-volatile semiconductor storage device of the invention is 144995.doc 201029011 [Description of the Invention] The volatile semiconductor storage device comprises: a memory string comprising a plurality of memory cells connected in series; a first selection transistor having a -m-m line connected to one end of the memory body, having Connected to the other end of the first selection transistor; a second wiring connected to the -interpole 'and-control circuit of the first selection transistor, configured to perform an erase operation Thereby erasing data from the memory cells, the memory string comprising: a first semiconductor layer having a columnar portion extending in a direction perpendicular to a substrate; a charge storage layer formed a conductive layer TM guiding layer extending around the charge storage layer and the substrate, the first selective transistor comprising: a second semiconductor layer contacting a top surface or a bottom surface of the columnar portion and Extending perpendicular to the direction of the substrate; a first gate insulating layer formed to surround the second semiconductor layer; and a second conductive layer surrounding the first gate insulating layer and parallel to the substrate Extending, the control circuit is configured to boost the voltage of the second wiring and the first wiring during the erasing operation while maintaining the voltage of the first wiring greater than the voltage of the second wiring The potential difference, which is a potential difference that causes a GIDL current. [Embodiment] An embodiment of a nonvolatile semiconductor storage device according to the present invention will now be described with reference to the accompanying drawings. [First Embodiment] I44995.doc 201029011 (General Configuration of Nonvolatile Semiconductor Storage Device in First Embodiment) Referring first to FIG. 1 ' Hereinafter, a nonvolatile semiconductor storage device according to a first embodiment will be described. General configuration. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a circuit diagram of a nonvolatile semiconductor storage device in a first embodiment. As illustrated in Fig. 1, the nonvolatile semiconductor storage device of the first embodiment comprises a memory cell array AR1 and a control circuit AR2 provided on the periphery of the memory cell array AR1. The memory cell array AR1 has electrically rewritable memory transistors MTrl to MTr8 (memory cells). The control circuit AR2 includes control circuits for controlling voltages applied to the memory transistors MTrl to MTr8 and the like. As described in Fig. 1, the memory cell array ARi has m rows of memory blocks MB. Each memory block MB includes an n-column and a 2-row memory string MS, source-side selection transistors SSTr' each connected to one end of the memory string MS, and each connected to the other end of the memory string MS The transistor SDTr is selected on the drain side. Note that in the example of Figure 1, the first row is represented by (j) and the second row is represented by (2). As illustrated in Fig. 2, each memory string MS has a memory transistor MTrl to MTr8 and a back-gate transistor BTr. The memory dielectric crystals MTrl to MT4 are connected in series. The memory transistors MTr5 to MTr8 are connected in series. The back gate transistor BTr is provided between the memory transistors MTr4 and MTr5. The memory transistors MTr 1 to MTr8 including the MONOS structure cause charges to accumulate in the respective control gates. The non-volatile semiconductor storage device of the first embodiment stores data via accumulation of electric charges. As shown in Fig. 2, the control gates 144995.doc 201029011 of the memory transistors MTrl to MTr8 are connected to the word lines WL1 to WL8. The control gate of the back gate transistor BTr is connected to the back gate line BG. As illustrated in Fig. 1, the respective word lines WLi (i = 1 to 8) are commonly supplied to the respective memory transistors MTn (1 = 1 to) in the memory strings MS aligned in the column direction. The control gate of 8) is formed to extend in the column direction across the memory string MS. Similarly, each of the back gate lines BG is commonly supplied to the control gates of the back gate transistor BTr aligned in the column direction, and is formed to extend in the column direction over the memory string MS. One end of each of the source side selection transistors SSTr is connected to one end of the memory transistor MTr8 as illustrated in Fig. 2 . The other end of each source side selective electro-optic body SSTr is connected to the first source line SLa. The control gate of each source side selection transistor SSTr is connected to the source side selection gate line SQS. As illustrated in FIG. 1, each of the first source lines SLA is commonly supplied to the source of the source side selection transistor SSTr aligned in the column direction, and is formed to cross the plurality of memory strings MS in the column. Extend in the direction. The first source lines SLA aligned in the row direction φ are commonly connected to a single second source line SLB extending in the row direction. Each of the source side selection gate lines SgS is commonly supplied to the control gate of the source side selection transistor 881 &gt; aligned in the column direction, and is formed to extend in the column direction across the plurality of memories _MS . As illustrated in Fig. 2, the end of each of the drain side selection transistors 81) 1 &gt; is connected to one end of the memory transistor MTrl. The other end of each of the drain side selective electro-optic bodies SDTr is connected to the bit line BL. The control gate of each of the drain side selection transistors SDTr is connected to the drain side selection gate line 8 (31). 144995.doc 201029011 As illustrated in FIG. 1, each bit line BL is commonly supplied to the drain of the drain side selection transistor SDTr aligned in the row direction, and is formed to cross a plurality of memory blocks MB Extend in the row direction. Each of the drain side selection gate lines SGD is commonly supplied to the control gates of the gateless selection transistors SDTr aligned in the column direction, and is formed to extend in the column direction across the plurality of memory strings MS. In the erasing operation, the control circuit AR2 boosts the voltages of the source line 乩 and the source side selection gate line SGS while maintaining the source line 乩 (the first source line SLA and the second source line SLB) The voltage is greater than the voltage of the source side selection gate line sgs by a certain potential difference. This potential difference is the potential difference Vth that causes the GIDL current. This is one of the features of this embodiment. Note that a potential difference is not limited to the potential difference Vth. As illustrated in FIG. 1, the control circuit AR2 has an input/output circuit 100, word line drive circuits 110a and 110b, select gate line drive circuits 120a and 120b, a bit address decoder circuit 13A, and a boost circuit i4. 〇a to 140C, a sense amplifier circuit 15A, a source line driver circuit 16A, a back gate line driver circuit 170, a first column decoder circuit i 8〇a, and a second column decoder circuit 180b, and a sequencer 190. As illustrated in Fig. 1, the input/output circuit 100 receives information from the outside to be input to the memory cell array AR1, and inputs the information to the sense amplifier circuit 150. Further, the input/output circuit 1 outputs information from the sense amplifier circuit 150. As illustrated in Fig. 1, the word line drive circuit 11 〇 &amp; outputs signals 乂^ to vCG4 for driving the word lines WL1 to WL4. The word line driver circuit n〇b outputs 144995.doc -10- 201029011 for driving the signals vCG5 to VCG8 of the word lines WL5 to WL8. The gate line driver circuit 120 &amp; output signals vsgsi, vSGD2, and vSG0FF are selected. The gate line driving circuit 12 〇 & output signals vsgs2 and vSGOFF are selected. The signal vSGS1 & vSGS2 is used to drive the source side selection gate line SGS in the selected memory block (hereinafter referred to as "selected memory block MB"). Signals VsGD2 and VsGD1 are used to drive the drain side select gate line SGD in the selected memory block MB. The signal Vsg〇ff is used to drive the source side selection gate line SGs and the drain side selection gate in the unselected memory block MB (hereinafter referred to as "non-selected memory block MB"). Polar line SGD. The address decoder circuit 13 outputs a signal Vbad 0 for specifying the block address. The boost circuit 140 A boosts the voltage from the power supply voltage and transfers the boosted voltage to the word line drive circuit 11 〇 & And the 1101 boost circuit 14 〇 B boosts the voltage from the power supply voltage to obtain a signal VRDEC, which is output to the first column decoder circuit 180a and the second column decimator circuit 18b. The boosting circuit 140C boosts the voltage from the power supply voltage to obtain a signal vERA, which is output to the source line driving circuit 160. The signal VERA is used to erase data from the memory transistor MTrl to MTr8. The sense amplifier circuit 150 reads information based on the voltage of the bit line BL. Further, the sense amplifier circuit 150 supplies the bit line BL with a signal of the same voltage as the voltage of the signal VSL of the source line SL (the first source line SLA and the second source line SLB). In addition, sense amplifier circuit 150 receives signal VBAD input from address decoder circuit 130. 144995.doc 201029011 The source line driver circuit 1 60 outputs a signal VSL for driving the source line SL (the first source line SLA and the second source line SLB). The back gate line driving circuit 1 70 outputs a signal VBG for driving the back gate line BG. A first column of decoder circuits 18a and a second column of decoder circuits 1 80b are provided, respectively, with one column decoder circuit for each memory block mb. Each of the first column decoder circuits 180a is provided at one end of the respective memory block mb in the column direction. Each of the second column decoder circuits 丨8〇b is provided at the other end of the respective memory block MB in the column direction. Based on the signal vBAD output from the address decoder circuit 130, each of the first column decoder circuits 180a selectively inputs the signals VCG1 &lt;i&gt; to Vcg4^ to the gates of the memory transistors MTrl to MTr4. Further, the signal Vsguo is selectively input to the gate of the source side selection transistor SSTr in the second row based on the signal VBAD' first column decoder circuit 180a. Further, based on the signal vBAD, the first column decoder circuit 180a selectively inputs the signal Vsgd to the gate of the drain side selection transistor SDTr in the first row. Each of the first column decoder circuits 180a has a voltage conversion circuit 108a, a transfer transistor igia to i86a, and second transfer transistors 187a and 188a. The voltage conversion circuit 180aa generates a signal VSELa&lt;i&gt; based on the received signals Vbad and Vrdec, which is output to the gates of the first transfer transistors 181a to 186a. Further, the voltage conversion circuit 18Aa controls the gates of the second transfer transistor 丨87a and 188a based on the voltage of the received signal vBAD. The gates of the first transfer transistors 181a to 184a receive the signal VSELa&lt;i&gt; from the voltage conversion circuit 180aa. The first transfer transistor 181 & to 184 & 144995.doc -12- 201029011 is between the word line driver circuit 110a and the word lines WL1 to WL4. The first transfer transistors 181a to 184a output signals VcGKi^Vcc^o to the word lines wu to WL4 based on the signals Vc(1) to ¥(^ and VsELa&lt;i&gt;. Further, the first transfer transistor 185a is connected to the selection gate line driving circuit. 12〇a and the source side selection gate line SGS of the source side selection transistor SSTr in the second row. The first transfer transistor 185a selects the gate to the source side based on the signal %2 and VsELa&lt;i&gt; The pole line SGS output signal VSGS2&lt;i&gt;. Further, the first transfer transistor l86a is connected to the gate line selection circuit 1 20a and the drain side selection gate of the drain side selection transistor XRD in the first row Between the lines SGD, the first transfer transistor 186 & based on the signals Vsgim and VSELa&lt;i&gt; to the drain side select gate line SGD output 4 Lu VSGm&lt;i&gt; 〇Second transfer transistors 187a and 188a gate reception The number from the voltage conversion circuit 180aa. One end of the first transfer transistor 187a is connected to the source side selection gate line SGS of the source side selection transistor SSTr in the second row, and the signal Vsg〇ff is input to the other End. The end of the second transfer transistor φ 188 & The drain side of the first row selects the drain side selection gate line SGD of the transistor SDTr, and the signal Vsg〇ff is input to the other end. Based on the signal Vbad output from the address decoder circuit 13〇, each The two-column decoder circuit 180b selectively inputs the signal V(10) to VCG8◊ to the gates of the memory transistors MTr5 to MTr8. Further, based on the signal VBAD, the second column decoder circuit 18〇b selects the signal VSGS1◊ selectively The ground is input to the gate of the source side selection transistor SSTr in the first row. Further, based on the signal VBAD, the second column decoder circuit 18 输入 inputs the signal selection I·the ground to the bottom side of the second row. The closed pole of the transistor. This 144995.doc •13. 201029011, based on the signal vBAD 'the second column decoder circuit 18〇b selectively inputs the signal Vbg<b to the gate of the back gate transistor BTr. The first column decoder circuit 180b has a voltage conversion circuit 180bb, first transfer transistors 181b to 187b, and second transfer transistors 188b and 189b. The voltage conversion circuit 180bb is generated based on the voltages of the received signals Vbad and vRDEC. Signal VsELb&lt;i&gt; And outputting the signal to the gates of the first transfer transistors 181b to 187b. Further, the power conversion circuit 180bb controls the gates of the second transfer transistors 188b and 189b based on the received signal Vbad. The gates of the crystals 181b to 187b receive the signal vSELb&lt;i&gt; from the voltage conversion circuit 180bb. The first transfer transistors 181b to 184b are connected between the word line drive circuit 11b and the word lines WL5 to WL8, respectively. The first transfer transistors 1811^ to 18415 input signals VCG5&lt;i&gt; to VCG8&lt;i&gt; to the word lines WL5 to 1WL8 based on the signal 乂(:(35 to ^(^8 and 乂^1^&lt;。&gt;). Further, the first transfer transistor 185b is connected between the selection gate line driving circuit i2〇b and the source side selection gate line SGS of the source side selection transistor SSTr in the first row. The first transfer electric BB body 185b The gate line SGS output signal v SGS1 &lt;i&gt; is selected to the source side based on the signals VsGS1 and VsELb&lt;i&gt;. Further, the first transfer transistor 186b is connected to the selection gate line driving circuit 12〇b and the second row. The drain side selects between the drain side select gate lines SGD of the transistor SDTr. The first transfer transistor 186b selects the gate line SGD output signal 没(10) based on the signals vSGD2 and V SELb&lt;i&gt; In addition, the first transfer transistor 18713 is connected between the back gate line driving circuit 170 and the back gate line BG. The first transfer transistor 18 is based on the signals VBG and VSELb&lt;i&gt; and inputs the signal H4995 to the back gate line BG. Doc • 14· 201029011

Vbg&lt;i&gt; 0 The gates of the first transfer transistors 188b and 189b receive signals from the galvanic conversion circuit 180bb. One end of the second transfer transistor 188b is connected to the source side selection gate line SGS' of the source side selection transistor SSTr in the first row and the signal VsGOFF is input to the other end. One end of the second transfer transistor 189b is connected to the drain side selection transistor drain side selection gate line SGD in the second row, and the signal VsG0FF is input to the other end. The sequencer 190 inputs control signals to the word line drive circuits ii 〇 a and 11 〇 b, the selection gate line drive circuits 120 a and 120 b ′ and the source line drive circuit 16 。. As illustrated in Fig. 3, each word line driver circuit 110a includes a first word line driver circuit 110A to a fourth word line driver circuit 11A. The first word line driver circuit 110A outputs a signal VCG1. The second word line drive circuit 110B outputs a signal VcG2. The second word line drive circuit 11 0C outputs a signal VcG3. The fourth word line driving circuit 110D outputs a signal VCG4. As illustrated in Fig. 3, each word line drive circuit η 〇b includes a first word line drive circuit 110A to a fourth word line drive circuit 11 〇D. The first word line driver circuit 110A outputs a signal VCG5. The second word line drive circuit 110B outputs a signal VCG6. The third word line drive circuit 110C outputs a signal vCG7. The fourth word line driving circuit 110D outputs a signal VCG8. As illustrated in Fig. 3, each of the first word line drive circuits i1a has: voltage conversion circuits 111A to 111C, and transfer transistors 112A to 112C. The voltage conversion circuits 111 A to 111C have input terminals that receive control signals input from the sequencer 190. The voltage conversion circuits 111A to 111C have output terminals connected to the gates of the transfer 144995.doc -15-201029011 shift transistors 112A to 112C. The output terminals of the transfer transistors 112A to 112C are connected in common. The input terminal of the transfer transistor 112A is connected to the output terminal of the booster circuit 140A. The input terminal of the transfer transistor 112B is connected to the ground voltage Vss. The input terminal of the transfer transistor 112C is connected to the power supply voltage Vdd. Note that the second word line drive circuit 11OB to the fourth word line drive circuit 110D have the same configuration as that of the first word line drive circuit 110 A. As shown in Fig. 4, each of the selection gate line driving circuits i20a (120b) includes a first selection gate line driving circuit 120A to a third selection gate line driving circuit 120C. The first selection gate line driving circuit 120A outputs a signal VSG0FF. The second selection gate line driving circuit 120B outputs a signal vsgs1 (Vsgs2). The third selection gate line driving circuit 120C outputs a signal VSGD2 (VSGD1). As illustrated in FIG. 4, the first selection gate line driving circuit 12A has: voltage conversion circuits 121A and 121B and transfer transistors 122A and 122B. The voltage conversion circuits 121A and 121B have input terminals for receiving signals from the sequencer 190. The voltage conversion circuits 121A and 12 1B have output terminals connected to the gates of the transfer transistors 122A and 122B. The output terminals of the transfer transistors 122A and 122B are connected in common. The input terminal of the transfer transistor i22A is connected to the ground voltage Vss. The input terminal of the transfer transistor 122B is connected to the power supply voltage Vdd. Note that the 'second selection gate line driver circuit 120B and the third selection gate line driver circuit 120C have the same configuration as that of the first selection gate line driver circuit 120A. The boosting circuits 140A to 140C generate a voltage higher than the power supply voltage Vdd by the charging and discharging of the capacitor. As illustrated in Fig. 5, the boosting circuit 144995.doc -16 - 201029011 140A to 140C has diodes 143a to 143n and charging and discharging circuits 144a to 1441. Please note that boost circuits 140 Α to 140C may have more diodes and charging and discharging circuits. The diodes 143a to 143e are connected in series as illustrated in Fig. 5. The diodes 143f to 143n are connected in series. One end of the diode 143a is connected to one end of the diode 143f. One end of the diode I43e is connected to one end of the diode 14311. The output terminals of the charging and discharging circuits 144a to 144d are connected between the diodes 143a to 143e as illustrated in Fig. 5. The output terminals of the charging and discharging circuits 14A to 1441 are connected between the diodes 143f to 143n. Each of the charging and discharging circuit 144a barrier 41 involves an AND circuit 144A, an inverter 144B, and a capacitor 144C connected in series. In the charging and discharging circuits 144a to 144d, the input terminal at one of the ends of the AND circuit 144A alternately receives the signal φ ΐ or φ 2 . In the charging and discharging circuits 144a to 144d, the input terminal at the other end of the AND circuit 144 receives the signal VPASS. In the charging and discharging circuits 144e to 1441, the input terminal at one of the ends of the AND circuit 144A alternately receives the signal φ ΐ or φ 2 . In the charging and discharging circuits 144e to 1441, the input terminal at the other end of the AND circuit Α4Α receives the signal VPRCJ. Referring now to Figures 6A and 6B, the operation of the boosting circuits 140A to 140C will be described hereinafter. 6A and 6B are timing charts illustrating the operation of the boosting circuits 140A to 140C. As shown in Figs. 6A and 6B, the boosting circuits 14A to 140C set the signal VPASS or the signal VpRG to 144995.doc -17-201029011 as the power supply voltage Vdd or the ground voltage Vss depending on the generated signal. As illustrated in Fig. 7, the source line driving circuit 16A has voltage converting circuits 161A to 161C, and transfer transistors 162A to 162C. The voltage converting circuits 161A to 161C and the transfer transistors 162A to 162C are connected in the same manner as the voltage converting circuits iiiA to me and the transfer transistors 112A to 112C in the word line driving circuit 110a. Voltage conversion circuits 161 to 161 (: an input terminal having a signal received from the input of the sequencer 190. The input terminal of the transfer transistor 162A is connected to the output terminal of the booster circuit 14A. The input terminal of the transfer transistor 162B is connected to The grounding voltage vss. The input terminal of the transfer transistor 162C is connected to the power supply voltage vdd. As illustrated in Fig. 8, the sense amplifier circuit 15A has a plurality of selection circuits 151, and voltage conversion circuits 152A and 152B. 151 selectively connects the bit line BL to the source line SL, and sets the bit line b1 to have the same potential as the potential of the source line SL. As illustrated in Fig. 8, 'each selection circuit ι51 has: One page buffer 151a, and transistors 1511:) and 151 (1. One end of the page buffer 15U is connected to one end of the receiving signal from the bit line BL of the transistor 151b, and to the input/output circuit 100 and the bit The address decoder circuit 130 inputs an output based on the signal. The other end of the transistor 151b is connected to the bit line bl. The transistor 151b also has a control gate which is received from the voltage conversion circuit 1 52A. The signal VCUT is output. One end of the transistor 151c is connected to the bit line BL ° The other end of the transistor 151c is connected to the source line sl. The transistor 151c also has a control gate 'The control gate receives the self-voltage conversion The signal vrst is output by the circuit 152B. 144995.doc • 18- 201029011 The voltage conversion circuit 152A receives the signal from the sequencer 190 and outputs a signal VCUT based on the signal. The voltage conversion circuit 152B receives the signal from the sequencer 190' and based thereon Signal and output signal vrst. (Laminated structure of nonvolatile semiconductor storage device in the first embodiment) Referring now to FIGS. 9 and 1B, a cascading of the nonvolatile semiconductor storage device according to the first embodiment will be described hereinafter. Fig. 9 is a schematic perspective view showing a part of the memory cell array AR丄 in the nonvolatile semiconductor storage device in the first embodiment. Fig. 10 is a partial cross-sectional view of Fig. 9. The memory cell array AR1 is provided on the substrate 1. The memory cell array AR1 has a back gate transistor layer 2, a memory transistor layer 30, and a selection. The crystal layer 40 and a wiring layer 5A. The back-charged aa body layer 20 functions as a back gate transistor BTr. The memory transistor layer 3 serves as a memory transistor MTrl to MTr8 (memory string MS). The transistor layer 40 is selected. It functions as a source side selection transistor SSTr and a drain side selection transistor SDTr. The wiring layer 50 serves as a source line SL and a bit line BL. φ As illustrated in FIGS. 9 and 1B, the back gate transistor layer 20 has A back gate conductive layer 21. The back gate conductive layer 21 is formed to expand in a two-dimensional manner in the column and row directions parallel to the substrate 1 . The back gate conductive layer 21 is separate for each memory block • River 8. The back gate conductive layer 21 contains polycrystalline germanium (p-Si). Each of the dorsal-conducting layers 21 acts as a back gate line BG. As illustrated in FIG. 10, the back gate transistor layer 20 has a back gate hole 22. The back gate hole 22 is formed to be inserted into the back gate conductive layer 21. Each of the back free holes 22 is formed into a substantially rectangular shape as viewed from above, and its longitudinal direction is in the row direction. The back gate holes 22 are formed in a matrix form in the column and row directions. 144995.doc •19· 201029011 As shown in Fig. 9 and Fig. 10, the memory layer 30 is formed on the back gate transistor layer 2G. • The memory transistor layer 3q has 31d. The word line conductive layers 3U to 3ld are laminated with an interlayer insulating layer (not shown) sandwiched between them: a dedicated &amp; μ nn, a *~. The sub-line conductive layer 3 is formed as a stripe pattern extending in the column direction at a certain pitch in the row direction. The word line conducting layers (1) to ... contain polycrystalline boasts. Word line conductive layers 31a to 3U to WLS. The word line conducting layers 31 &amp; to 31 (1 charge the control gate of the Tin Tin 0 memory cell MTrl to MTr8. As illustrated in Fig. 10, the memory transistor layer 3 has a memory hole 32. The memory holes 32 are formed to penetrate the word line conductive layers ... to w. The memory holes 32 are formed at positions close to each end in the direction of the (four) holes 22. Further, as illustrated in FIG. The transistor layer 2 and the memory transistor layer 30 have: - a block insulating layer - a charge storage layer, a milk penetrating insulating layer 33c, and a U-shaped main circuit jsu x T. a bovine conductor layer 34. The 1^ The semiconductor layer 34 serves as a body of the memory string MS. As illustrated in Fig., the block insulating layer 33a is formed to have a certain thickness on the sidewalls of the back gate hole 22 and the memory hole 32. The charge storage layer is formed. The gate insulating layer 33c is formed to have a certain thickness on the side surface of the charge storage layer 33b. The U-shaped semiconductor layer 34 is formed to be the tunneling insulating layer 33c. The side surface contacts. The U-shaped semiconductor layer 34 is formed to fill the back gate hole 22 and the memory hole 32. The U-shaped semiconductor layer 34 is formed in a U-shape when viewed from the column direction. The u-shaped semiconductor layer 34 has a pair of pillars 144995.doc -20- 201029011 portion 34a extending in a direction perpendicular to the substrate 1〇. And a bonding portion 34b joining the lower end portions of the pair of columnar portions 34a, the block insulating layer 33a and the tunneling insulating layer 33C containing the SiO2 (Si〇2). The charge storage layer 33b contains the cerium (SiN) The u-shaped semiconductor layer 34 contains polycrystalline germanium (p-Si). The block insulating layer 33a, the charge storage layer 33b, and the tunnel insulating layers 33c and 11 are opened. The semiconductor layer 34 functions as a MONOS of the memory transistor MTr丨 to μτγ8. The above-mentioned configuration of the back gate transistor layer 20 is restated as follows: a tunneling insulating layer 33c is formed to surround the bonding portion 34b. The back gate conducting layer 21 is formed to surround the bonding portion 34b. The configuration mentioned above at 30 is restated as follows: The tunneling insulating layer 33c is formed to surround the columnar portion 34a. The charge storage layer 33b is formed to surround the tunneling insulating layer 33c. The block insulating layer 33 &amp; is formed to surround Charge storage layer 33b. Word line The conductive layers 31 &amp; to 31 (1 are formed to surround the block insulating layer 33a and the columnar portion 34a. As illustrated in FIGS. 9 and 10, the selective transistor layer 4A has a source side conductive layer 41a and a stack The source side conduction layer 41&amp; and the drain side conduction layer 41b are formed in a stripe pattern extending in the column direction at a certain pitch in the row direction. A pair of source side conduction layers 4U and a pair of 汲The pole side conductive layers 41b are alternately positioned in the row direction. Each of the source side conductive layers 4u is formed over one of the columnar portions 34a included in a respective 17-type semiconductor layer 34, and each of the drain side conductive layers 41b is formed to be included in the semiconductor Above the other of the columnar portions 34a in layer 34. The source side conduction layer 41a and the drain side conduction layer 41b contain polysilicon (p_144995.doc • 21 201029011)

Si). Each source side conduction layer 41a serves as a source side selection gate line sgs. Each of the source side conduction layers 41a also functions as a control gate of the source side selection transistor SSTr. Each of the drain side conduction layers 41b serves as a drain side selection gate line SGD. Each of the drain side conductive layers 41b also serves as a control gate of the drain side selection transistor SDTr. As illustrated in FIG. 10, the selective transistor layer 40 has a source side hole 42a and a drain side hole 42b. The source side hole 42a is formed to penetrate the source side conduction layer 41a. The source side hole 42a is formed at a position matching the memory hole 32. The drain side hole 42b is formed to penetrate the drain side conduction layer 41b. The drain side hole 42b is formed at a position matching the memory hole 32. As shown in FIG. 10, the selective transistor layer 40 has a source side gate insulating layer 43a, a source side columnar semiconductor layer 44a, a gate electrode insulating layer 43b, and a drain. The side columnar semiconductor layer 44b. The source side gate insulating layer 4 3 a is formed on the sidewall of the source side hole 4 2 a. The source side columnar semiconductor layer 44a is formed in a columnar shape extending in a direction perpendicular to the substrate 1A and in contact with the source side gate insulating layer 43a. The drain side gate insulating layer 43b is formed on the sidewall of the drain side hole 42b. The drain-side columnar semiconductor layer 44b is formed into a columnar shape extending in a direction perpendicular to the substrate 10 and is in contact with the gateless gate insulating layer 43b. The source side gate insulating layer 43a and the drain side gate insulating layer 43b contain cerium oxide (Si 〇 2). The source side columnar semiconductor layer 4A and the drain side columnar semiconductor layer 44b contain polycrystalline (p-Si). The above-mentioned configuration of the selection of the transistor layer 40 is restated as follows: The source side gate insulating layer 43a is formed to surround the source side columnar semiconductor layer. 144995.doc -22- 201029011 The source side conduction layer 41a is formed to surround the source side gate insulating layer 43a and the source side columnar semiconductor layer 44a. The drain side gate insulating layer 43b is formed to surround the drain side columnar semiconductor layer 44b. The drain side conductive layer 41b is formed to surround the drain side gate insulating layer 431 and the drain side columnar semiconductor layer 44b. As illustrated in FIGS. 9 and 10, the wiring layer 50 is formed on the selective transistor layer 40. The wiring layer 50 has a source line layer 51, a plug layer 52, and a bit line layer 53. The source line layer 51 is formed in the form of a plate extending in the column direction. The source line layer 51 is formed in contact with the top surface of one of the pair of source side columnar semiconductor layers 44a adjacent in the row direction. The plug layer 52 is formed to be in contact with the top surface of the drain-side columnar semiconductor layer 44b and to extend in a direction perpendicular to the substrate 10. The bit line layer 53 is formed as a stripe pattern extending in the row direction at a certain pitch in the column direction. The bit line layer 53 is formed in contact with the top surface of the plug layer 52. The source line layer 51, the plug layer 52, and the bit line layer 53 contain a metal such as tungsten (W). Each of the source line layers 51 serves as a source line sl (first source line SLA). Each bit line layer 53 serves as a bit line bl. (Outline of erasing operation of the nonvolatile semiconductor storage device in the first embodiment) Referring now to Figs. 11 and 12, the erasing operation of the nonvolatile semiconductor storage device according to the first embodiment will be hereinafter described. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 流程图 is a flow chart for explaining the erasing operation of the nonvolatile semiconductor storage device in the first embodiment. Figure 12 schematically illustrates the erase operation. First, as indicated by the label "sii" in FIG. 12, in the selected memory block MB, the control circuit AR2 raises the source side selection gate line SGS and the drain side selection gate line SGD to some A voltage Vdd_Vth, and 144995.doc -23-201029011 boost the source line SL and the bit line BL to the power supply voltage vdd (step sil). The power supply voltage vdd is a voltage that causes a GIDL current due to a certain voltage vth and due to the potential difference Vth. In this case, as indicated by the label "A" in Fig. 13, the source side conduction layer 4a on the source line layer 5 1 (source line SL) side (source side selection) A higher electric field is established at the end of the gate line SGS) to cause a GIDL current. In addition, as indicated by another tag rA" in FIG. 13, the gate electrode layer 4 ib is also provided on the side of the bit line layer 53 (bit line bl). A higher electric field is established at the end of SGD) to cause a GIDL current. Due to the GIDL current, a hole η and an electron e are generated. Further, at step sii, the control circuit AR2 boosts the word lines WL1 to WL8 and the back gate line BG to the power supply voltage Vdd as indicated by the label "sUj" in Fig. 12. Subsequently, as indicated by the reference in Fig. 12. As indicated by "sl2", the control circuit AR2 boosts the source line SL and the bit line BL from the power supply voltage vdd to the erase voltage Vera (step S12). Note that during the operation at step S12, the other wiring is maintained in the same controlled state as the controlled state described in step S11. However, the source side selection gate line SGS, the drain side selection gate line SGD, the word lines WL1 to WL8, and the back gate line BGs are set in a floating state. Then, the respective potentials of the source side selection gate line SGS, the drain side selection gate line sgd, the word lines WL1 to WL8, and the back gate line BG are increased due to the light combination with the body of the memory string MS. . More specifically, at step S12, the following control is performed: a potential difference greater than Vth is generated between the source side selection gate line SGS and the source line SL to 144995.doc • 24· 201029011 and selected on the non-polar side A potential difference greater than vth is generated between the gate line SGD and the bit line BL. Due to this potential difference, the GIDL current is caused and the hole is injected into the body of the memory string MS, thereby raising the potential of the body. Then, due to the coupling with the body of the memory string MS, the respective gate potentials of the source side selection transistor SSTr and the drain side selection transistor SDTr become higher than the certain voltage Vdd-Vth. Therefore, the source side selection gate line SGs &amp; the drain side selection gate line SGD is set to the floating state. Once this cycle starts, the potential of the body of the memory string MS, the source side selection gate line S (the potential of the 5s and the potential of the gate selection SGD of the gate side follow the potential of the source line S1 and the bit line B1). Increases and becomes higher. After the operation at step S12 is performed, and when the source line % and the bit line BL reach the erase voltage Vera, 'as indicated by the label "sl3" in Fig. 12, control The circuit AR2 sets the word lines WL1 to WL8 and the back gate line BG to the ground voltage Vss (step S13)' and feeds the holes caused by the GIDL currents to the gates of the CMOS circuits MTrl to MTr8. In this manner, the data is erased. (Specific erasing operation of the non-volatile semiconductor storage device in the first embodiment) Referring now to FIGS. 14A and 14B, the non-volatile semiconductor storage device according to the first embodiment will be described hereinafter. Specific erase operation. Figure 14A and Figure 14B are timing diagrams illustrating the erase operation. First, at time til, the signal vBAD is inverted as illustrated in Figure 14A. As illustrated in Figure 14B, due to the signal Vbad The change at time 111 'in the selected memory block MB The signal VsELa&lt;i&gt;&amp;VsELb&lt;i&gt; is self-connected 144995.doc -25- 201029011 The ground voltage Vss is boosted to the power supply voltage Vdd. That is, the first transfer transistors 181a to 186a (181b to 187b) are set to be connected. On the other hand, the ground voltage Vss is applied to the gates of the second transfer transistors 187 &amp; and 188 &amp; (1881) and 189b). This allows the second transfer transistors 187 &amp; and 188 &amp; (1881) and 189b) to be set to the off state. By this operation, in the selected memory block MB, the word lines WL1 to WL4 and WL5 to WL8 are connected to the word line drive circuits 11a and 11B1 via the first transfer transistors 181a to 184a and 181b to 184b, respectively. Further, the source side selection gate line sgs and the drain side selection gate line SGD are connected to the selection gate line driving circuits 120a and 120b via the first transfer transistors 185a, 186a, 185b, and 186b. Further, the back gate line BG is connected to the back gate line driving circuit 170 via the first transfer transistor 1 8 7b. In contrast, as illustrated in Fig. 14B, at time 111, the signal VsELa&lt;x&gt;&amp;VsELb&lt;x&gt; is maintained at voltage VSS due to the change of signal Vbad. That is, the first transfer electric crystals 181a to 186a (181b to 187b) are maintained in the off state. On the other hand, a voltage VDD is applied to the gates of the second transfer transistors 187a and 188a (188b and 189b). This allows the second transfer transistors 187a and 188a (188b and 189b) to be set to the on state. By this operation, the word lines WL1 to WL4 and WL5 to WL8 are set in the floating state in the non-selected memory block MB. Further, the source side selection gate line SGS and the drain side selection gate line SGD are connected to the selection gate line driving circuits 120a and 120b via the second transfer transistors 188a, 187a, 188b, and 189b. Further, the back gate line BG is set to a floating state. Next, as illustrated in FIG. 14A, at time t12, the signals VSGS1, 144995.doc -26- 201029011

Vsgs2, VSGD丨, VSGD2, VSG0FF, VCG丨 to VCG8 and VBG are boosted from the ground voltage Vss to the supply voltage Vdd. As illustrated in FIG. 14B, at time t12, due to the change of the signals VsGs1, VsGS2, VSGD1, VSGD2, VSG0FF, VCG1 to VCG8&amp; VBG, the signals VSGIM&lt;i&gt;, VSGD2&lt; in the selected memory block MB ;i&gt;,

VsGSl&lt;i&gt;, VSGS2&lt;i&gt;, VCG丨&lt;i&gt; to Vcgso and VBG&lt;i&gt; are raised to a certain voltage Vdd-Vth. On the other hand, as illustrated in FIG. 14B, at time ti2, due to the signals Vsgsi, VSGS2, VSGD1, VSGD2, VSG0FF, 乂(:(}1 to ¥(;(58 and ¥8(3 change 'in The signals VsGm &lt;x&gt;, VSgd2&lt;x&gt;, VSGS1&lt;X&gt;&VSGS2&lt;X&gt; in the non-selected memory block MB are boosted to the certain voltage vdd-Vth. Further, as illustrated in Fig. 14B, at time ^ 2. The signal Vs1 is boosted to the power supply voltage vdd at the source line drive circuit 160. Further, at time t12, the signal VRST is boosted to the voltage vpp at the sense amplifier circuit 15A. Due to the change of the signal VRST, at time Ti 2, the voltage of the signal vBL is set to the power supply voltage Vdd. Subsequently, as illustrated in Fig. 14B, at time t13, the signal Vs1 starts to rise toward the erase voltage Vera at the source line drive circuit 160. Therefore, the signal Vbl is also Beginning toward the erase voltage Vera rises. The control mentioned above at time 113, as indicated by the labels "A" and "B" in Figure 4b, is attributed to the memory string MS (ontology) Face 'signal VSGS1&lt;i&gt;, VSGS2&lt;i&gt;, vSGD1&lt;i&gt;, and vSGD2&lt;i&gt; The potential becomes higher as the signals VSL and VBL are boosted. Then, since time t13, due to the signal VsL and the signals VsGw, Vsgs2 and the signal Vbl 144995.doc -27-201029011 and the signal VSGD1 The potential difference between VSGD2 causes a GIDL current. Next, as illustrated in Fig. 14B, at time t14, the signal VSL is set to the erase voltage Vera. Therefore, as illustrated in Fig. 14A, in the selected memory block MB The middle signals VCG1 to VCG8 and VBG are set to the ground voltage Vss. That is, at time t14, the transfer transistor 112B illustrated in FIG. 3 is set to the "on" state. As illustrated in FIG. 14B, 'attributed to The change of the signal Vcg 丨 to Vcg8 &amp; vbg 'at time t14, the signals vCG1 &lt;i&gt; to Vcgso and VBG&lt;i&gt; are set to the ground voltage Vss in the selected memory block mb. After the control at time t14, The hole H caused by the GIDL current is fed into the gates of the memory transistors MTrl to MTr8, and then the execution of the erase operation is started. Subsequently, at time t15, all signals are set to the ground voltage as illustrated in Fig. 14A. Vss. Therefore, as shown in Figure 14B Description, all signals is set to a ground voltage Vss at time tl5. That is, the erase operation ends at time ^. ❹ (Advantages of Nonvolatile Semiconductor Storage Device in First Embodiment) The advantages of the nonvolatile semiconductor storage device according to the first embodiment will now be described hereinafter. As described above, the non-volatile semiconductor storage device of the first embodiment increases the source side select (four) line SGS and the non-polar side select line line to a certain voltage burst, and the source sail and the bit The line is raised to the power supply voltage Vdd. Thereafter, the non-volatile semiconductor storage device starts to raise the source line SL and the bit line muscle to the erase voltage I.

This #operation' following cycle will occur: (1) source line and bit 'boost, (2) between source line SL and source side select gate line SGS 144995.doc •28· 201029011 and in the bit Between the line BL and the drain side selection gate line SGD, the GIDL current is generated; (3) the potential of the body of the memory string MS is increased; and (4) the source side selection gate line SGS and the drain side selection gate The respective potentials of the line SGD are increased due to coupling with the body of the memory string MS. Through the above-mentioned loops (1) to (4), the potential of the body of the memory string MS, the potential of the source side selection gate line SGS, and the potential of the drain side selection gate line SGD also rise. The non-volatile semiconductor storage device of the first embodiment can achieve an effective data erasing operation using the GIDL current caused by the above-mentioned operation. In addition, because of the configuration described above, the non-volatile semiconductor storage device in the first embodiment does not need to be in time with the source line SL and the bit line BL to select the corresponding source side. The gate line S(}S and the drain side select gate line SGD are boosted. That is, the non-volatile semiconductor memory device is not required to control the source side select gate line SGS and the drain side select gate. Any circuit in which the line SGD is boosted. Therefore, the nonvolatile 半导体 semiconductor storage device can suppress an increase in its occupied area. [Second Embodiment] (Non-volatile semiconductor storage device in the second embodiment) The configuration of the non-volatile semiconductor storage device according to the second embodiment will now be described with reference to Fig. 15 and Fig. 16. Fig. 15 is a circuit diagram of the nonvolatile semiconductor storage device according to the second embodiment. (10) A circuit diagram of the sense amplifier circuit 150a according to the second embodiment. Note that the same reference numerals denote the same components as those of the first embodiment, and a description thereof will be omitted in the second embodiment 144995.doc - 29· 20102 9011, the non-volatile semiconductor storage device of the second embodiment is different from the first embodiment only in the sense amplifier circuit 15A as illustrated in Fig. 15. As illustrated in Fig. 16, with the first embodiment The only difference is the connection included in each of the transistors 151c in the sense amplifier circuit 15A according to the second embodiment. Each of the transistors 151 (one end is connected to the bit line and the other end) Connected to the ground. (Erase Operation of Nonvolatile Semiconductor Storage Device in First Embodiment) Referring now to Figures 17 and 18, the erasing of the nonvolatile semiconductor storage device according to the second embodiment will be described hereinafter. Figure 17 is a diagram for explaining the GIDL current according to the second embodiment; and Figure 18 is a timing chart illustrating the erasing operation thereof. Unlike the first embodiment, in the erasing operation of the second embodiment, As indicated by the label "A" in Fig. 17, by the end of the source side conduction layer 41a (source side selection gate line sgs) on the source line layer 51 (source line SL) side Establishing a higher electric field to cause a GIDL current. That is, according to the second embodiment As indicated by time t 2 to 11 5 in FIG. 18, only the voltage of the source line SL is controlled without controlling the voltage of the bit line bl. The erasing operation in the second embodiment is otherwise The erase operation described in one embodiment is the same. (Advantages of the Nonvolatile Semiconductor Storage Device in the Second Embodiment) The nonvolatile semiconductor storage device according to the second embodiment has the features and advantages of the first embodiment. The same features and advantages. [Third Embodiment] (Configuration of Nonvolatile Semiconductor Storage Device in Third Embodiment) 144995.doc -30- 201029011 Referring now to FIG. 19', a third embodiment will be described hereinafter. Configuration of a non-volatile semiconductor storage device. Fig. 19 is a circuit diagram of a nonvolatile semiconductor storage device in the third embodiment. Note that the same reference numerals denote the same components as those of the first embodiment and the second embodiment, and a description thereof will be omitted in the third embodiment. As illustrated in FIG. 19, the nonvolatile semiconductor storage device of the third embodiment has a memory cell array AR1a and a control circuit ARa2 different from the memory cell array and control circuit of the first embodiment and the second embodiment. . As illustrated in Fig. 19, the memory cell array AR1a has m rows of memory blocks MBa. Each of the memory blocks MBa includes an n-column and a 4-row memory string MSa, source-side selection transistors SSTra each connected to one end of the memory string MSa, and each connected to the other end of the memory string MSa. Select the transistor SDTra on the drain side. Note that in the example of FIG. 19, the first line indicates by (1) that 'the second line is represented by (2), the third line is represented by (3)' and the fourth line is represented by (4) . As illustrated in Fig. 20, each memory string MSa has a memory transistor MTral to MTra4. The memory transistors MTral to MTra4 are connected in series. The memory transistors MTral to MTra4 including the MONOS structure allow charge to accumulate in the respective control gates. As illustrated in Fig. 20, the control gates of the memory transistors MTral to MTra4 are connected to the word lines WLal to WLa4. The word lines WLal to WLa4 together provide control gates of the respective memory transistors MTral to MTra4 aligned in a matrix form in the column direction and the row direction. As illustrated in Figure 20, the drain of each source side select transistor SSTra 144995.doc -31 - 201029011 is connected to the source of the memory transistor 逍. The source of each of the source side selection electro-optic bodies SSTra is connected to the first-source view. Each source-source side selects the control transistor of the SSTra to be connected to the source side selection gate line 8 . As illustrated in FIG. 19, each of the first source lines is commonly supplied to the source of the source side selected in the column direction to select the source of the electric (four), and is formed to cross the plurality of memory strings "in the column direction" The first source line SLAa* aligned in the row direction is connected to a single second source line SLBa extending in the row direction. Each source side selection gate line SSa is provided in the column direction and the row direction. The control gate of the transistor SSTra is selected on the source side aligned in the form of (4). As illustrated in Fig. 20, one end of each of the drain side selection transistors SDTra is connected to one end of the memory transistor. The other end of each of the drain side selection transistors SDTra is connected to the bit line BLa. The control gate of each of the drain side selection transistors SDTra is connected to the drain side selection gate line SGDa, as shown in FIG. It is to be noted that each bit line BLa is commonly supplied to one end of the drain side selection transistor 3 aligned in the row direction, and is formed to extend in the row direction across the plurality of memory blocks MBa. Each of the drain side selection gate lines SGDa is provided together in the column direction The upper gate side selects the control gate of the transistor SDTra and is formed to extend in the column direction across the plurality of memory strings MSa. As illustrated in Fig. 19, the control circuit AR2a has: an input/output circuit 100, a word line driving circuit 11〇c, a selection gate line driving circuit 120a·, a bit address decoder circuit 13〇, a boosting circuit 14〇8 to 14〇c, —144995.doc -32- 201029011 Amplifier circuit 150, a source line driver circuit 160, a first column decoder circuit 180c, a second column decoder circuit 180d, and a sequencer 190. As shown in Figure 19, the word line driver circuit n〇c The signals VCG1 to VCG4 for driving the word lines WLal to WLa4 are output. The word line driving circuit 1 i 〇 c has substantially the word line driving circuits 11 〇 a and 110 b in the first embodiment and the second embodiment (see FIG. 3) The same configuration is configured. The gate line driving circuit 120a is selected to output signals Vsgs, VsGD1 to vSGD4 and VSG0FF. The signal Vsgs is used to drive the source side selection gate line SGSa in the selected memory block MBa. Signals VsGDi to Vsgd4 are used to drive the selected

Select the gate line SGDal to SGDa4 on the drain side of the memory block MBa. #说vSG〇FF is used to drive the source side selection gate line SSa and the drain side selection gate line sGDal to SGDa4 in the non-selected memory block MBa to provide the first column decoder circuit 180c and the second column, respectively. The decoder circuit 1 80d' has a column decoder circuit for each memory block MBa. Each of the first column decoder circuits 18c is provided at one end of the respective memory block MBa in the column direction. Each of the second column decoder circuits 丨8〇d is provided at the other end of each memory block MBa in the column direction. Based on the signal vBAD output from the address decoder circuit 130, each of the first column decoder circuits 180c selectively inputs signals to the gates of the 5 memory cells MTral to]ViTra4. Each of the first column decoder circuits 18A has a voltage conversion circuit 180cc and first transfer transistors 181c to 184c. The voltage conversion circuit 18 〇cc generates a signal 'VsELL&lt;i&gt; based on the signals received by 144995.doc -33-201029011, and the signal VSELL is output to the gates of the first transfer transistors 181c to 184c. The gates of the first transfer transistors 181c to 184c receive the signal VSELL&lt;i&gt; from the voltage conversion circuit 180cc. The first transfer transistors 181c to 184c are connected between the word line drive circuit 111c and the word lines WLal to WLa4. The first transfer transistors 181c to 184c output signals VCG1 &lt;i:^ VCG4&lt;i&gt; to the word lines WLal to WLa4 based on the signals VcG1 to Vcg4 and VsELL&lt;i&gt;. Based on the signal VBAD output from the address decoder circuit 130, each of the second column decoder circuits 180d selectively inputs the signal VSGS&lt;i&gt; to the gates of the four rows of source side selection transistors sSTra. Further, based on the signal vBAD, the second column decoder circuit 180d selectively inputs the signals VSGD1 &lt;i&gt; to VSGD4 &lt;i&gt; to the gates of the drain side selection transistors SDTra in the first to fourth rows. Each of the second column decoder circuits 18 (1 has: a voltage conversion circuit 180dd, first transfer transistors 181d to 185d, and second transfer transistors 181d' to 185d'. The voltage conversion circuit 180dd is based on the received signal The voltages of Vbad and vRDEC generate a signal VsELR&lt;i&gt;, and the signal is output to the gates of the first transfer transistors 181d to 185d. Further, the voltage conversion circuit 180d controls the second transfer based on the received signal Vbad&Vrdec The gates of the transistors 181 d' to 185d1. The gates of the first transfer transistors 181d to 185d receive signals from the voltage conversion circuit 180dd. The first transfer transistor 181d is connected to the selection gate line driver circuit 120a'. In addition, the first transfer transistors 182d to 185d are respectively connected to the selection gate line driving circuit 120a and the drain side selection gate line sGDa aligned in the four rows. 144995.doc 34- 201029011. The first transfer transistor 181(} selects the gate line SGSa input signal VsGS&lt;i&gt; based on the signal VsGs&VsELR&lt;i&gt; to the source side. In addition, the first transfer electric b body 182d to 185d base Shu vSGD signal to vSGD4 & vSELR &lt; i &gt; to the drain side select gate are aligned in four rows of source lines of the input signal Yi in SGDa deduction) 1 &lt;; &gt;! To

VsGD4 &lt;i&gt; ° The second transfer transistors 181d' to 185d, the gate receives a signal from the voltage conversion circuit 180dd. The second transfer transistor 181d is connected between the selection gate line driving circuit 120a' and the source side selection gate line SSa. Further, the second transfer transistor 丨 82 (1' to 185d is connected between the selection gate line driving circuit 120a' and the drain side selection gate line sGDa aligned in the four rows. The crystal 181d' selects the gate line SSa input signal VSGS&lt;i&gt; to the source side based on the signal vSG0FF. Further, based on the signal Vsg〇ff, the second transfer transistors 182d' to 185d are aligned in four rows. The pole side selection gate line SGDa input signal VsGD1 &lt; id VsGD4 &lt;i&gt;. (Layer structure of the nonvolatile semiconductor storage device in the third embodiment) Referring to FIG. 21 and FIG. 22, the following will be described according to the third Fig. 21 is a schematic perspective view showing a part of the memory cell array AR1a in the nonvolatile semiconductor memory device according to the third embodiment. Fig. 22 is a view of Fig. 21. A partial cross-sectional surface view. As illustrated in Fig. 21, a memory cell array AR1a is provided on a substrate 1a. The memory cell array AR1a has a source side selective transistor layer 60 and a memory transistor layer 70. One side The transistor layer 8〇 and the wiring layer 90 are selected. The substrate i〇a serves as the source-source line SLAa (source line this hook. Source 144995.doc • 35- 201029011 Polar-side selection transistor layer 60 serves as the source side selection The transistor SSTra. The memory transistor layer 70 functions as a memory transistor MTral to MTra4 (memory string MSa). The drain side selection transistor layer 80 serves as a drain side selection transistor SDTra. The wiring layer 90 serves as a bit line BLa. As illustrated in FIGS. 21 and 22, 'different from the first embodiment, the substrate i〇a has a diffusion layer 11a on its surface. The diffusion layer 11a serves as the first source line SLAa (source line SLa). As shown in Fig. 21 and Fig. 22, the source side selective transistor layer 60 has a source side conduction layer 61. Each of the source side conduction layers 61 is expanded in the column direction and the row direction in parallel with the substrate 1 &amp; Formed in the form of a plate. The source side conductive layer 6) is separated for each memory block MBa. The source side conductive layer 61 comprises polycrystalline (p-Si). Each source side conductive layer 61 acts as a The source side selects the gate line s GS a. Each source side conduction layer 6 i also serves as a gate of the source side selection transistor SSTra As illustrated in Fig. 22, the source side selective transistor layer 6A also has a source side hole 62. The source side hole 62 is formed to penetrate the source side conduction layer 6A. The source side hole 62. Formed in a matrix form at a position matching the diffusion layer 11 a in the column direction and the row direction. As illustrated in FIG. 22 , the source side selection transistor layer 6 〇 also has a source side gate insulating layer 63 and A source side columnar semiconductor layer 64. The source side gate insulating layer 63 is formed to have a certain thickness on the side wall of the source side hole 62. The source side columnar semiconductor layer 64 is formed to be in contact with the side surface of the source side gate insulating layer 63 and fills the source side hole 62. The source side columnar semiconductor layer 64 is formed to be perpendicular to The columnar shape extending in the direction of the substrate 1〇a is in contact with the diffusion layer 1 la of 144995.doc -36 - 201029011. The source side gate insulating layer 63 contains hafnium oxide (Si〇2). The source side columnar semiconductor layer 64 contains polycrystalline germanium (p-Si). The above-mentioned configuration of the source side selection transistor layer 60 is restated as follows: The source side gate insulating layer 63 is formed to surround the source side columnar semiconductor layer 64. Further, each source side conducts The layer 61 is formed to surround the source side gate insulating layer 63. As illustrated in Figures 21 and 22, the memory transistor layer 7A has stacked word line conductive layers 71a to 71d. Each of the word line conductive layers 71a to 71d is formed in the form of a plate which is expanded in the column direction and the row direction in parallel with the substrate 10a. The word line conductive layers 71a to 71d are separated for each memory block MBa. The word line conductive layers 71a to 71d include polysilicon (p_si) » word line conductive layers 71a to 71«1 function as word lines 1\^1^1 to the stomach 1^4. The word line conductive layers 71 &amp; to 71 (1 also serve as gates of the memory transistors MTral to MTra4. As illustrated in Fig. 22, the memory transistor layer 70 also has a memory hole 72. The memory hole 72 is Formed to penetrate the word line conductive layers 71a to 71d. The memory holes 72 are formed in a matrix form at a position matching the source side holes 62 in the column direction and the row direction. The memory transistor layer 70 also has: a region The block insulating layer 73a, a charge storage layer 73b, a tunneling insulating layer 73c, and a memory columnar semiconductor layer 74. The memory columnar semiconductor layer 74 serves as a body of the memory string MSa. The block insulating layer 7 3 a It is formed to have a certain thickness on the sidewall of the source side hole 7.2. The charge storage layer 73b is formed to have a certain thickness on the sidewall of the block insulating layer 73a 144995.doc -37· 201029011. The tunneling insulating layer 73c is The memory is formed to have a certain thickness on the sidewall of the charge storage layer 73b. The memory columnar semiconductor layer 74 is formed to be in contact with the sidewall of the via insulating layer 73c and fill the memory hole 72. The memory columnar semiconductor layer 74 is formed. With the source side columnar semi-derivation described below The top surface of the layer 64 is in contact with the bottom surface of the drain-side columnar semiconductor layer 84, and extends a in a direction perpendicular to the substrate 10. The block insulating layer 73a and the tunneling insulating layer 73c contain germanium dioxide (Si〇). 2) The charge storage layer 73b contains tantalum nitride (SiN). The memory pillar semiconductor layer 74 contains polysilicon (p-Si). _ The above mentioned configuration of the memory transistor layer 70 is re-stated as follows: tunneling The insulating layer 73c is formed to surround the memory columnar semiconductor layer 74. The charge storage layer 73b is formed to surround the tunneling insulating layer 73c. The block insulating layer is formed to surround the charge storage layer 73b. The word line conductive layer 713 to 71 (1 is formed to surround the block insulating layer 73a. As illustrated in FIGS. 21 and 22, the drain side selective transistor layer 8A has a drain side conductive layer 81. The drain side conductive layer 81 is formed to A strip pattern in which a certain pitch in the row direction extends in the column direction. _ and the pole side conductive layer 81 include polycrystalline stone (p_si). Each of the drain side conductive layers 81 functions as a drain side selective gate line SGDa. A drain side conductive layer 81 also serves as a gateless selection transistor SDTra. As illustrated in Fig. 22, the drain side selective transistor layer 8A also has a drain side hole 82. The drain side hole 82 is formed to penetrate the drain side conductive layer 81. 82 is formed in a matrix form at a position matching the memory hole 7 2 in the 歹1J direction and the row direction. 144995.doc -38 - 201029011 As illustrated in FIG. 22, the drain side selection transistor layer 8 〇 also has a The drain side gate insulating layer 83 and the drain side pillar type semiconductor layer 84. The gate side gate insulating layer 83 is formed to have a certain thickness on the sidewall of the drain side hole 82. The 极 pole side columnar semiconductor layer 84 is formed in contact with the side wall of the drain side gate insulating layer 83 to fill the gate side hole 82. The electrodeless side columnar semiconductor layer 84 is opened to extend in a direction perpendicular to the substrate 1a to contact the top surface of the memory columnar semiconductor layer 74. The gate electrode insulating layer 83 includes cerium oxide (the Si 〇 2p 侧 柱 columnar semiconductor layer 84 includes polysilicon (p_si). As illustrated in FIGS. 21 and 22, the wiring layer 90 has a bit line layer 91. The bit line layer 91 is formed into a stripe pattern extending in the row direction at a certain pitch in the column direction. The bit line layer 91 is formed in contact with the top surface of the drain side columnar semiconductor layer 84. The layer 9 1 contains polycrystalline spine (p_si). Each bit line layer 91 serves as a one-dimensional line BLa. (Erasing operation of the non-volatile semiconductor storage device in the third embodiment) Referring now to Fig. 23, The erasing operation of the nonvolatile semiconductor storage device according to the third embodiment will be described hereinafter. In the erasing operation according to the third embodiment, as indicated by the label "A" in Fig. 23, A higher electric field is generated at the end of the source side conduction layer 61 (source side selection gate line SSa) on the diffusion layer 11a (source line SLa) side to cause a GIDL current. Also by the bit line layer 91 ( Higher power is established at the end of the non-polar side conduction layer 81 (drain side selection gate line SGDa) on the side of the bit line BLa) While causing the GIDL current, the erasing operation 144995.doc • 39- 201029011 in the third embodiment is otherwise identical to the erasing operation described in the first embodiment. (Non-volatile semiconductor storage in the third embodiment) Advantages of the Device The non-volatile semiconductor storage device according to the third embodiment has the same features and advantages as those of the first embodiment. [Fourth Embodiment] (Non-volatile semiconductor storage in the fourth embodiment) Configuration of Apparatus Referring now to Figure 24, the configuration of the non-volatile semiconductor storage device according to the fourth embodiment will be described hereinafter. Figure 24 is a circuit diagram of the non-volatile semiconductor storage device in the fourth embodiment. The same reference numerals denote the same components as those of the first to third embodiments, and the description thereof will be omitted in the fourth embodiment. As illustrated in Fig. 24, the non-volatile in the fourth embodiment The semiconductor storage device has a control circuit AR2b different from the control circuits of the first to third embodiments. Instead of the selection gate lines in the first to third embodiments The driving circuits 120a and 120b, the boosting circuit 140C, the source line driving circuit 160, the first column decoder circuit 18a and the second column decoder circuit 180b, and the control circuit AR2b have the selection gate line driving circuits 120c and 120d. a one-liter circuit 140D, a source line driver circuit 160a, and a first column decoder circuit 180e and a second column decoder circuit 18〇f. The control circuit AR2b has a liter in addition to the configuration of the second embodiment. The voltage circuit 140E. In this regard, the control circuit AR2b according to the fourth embodiment is different from the control circuits of the first to third embodiments. As illustrated in Fig. 25, each of the selection gate line driving circuits 12〇c (12〇d) I44995.doc • 40- 201029011 has a first selection gate line driving circuit 120D to a third selection gate line driving circuit 120F. The first selection gate line driving circuit 120D outputs a signal VSG0FF. The second selection gate line driving circuit 120E outputs a signal Vsgsi (Vsgs2). The third selection gate line flicking circuit 120F outputs a signal

VsGD2 (VsgD1). The signals VsGOFF, VsGS1 (VsGS2), and VsGD2 (VSGJD1) have the same potential as the ground voltage Vss, the power supply voltage Vdd, and the signal Ve2, respectively. As illustrated in FIG. 25, each of the first selection gate line driving circuits 120D has a first circuit 121D and a second circuit 122D. As illustrated in Fig. 25, the output terminal of the first circuit 121D is connected to the output terminal of the second circuit 122D. The first circuit 121D receives the signal Ve2 from the booster circuit 104D and the signal ERASE from the sequencer 190. If the signal ERASE is in the "high" state, the J first circuit 121D outputs the received signal Ve2. The signal ERASE is set to the "High" state when the erase operation is performed. The second circuit 122D receives the signals READ, SAi, ERASE and PROGRAM from the sequencer 190. The signal READ is set to the "High" state when the read operation is performed. The signal PROGRAM is set to the "on" state when a write operation is performed.

The second circuit 122D outputs a signal at the power supply voltage Vdd or the ground voltage Vss based on the received signal. If the signals READ, SAi, and ERASE are in the "high" state, the second circuit 122D outputs a signal at the power supply voltage Vdd. If the signals PROGRAM and ERASE are in the "low" state, and if the signals READ and SAi are in the "high" state, the second circuit 122D 144995.doc -41 - 201029011 outputs a signal at the ground voltage vss. As illustrated in Fig. 26A, each boosting circuit i4〇D has an oscillating circuit 141D, a first signal generating circuit 1UD, a second signal generating circuit 143D, and a third signal generating circuit 144D. As illustrated in Fig. 26B, the oscillation circuit 141D is a ring oscillator including a NOR circuit 141Da and inverter circuits 14iDb to 141De. The oscillating circuit 141D outputs the oscillating signal Vos based on the signal bEN from the third signal generating circuit 144D. The oscillation circuit 141D outputs the oscillation signal Vos' only when the signal bEN is in the "low" state and does not output the oscillation signal Vos when the signal bEN is in the "high" state. As illustrated in Fig. 26A, the first signal generating circuit i42d boosts the voltage of the signal Vel based on the oscillating signal Vos from the oscillating circuit 141D. Further, based on the signal bEN (differential signal), the first signal generating circuit 142D switches between the operating state and the stop state depending on the oscillating signal Vos from the oscillating circuit 141D. The voltage of the signal Vel is set to the ground voltage Vss or the power supply voltage Vdd. Further, the voltage of the signal Vel is boosted from the power supply voltage vdd to the erase voltage Vera 1. The signal Vel is output to the source line driving circuit i6〇a. As illustrated in Fig. 26A, the first signal generating circuit 142D has a charge buffer circuit 142Da and a transistor 142Db. The charge pump circuit i42Da boosts the signal Ve1 from the power supply grind Vdd to the erase voltage Veral based on the wobble signal Vos. The power supply voltage Vdd is supplied to one end of the transistor i42Db. Further, the signal RST1 is input from the sequencer 190 to the gate of the transistor 142Db, and the other end of the transistor 142Db is connected to the output terminal of the charge pump circuit i42Da. If the signal RST1 is in the "local" state, the electric crystal boat 142Db 144995.doc -42 - 201029011 goes to the "on" state. As a result, the signal Ve 1 is fixed to the power supply voltage vdd. As illustrated in FIG. 26A, the second signal generating circuit 143D generates the signal Ve2 based on the signal Vel from the first signal generating circuit 142D. Further, the first signal generating circuit 143D switches between the operational state and the non-operating state depending on the signal bEN from the third signal generating circuit 144D. The voltage of the signal Ve2 is set to the ground voltage Vss or the power supply voltage Vdd. Further, after a certain delay time elapses since the signal Ve 1 is boosted, the voltage of the signal Ve2 is boosted from the power source voltage Vdd to the voltage Vera2 (Vera2 &lt; Veral). The signal Ve2 is boosted by the boost of the signal Vel. The signal Ve2 is output to the selection gate line driving circuits 120c and 120d. The second signal generating circuit i43d as illustrated in Fig. 26A has a delay circuit 143Da, a switching circuit 143Db, and a transistor 143Dc. The delay circuit 143Da delays the signal Vel for a certain period of time and reduces the voltage of the signal Ve1 by a certain amount, thereby generating a signal. The switching circuit 143Db controls whether or not the signal from the delay circuit 143Da is output as the signal Ve2 based on the output signal bEN of the third signal generating circuit 144D. As illustrated in Fig. 26A, the switching circuit i43Db has a one-bit shifter circuit 143Db1 and a transistor 143Db2. As illustrated in Fig. 26C, when the signal bEN is in the "low" state, the level shifter circuit i43Dbi outputs the received 彳 § Vel. One end of the transistor 143Db2 is connected to the output terminal of the delay circuit 143Da. A gate of the transistor 143Db2 is connected to the output terminal of the level shifter circuit 143Dbl. When the signal from the level shifter circuit 143 Dbl is in the "high" state, the transistor m3 Db2 is switched to the "on j state. 144995.doc -43- 201029011, as illustrated in Fig. 26A, the transistor 143" The source of 0 is connected to the output terminal of the switching circuit 143Db (the source of the transistor 143Db2). The power supply voltage Vdd is applied to the drain of the transistor 143Dc, and the transistor 143£) (: has the signal received from the input of the sequencer 190) Gate RST2. If the signal RST2 is in the "high j state", the transistor 143Dc is turned to the "on" state. As a result, the voltage of the output terminal of the switching circuit 143Db is fixed to the power supply voltage V (id. As shown in Fig. 26A Note that the third signal generating circuit i44D outputs the signal bEN. The third signal generating circuit 144D generates the signal % based on the signal Ve2. The signal Va has a voltage generated by reducing the voltage of the signal Ve2 by a certain amount. The circuit 144D compares the voltage of the signal Va with the reference potential (reference voltage) Vref to output a signal bEN. The signal Va has a relationship with the signal Vel. As illustrated in Fig. 26A, the third signal generating circuit M4D has: The voltage drop circuit 144Da, a reference potential generating circuit i44Db, and a differential amplifier circuit 144Dc. As illustrated in Fig. 26A, the voltage drop circuit i44Da generates a signal Va at a voltage which is reduced by a certain amount by the voltage of the k number Ve2. As shown in Fig. 26A, the input terminal of the voltage drop circuit 144Da is connected to the output terminal of the switching circuit 132Db in the second signal generating circuit 143D (the source of the transistor 143Db2). The output terminal of the voltage drop circuit 144Da is connected to the difference. An input terminal of the amplifier circuit 144Dc. As illustrated in Fig. 26A, the reference potential generating circuit 144Db generates a reference potential Vref to be input to the other terminal of the differential amplifier circuit 144Dc. 144995.doc -44 - 201029011 As described, the differential amplifier circuit i44Dc compares the signalized AND signal Vref to output the signal bEN. The boosting circuit 140E generates a signal Vhh generated by boosting the power supply voltage vdd to a certain voltage. As illustrated in Fig. 24, Voltage circuit 140E will signal

Vhh is input to the first column decoder circuit 18〇e and the second column decoder circuit 180f. As illustrated in FIG. 27, based on the signals erase and READ from the sequencer 19, the source line driver circuit 16A receives the signal Vel' input from the booster circuit m〇d and controls the supply to the source line SL. Signal vsl. If the signal READ is in the "high" state, the source line driver circuit 丨6〇b sets the signal vSL to the ground voltage Vss. In addition, if the signal erase is in the "local" state, the source line driving circuit i 6〇b supplies the signal Vel to the source line S1 as the signal vSL. As illustrated in FIG. 24, the first column decoder circuit 18〇e And the second column decoder circuit 180f has transfer circuits 1866 and 185f, respectively, instead of the first transfer transistors 1 86a and 1 85b according to the first embodiment. Each of the transfer circuits 186e & 185f as illustrated in Fig. 28A has a voltage conversion circuit 185A and a transistor 185B. As shown in Figs. 28A and 28B, the voltage conversion circuit i85A receives the signals Vredc2 and VSELa&lt;i&gt;(VSELb&lt;j&gt;) from the booster circuit 140D. Further, the 'transfer circuits 1866 and 185' receive the signal Vhh from the boosting circuit 140E. » The voltage converting circuit 185A outputs the signal vn〇dei based on the signal VsELa&lt;i&gt;(VSELb&lt;i&gt;), and controls the on/off of the transistor 1 mb. Broken. As illustrated in Fig. 28A, one end of the transistor 185B is connected to the selection gate 144995.doc • 45 - 201029011 the pole line driving circuit 120c (120d) and the other end is connected to the source side selection gate line SGS. (Outline of erasing operation of nonvolatile semiconductor storage device in the fourth embodiment) Referring now to Figs. 29 and 30, the erasing operation of the nonvolatile semiconductor storage device according to the fourth embodiment will be hereinafter described. Fig. 29 is a flow chart for explaining the erasing operation of the nonvolatile semiconductor storage device in the fourth embodiment. Figure 30 schematically illustrates the erase operation. First, as indicated by the label "s3i" in FIG. 30, the control circuit AR2b boosts the source side selection gate line sgs and the source line SL to the power supply voltage vdd in the selected memory block Mb (step S31). ). Note that the word lines WL1 to WL8 and the back gate line BG are boosted to a certain voltage Vdd-Vth. Subsequently, as indicated by the label "S32" in FIG. 30, the control circuit AR2b starts boosting the source line sl to the erase voltage Vera 1 ' in the selected memory block MB while being applied to the source. The voltage of the pole line sl is delayed for a certain period of time and the voltage applied to the source line SL is decreased by a certain amount (this voltage is the start of the voltage boost to the erase voltage Vera2). The gate line SGS is selected on the pole side (step S32). That is, the control circuit AR2b and the source line SL are boosted to start boosting the source side selection gate line SGS. This causes a GIDL current. In addition, the word line is slid to "slip", the sluice gate line BG and the drain side selection gate line sgd are set in a floating state. Then the 'control circuit AR2b determines whether the voltage of the source line SL in the selected memory block mb reaches The voltage Veral is erased (step S33). At this point, if it is determined that the voltage of the source line SL reaches the erase voltage Veral ("Υ" at step S33 144995.doc • 46 - 201029011), the control circuit AR2b stops This voltage is boosted (step S34). At step S34, the control circuit AR2b also stops boosting the source side selection gate line SGS. Note that at the stop point, the source side selection gate line SGS has a potential lower than the potential of the source line sl. After the operation at step S34 is performed, the word lines WL1 to WL8 and the back gate line BG are set to the ground voltage Vss (step S35)' by the control circuit AR2b indicated by the label "s35j" in FIG. 3 and will be operated by GID1. The current-induced hole is fed into the gate of the memory transistor He Ding ^ to He Ding. In this way, the data was erased. (Specific erasing operation of the nonvolatile semiconductor storage device in the fourth embodiment) Referring now to Figures 31A and 31B, a specific erasing operation of the nonvolatile semiconductor storage device according to the fourth embodiment will be described hereinafter. Figure 31A and Figure 31B are timing charts illustrating the erase operation. First, as illustrated in Figure 31, at time m, the signal Vbad is inverted. As illustrated in FIG. 31A, due to the change of the signal Vbad, at time 忉1, the signals RST1 and RST2 are dropped from the power supply voltage Vdd to the ground voltage Vss, that is, the transistors i42Db and 143Dc in the boosting circuit 140D are set. In the off state, the signal %丨 output from the booster circuit 14〇D is set to a floating state. Further, as illustrated in Fig. 31B, due to the change of the signal Vbad, the signal Vsel heart and the vSELb&lt;i&gt; from the ground voltage Vss rise to the power supply voltage vdd at the selected memory block MB at time (1). That is, the first 144995.doc • 47· 201029011 transfer transistors 181a to 185a (181b to 184b, 186b, and 187b) are set to the on state. On the other hand, the ground voltage Vss is applied to the gates of the second transfer transistors l87a and 188a (188b and 189b). This allows the second transfer transistors 187a and 188a (188b and 189b) to be set to the off state. By this operation, in the selected memory block MB, the word lines WL1 to WL4 and WL5 to WL8 are respectively connected to the word line drive circuits 11a and 经由 via the first transfer transistors i81a to 184a and 181b to 184b, respectively. In addition, the drain side selection gate line SGD is connected to the selection gate line driving circuits 120c and 120d via the first transfer transistors 185a and 186b, respectively. Further, the back gate line BG is connected to the back gate line driving circuit 170 via the first transfer transistor 187b. Further, as illustrated in Fig. 31B, the signal VnodeA of the transfer transistors i86e and 185f in the selected memory block mb rises to the voltage Vpp at time t3 1 due to the change of the signal Vbad. That is, the transfer transistor 186e and 185f connect the source side selection gate line SGS to the selection gate line driving circuit 12 (^ and 12 〇d) in the selected memory block MB. On the other hand, As illustrated in Fig. 31B, due to the change of the signal Vbad, the signal VsELa &lt;x&gt;&amp;VsELb&lt;x&gt; is maintained at the voltage VSS in the non-selected memory block mb at time t3 1. That is, The first transfer transistors 181a to 186a (181b to 187b) are maintained in an off state. On the other hand, a voltage VDD is applied to the gates of the second transfer transistors 187 &amp; and 188 &amp; (18 and 189b). The first transfer transistor 18 and 188 &amp; 881) and 1891)) are set to the on state. By this operation, the word lines WL1SWL4 and WL5 to WL8 are set in the floating state in the non-selected memory block. In addition, the source side selection gate line SGS and the drain side selection gate line SGD are respectively connected to the selection gate line driving circuit 120c via the second 144995.doc -48·201029011 transfer transistors 188a, 187a, 188b and 189b, respectively. 120d. In addition, the back gate line BG is set to a floating state. Further, as illustrated in Fig. 31B, at time t3 1, the signal vnodeA of the transfer transistor 186e &amp; 185f in the non-selected memory block MB is maintained at the ground voltage Vss. That is, in the non-selected memory block mb, the transfer transistors 186e and 185f keep the source side selection gate line SGS off the selection gate line driving circuits 120c and 120d.

Next, as illustrated in Fig. 31A, at time t32, the signal VSGS and VSGS2 are boosted from the ground voltage Vss to the power supply voltage vdd. Further, at time t32', signals VSGDI, VsGD2, Vsg〇ff, Vcgi to VcG8, and Vbg are grounded to a certain voltage vdd-Vth. As illustrated in Fig. 31B, at time t32' due to changes in signals %(10) and Vsgs2, in the selected memory block? The signal in ^8 and Vsgszo are boosted to the supply voltage Vdd. Also, at time t32, due to

The change of the signal VsGD1 VSGD2, VCG丨 to VCG8 &amp; VBG is boosted to the supply voltage Vdd at the selected line drive circuit 160. The signal vSGDi&lt;i&gt;, VBG&lt;i&gt; is raised to a certain voltage Vdd-Vth in the memory block MB. Further, as illustrated in Fig. 31B, VSGD2&lt;i&gt;, at time t32, the signal VSL is subsequently at the source As illustrated in Fig. 31B, at time (1), the signal Vref is boosted to the boost (1) at the booster circuit 1. Therefore, at time (1), the oscillation circuit 141D starts its operation, and the first signal generating circuit (4) D starts to raise the signal Vel. Next, after a period of time I44995.doc -49 - 201029011 has elapsed since time (1), the second signal generating circuit 143D starts to boost the signal Ve2. Further, as illustrated in Fig. 31B, at time t33, in response to the operation of the above-mentioned booster circuit 140D, the voltage of the signal vSGS1 &amp; VSGS2 starts to rise in accordance with the signal Ve2. As a result, the voltage of the signal in the selected memory block mb starts to rise. The voltage of the signal VsL also starts to rise according to the signal Ve I. Subsequently, as illustrated in Fig. 31A, at time t34, the boosting circuit 14A determines whether the signal Va rises to the voltage Vera3 based on the h-number bEN (i.e., the signal Vel is boosted to a certain voltage). Then, the boosting of the signals Vel and Ve2 is stopped, and the signals Vel and Ve2 are set to the erase voltage veral &amp; Vera2. Further, as illustrated in Fig. 31B, at time t34, in response to the operation of the above-mentioned boost circuit 140D, the boost of the signal Vsgsi &amp; vSGS2 is stopped' and the signals VSGS1 and VSGS2 are set to the erase voltage vera2. As a result, in the selected memory block MB, the signal vSGS1&lt;i&gt;&VsGs2&lt;i&gt;2 boost is stopped&apos; and ##VSGS1&lt;i&gt;&amp;VsGSki> is set to the erase voltage Vera2. The boost of the signal VSL is also stopped, and the signal VsL is set to the erase voltage Veral. Next, as illustrated in FIG. 31A, at time t35, signals %(1) to Vcg8 and vBGs are set to the ground voltage Vss. Via the control at time t35, the hole η caused by the GIDL current is fed into the gates of the memory transistors MTrl to MTr8, after which the execution of the erase operation is started. Next, as illustrated in Figs. 31A and 31B, the erase operation ends at time t36. (Advantages of Nonvolatile Semiconductor Storage Device in Fourth Embodiment) The advantages of the nonvolatile semiconductive storage I44995.doc -50·201029011 storage device according to the fourth embodiment will now be described hereinafter. As described above, the nonvolatile semiconductor storage device of the fourth embodiment has a boosting circuit 140D. The booster circuit 14A generates signals Vel and Ve2. The signal Ve2 is boosted after a certain period of time since the signal Vel is boosted, while maintaining a certain potential difference from the signal Vei. Further, the signal Vel is supplied to the source line SL, and the signal Ve2 is supplied to the source side selection gate line SGS. Using the signals Vel and Ve2' of the boosting circuit 140D as in the first to third embodiments, the non-volatile semiconductor storage device of the fourth embodiment can achieve a data erasing operation with a ^:: using the GIDL current. . Please also note that unlike the first to third embodiments described above, the non-volatile semiconductor storage device of the fourth embodiment does not use between the body of the memory string MS and the source line SL. The coupling ratio is used to generate a GmL current. That is, the nonvolatile semiconductor storage device of the fourth embodiment directly regulates the potentials of the source side selection transistor SSTr and the source line SL to generate a GIDL current. This allows the non-volatile semiconductor storage φ device in the fourth embodiment to perform an erase operation independently of device parameters such as a coupling ratio or a wiring capacitance. Further, the nonvolatile semiconductor storage device of the fourth embodiment can alleviate the stress on the gate of the source side selection transistor SSTr as compared with the first to third embodiments. [Other Embodiments] While the embodiments of the non-volatile semiconductor storage device have been described, the present disclosure is not intended to be limited to the disclosed embodiments, and the disclosed embodiments may be practiced without departing from the spirit of the invention. For example, various other changes, additions, substitutions, or the like are made. 144995.doc -51· 201029011 BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram of a nonvolatile semiconductor storage device according to a first embodiment of the present invention; FIG. 2 is a circuit diagram of a memory string MS according to a first embodiment. 3 is a circuit diagram of a word line driver circuit 110a (110b) according to the first embodiment; FIG. 4 is a circuit diagram of a selection gate line driver circuit 120a (120b) according to the first embodiment; FIG. 6A is a timing diagram illustrating the operation of the boosting circuits 140A to 140C; FIG. 6B is a timing chart illustrating the operation of the boosting circuits 140A to 140C; FIG. 7 is a diagram illustrating the operation of the boosting circuits 140A to 140C; FIG. 8 is a circuit diagram of a sense amplifier circuit 丨5 根据 according to the first embodiment; FIG. 9 is a diagram illustrating a non-volatile semiconductor storage device according to the first embodiment; a schematic perspective view of a portion of the memory cell array AR1;

Figure 10 is a partial cross-sectional view of Figure 9; Figure 11 is a flow chart illustrating the erasing operation according to the first embodiment; Figure 12 is a schematic view illustrating the erasing operation according to the first embodiment; FIG. 14A is a timing chart illustrating an erase operation according to the first embodiment; FIG. 14B is a timing chart illustrating an erase operation according to the first embodiment; FIG. 15 is a timing chart illustrating the erase operation according to the first embodiment; Circuit diagram of a non-volatile semiconductor storage device according to a second embodiment; 144995.doc - 52 - 201029011 FIG. 16 is a circuit diagram of a sense amplifier circuit 15 〇 &amp; FIG. 18 is a timing chart illustrating an erasing operation according to a second embodiment; FIG. 19 is a circuit diagram of a nonvolatile semiconductor storage device according to a third embodiment; 20 is a circuit diagram of a memory string MSa according to a third embodiment; FIG. 21 is a schematic perspective view illustrating a portion of the δ-remembered early-earth array AR1 a in the non-volatile semiconductor storage device according to the third embodiment. Figure 22 is a diagram 21 is a partial cross-sectional view of FIG. 23; FIG. 23 is a circuit diagram for explaining a gidl current according to a third embodiment; FIG. 24 is a circuit diagram of a nonvolatile semiconductor storage device according to a fourth embodiment; FIG. 26A is a circuit diagram of a booster circuit 14OD according to a fourth embodiment; FIG. 26B is a circuit diagram of an oscillating circuit 141D according to a fourth embodiment; FIG. 27 is a circuit diagram of the source line driving circuit 160a according to the fourth embodiment; FIG. 28A is a circuit tgl of the transfer circuits 186e and 185f according to the fourth embodiment. 28B is a circuit diagram of 144995.doc-53-201029011 of the transfer circuits 186e and 185f according to the fourth embodiment; FIG. 29 is a flowchart illustrating an erase operation according to the fourth embodiment. FIG. FIG. 31A is a diagram showing the erasing operation of the fourth embodiment; FIG. 31B is a diagram illustrating the erasing operation according to the fourth embodiment. ] 'Sequence wins FIG. 10 substrate 10a substrate 11a diffusion layer 20 back gate transistor layer 21 back gate conduction layer 22 back gate hole 30 memory transistor layer 3 la~3Id word line conduction layer 32 memory hole 33a block insulating layer 33b charge storage layer 33c Tunneling insulating layer 34 U-shaped semiconductor layer 34a Columnar portion 34b Bonding portion 40 Selecting a transistor layer 41a Source-side conductive layer 41b &gt; and a pole-side conductive layer 144995.doc -54 - 201029011 Reference 42a Source side hole 42b 汲Polar side hole 43a Source side gate insulating layer 43b Side side gate insulating layer 44a Source side columnar semiconductor layer 44b Side side columnar semiconductor layer 50 Wiring layer 51 Source line layer 52 Plug layer 53 bits Line layer 60 Source side selection transistor layer 61 Source side conduction layer 62 Source side hole 63 Source side gate insulating layer 64 Source side columnar semiconductor layer 70 Memory transistor layer 71a to 71d Word line conduction layer 72 memory hole 73a block insulating layer 73b charge storage layer 73c tunneling insulating layer 74 memory columnar semiconductor layer 80 drain side selective transistor layer 81 drain side conductive layer 144995.doc -55- 201029011 82 汲Side hole 83, no-pole side gate insulating layer 84, drain side columnar semiconductor layer 90, wiring layer 91, bit line layer 100, input/output circuit 110A, first word line driver circuit 110a, word line driver circuit 110B, second word line driver circuit 110b word line driver circuit 110C third word line driver circuit 110c word line driver circuit 110D fourth word line driver circuit 111A to 111C voltage conversion circuit 112A-112C transfer transistor 120A first selection gate line driver circuit 120a select gate line Drive circuit 120a' select gate line drive circuit 120B second select gate line drive circuit 120b select gate line drive circuit 120C third select gate line drive circuit 120c select gate line drive circuit 120D first select gate line drive Circuit 120d selects gate line driver circuit 144995.doc - 56 - 201029011 120E first selection gate line driver circuit 120F third selection gate line driver circuit 121A voltage conversion circuit 121B voltage conversion circuit 121D first circuit 122A transfer transistor 122B Transfer transistor 122D second circuit ® 130 address decoder circuit 140A-140C liter Circuit MOD Boost Circuit 140E Boost Circuit 141D Oscillation Circuit 141Da NOR Circuit 141Db to 141De Inverter Circuit A 142D Reference First Signal Generation Circuit 142Da Charge Pump Circuit 142Db Transistor 143a to 143n Diode 143D Second Signal Generation Circuit 143Da Delay circuit 143Db switching circuit 143Dbl level shifter circuit 143Db2 transistor 144995.doc -57- 201029011 143Dc transistor 144a~1441 charging and discharging circuit 144A AND circuit 144B inverter 144C capacitor 144D third signal generating circuit 144Da voltage drop Circuit 144Db reference potential generating circuit 144Dc differential amplifier circuit 150 sense amplifier circuit 150a sense amplifier circuit 151 selection circuit 151a page buffer 151b transistor 151c transistor 152A voltage conversion circuit 152B voltage conversion circuit 160 source line driver circuit 160a source Polar line drive circuit 161A-161C voltage conversion circuit 162A-162C transfer transistor 170 back gate drive circuit 180a first column decoder circuit 1 80aa voltage conversion circuit 144995.doc -58- 201029011 180b second column decoder circuit 18 0bb voltage conversion circuit 180c first column decoder circuit 1 80cc voltage conversion circuit 180d second column decoder circuit 180dd voltage conversion circuit 180e first column decoder circuit 180f second column decoder circuit ® 181a to 186a first transfer transistor 181b to 187b first transfer transistors 181c to 184c first transfer transistors 181d to 185d first transfer transistors 181d' to 185d' second transfer transistor 185A voltage conversion circuit 185B transistor A 185f transfer circuit 186e transfer circuit 187a Two transfer transistor 188a second transfer transistor 188b second transfer transistor 189b second transfer transistor 190 sequencer AR1 memory cell array AR1 a memory cell array 144995.doc -59- 201029011 AR2 control circuit AR2a control circuit AR2b Control circuit bEN signal BG back gate line BL bit line BLa bit line BTr back gate transistor E electron ERASE signal H hole MB memory block MBa memory block MS memory string MSa memory string MTrl ~MTr8 memory Body transistor MTral ~MTra4 memory transistor PROGRAM signal READ letter RST1 signal RST2 signal Sai signal SDTr drain side selection transistor SDTra drain side selection transistor 144995.doc -60- 201029011 SGD drain side selection gate line SGDa drain side selection gate line SGDal ~SGDa4 side selection Gate line SGS Source side selection gate line SSa Source side selection gate line SLA First source line SLAa First source line SLB First source line ® SLBa First source line SSTr Source side selection Crystal SSTra Source side selection transistor til time tl2 time tl3 time tl4 time A tl5 time t31 time t32 time t33 time t34 time t35 time t36 time Va signal Vbad signal I44995.doc -61 - 201029011

Vbg signal VbG&lt;i&gt; signal Vbl signal VcG1 to VcG4 signal VcG 1 &lt;i&gt;~Vcg4&lt;i&gt; signal VCG5 to VCG8 signal VcG5&lt;i&gt;~Vcg8&lt;i&gt; signal VCUT signal Vdd power supply voltage Vdd-Vth voltage Vel signal Ve2 signal Verl erase voltage Ver2 erase voltage Vera erase voltage V era signal Vera3 erase voltage Vhh signal Vnode 1 signal VnodeA signal Vos oscillation signal V PASS signal Vpp voltage V PRO signal 144995.doc -62- 201029011

V rdec signal V REDC2 signal Vref reference potential VRST signal V SELa &lt; i &gt; signal V SELb &lt; i &gt; signal V SELL &lt; i &gt; signal V SELR &lt; i &gt; signal V SGD1 ~ VsGD4 signal V SGDl &lt; i &gt; ~ VsGD4 &lt; i &gt; Signal VsGOFF signal V SGS signal V SGS &lt; i &gt; signal VsGS 1 signal VsGS2 signal VsGS2 &lt; i &gt; signal VSL signal Vss ground voltage Vth potential difference WL1 ~ WL8 word line WLal ~ WLa4 word line φ 信号 signal φ2 signal 144995.doc -63-

Claims (1)

201029011 VII. Patent application scope: 1. A non-volatile semiconductor storage device comprising: - a memory string 'which comprises a plurality of memory cells connected in series; - a -selective transistor ' having a connection to the memory One of the strings • one end of one end of each individual; • a first wiring 'having an end connected to the other end of the first selection transistor; a second wiring connected to the first Selecting a gate of the transistor; and a 10-control circuit configured to perform an erase operation to erase data from the memory cells, the memory string comprising: a first semiconductor layer having a a columnar portion extending in a direction perpendicular to a substrate; a charge storage layer formed to surround the first semiconductor layer; and a first conductive layer surrounding the charge storage layer and parallel to Extending the substrate, The first selection transistor comprises: a second semiconductor layer in contact with a top surface or a bottom surface of the columnar portion and extending in a direction perpendicular to the substrate; - a first gate insulating layer Formed to surround the second semiconductor layer; and a first conductive layer that surrounds the second gate insulating layer and extends parallel to the substrate, the control circuit configured to cause the second in the erase operation Wiring and 144995.doc 201029011 The voltage of the first wiring is boosted, and at the same time, the voltage of the first wiring is maintained at a certain potential difference from the electric current of the first wiring, and the potential difference is A potential difference that causes a GIDL current. 2. The non-volatile semiconductor storage device of claim 1, wherein in the erasing operation, the control circuit boosts the first wiring to a first voltage and the second wiring to a second voltage, such that The potential difference is maintained between the first voltage and the second voltage, and then the first wiring is boosted from the first voltage, and the second wiring is set to a floating state. 3. The non-volatile semiconductor storage device of claim 1, wherein the control circuit comprises: a first voltage generating circuit configured to supply a first voltage to be boosted to the first wiring; a voltage generating circuit configured to supply a second voltage to the second wiring, the second voltage being generated by delaying the first voltage for a period of time and decreasing the first voltage by the potential difference; a second voltage generating circuit configured to compare a third voltage and a reference voltage to output a differential signal, the third voltage having a relationship with the first voltage, the first voltage generating circuit is based on The differential signal is switched between an operating state and a stopped state, and the "Hid-voltage generating circuit switches between an operating state and a stopped state based on the differential signal. 4. If the request item 3 is not Volatile semiconductor storage device, wherein 144995.doc • 1· 201029011 ^ control circuit includes _vibrating circuit 'the vibrating i circuit is configured to output based on the differential signal - the vibrating signal, and the first The waste generating circuit includes a boosting circuit configured to boost a certain voltage to the first voltage based on the oscillating signal. 5. The non-volatile semiconductor storage device of claim 3, wherein the The second voltage is a voltage generated by reducing the second voltage. 6. The non-volatile semiconductor storage device of claim 1, wherein the control circuit causes the first one before applying a ground voltage to the first conductive layer The wiring and the second wiring are boosted. 7. The non-volatile semiconductor storage device of claim 1, wherein the first control circuit is configured to boost the voltage of the second wiring and the voltage of the first wiring The conductive layer is set in a floating state. The non-volatile semiconductor storage device of claim 1, comprising a second selection transistor having an end connected to the other end of the memory string; a wiring having an end connected to the other end of the second selection transistor; and a fourth wiring connected to one of the gates of the second selection transistor, wherein the second selection transistor comprises: a third semiconductor layer 'extending in a direction perpendicular to the substrate; a second gate insulating layer 'which is formed to surround the third semiconductor 144995.doc 201029011 layer; and a first conductive layer surrounding the first a second closed insulating layer extending parallel to the substrate, the first semiconductor layer including a bonding portion joining the lower ends of one of the columnar portions, the second semiconductor layer being formed and borrowed a top surface contact of one of the dedicated pillar portions joined by the joint portion, and 9. the third semiconductor layer is formed to be the other of the pillar portions joined by the joint portion The non-volatile semiconductor storage device of claim 8, wherein in the erasing operation, the control circuit boosts a voltage of the third wiring and the fourth wiring while maintaining the third wiring The electric power is greater than the voltage of the fourth wiring by a certain potential difference. 10. The non-volatile semiconductor storage device of claim 9, wherein the control circuit selectively connects the third wiring to the first wiring, and the third wiring is provided with the first wiring The potential of the same potential. 11. The non-volatile semiconductor storage device of claim 9, wherein in the erasing operation, the control circuit boosts the first wiring to a first voltage and the second wiring to a second voltage, such that Maintaining the potential difference between the first voltage and the second ", and then boosting the first wiring from the first voltage while setting the second wiring to a floating state". The non-volatile semiconductor storage device of claim 11, wherein 144995.doc -4- 201029011, in the erasing operation, the control circuit boosts the third wiring to a first voltage and boosts the fourth wiring to one a second (four), wherein the certain potential i is maintained between the third voltage of the first electric grinder, and then the third wiring is boosted from the first voltage, and the fourth wiring is set at A floating state. The non-volatile semiconductor storage device of claim 9, wherein the control circuit comprises: - a first electric dust generating circuit configured to supply a first electric diffuser to be boosted to the first wiring; a second voltage generating circuit configured to supply a second voltage to the second wiring. The second voltage is delayed by the first voltage by a certain period of time and the first voltage is decreased by the potential difference And generating a third voltage generating circuit configured to compare a third voltage with a reference voltage to output a differential signal, the third voltage having a relationship with the first voltage, (4) a The voltage generating circuit switches between the -operating state and a stopped state based on the differential signal, and the second electric house generating circuit switches between an operating state and a stopped state based on the differential signal. 14. The non-volatile semiconductor storage device of claim 9, wherein the control circuit causes the S&amp; line, the second wiring, the third wiring, and the fourth before applying a ground voltage to the first conductive layer. Wiring boost. 15. The non-volatile semiconductor storage device of claim 1, wherein an end of a second selection transistor is connected to the other end of the memory string; an end of a third wiring is connected to the end a second terminal of the second selection transistor; and a fourth wiring connected to one of the gates of the second selection transistor, wherein the second selection transistor comprises: a third semiconductor layer 'which is perpendicular to the Extending in a direction of the substrate; a second gate insulating layer formed to surround the third semiconductor layer; and a third conductive layer surrounding the second gate insulating layer and extending parallel to the substrate, the The second semiconductor layer is formed in contact with a bottom surface of one of the columnar portions, and the third semiconductor layer is formed in contact with a top surface of one of the columnar portions. 17. The non-volatile semiconductor storage device of claim 15, wherein in the erasing operation, the control circuit is configured to boost the voltage of the third wiring and the fourth se* line while maintaining The voltage of the third wiring is greater than the voltage of the fourth wiring by a certain potential difference. The non-volatile semiconductor storage device of claim 16, wherein the control circuit selectively connects the third wiring to the first wiring 'and sets the third wiring to have the same potential as a potential of the first wiring . 144995.doc • 6 - 201029011 18. The non-volatile semiconductor storage device of claim 16, wherein in the erasing operation, the control circuit raises the first wiring to a first voltage and the first The second wiring is raised to a voltage _ _ first voltage to maintain a two lanthanum potential difference between the first voltage and the second voltage, and the junction begins to make the first wiring from the first voltage well - λ Pressing, while the second wiring § is in a floating state. 19. The non-volatile semiconductor storage device of claim 18, wherein in the erasing operation, the control circuit boosts the third wiring to a "first" and raises the fourth wiring to a second voltage, The potential difference is maintained between the first voltage and the second money, and then the third wiring is started to be boosted from the first voltage, and the fourth wiring is set to a floating state. 20. The non-volatile semiconductor storage device of claim 15, wherein: the 6-Hai control circuit causes the second wiring, the second wiring, the third wiring, and the first to apply a ground voltage to the first layer of Yanhai The fourth wiring is raised and pressed. 144995.doc