US7892934B2 - SOI substrate and method for manufacturing SOI substrate - Google Patents

SOI substrate and method for manufacturing SOI substrate Download PDF

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US7892934B2
US7892934B2 US12/158,047 US15804706A US7892934B2 US 7892934 B2 US7892934 B2 US 7892934B2 US 15804706 A US15804706 A US 15804706A US 7892934 B2 US7892934 B2 US 7892934B2
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substrate
single crystal
transparent insulating
crystal silicon
insulating substrate
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US20100025804A1 (en
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Makoto Kawai
Yoshihiro Kubota
Atsuo Ito
Koichi Tanaka
Yuuji Tobisaka
Shoji Akiyama
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Shin Etsu Chemical Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation

Definitions

  • the present invention relates to an SOI substrate and a method for manufacturing an SOI substrate and, more particularly, to an SOI substrate in which a peeled surface of a single crystal silicon thin film bonded and formed on a transparent insulating substrate has suppressed surface roughness and a method for manufacturing the SOI substrate.
  • a so-called SOI (Silicon on Insulator) wafer in which a single crystal silicon (Si) layer is provided on an insulating film such as an oxide film, is used as a substrate for device formation for the purpose of forming a MOS transistor excellent in radiation-resistant characteristics and latch-up characteristics and excellent at suppressing the short channel effect.
  • SOI substrates a less-defective SOI substrate to which a bonding technique has been applied is attracting attention.
  • the use of such an SOI substrate as a substrate for optical device manufacture has come under review in recent years (e.g., Patent Documents 1 to 5).
  • an active matrix method is a driving method which is commonly used for the reason that high definition is achieved due to high response speed if the method is applied to a display device and for other reasons.
  • the general configuration of such an active-matrix-driven electro-optic device is such that a liquid crystal layer is provided by sandwiching liquid crystal between two glass substrates of upper and lower glass substrates and that an upper electrode (counter electrode) common to the whole pattern is formed on the upper glass electrode while pixel electrodes and TFTs as switching elements for driving the respective pixel electrodes are provided on the lower glass substrate.
  • An X electrode as a gate input unit of the TFT provided for each pixel and a Y electrode as a source input unit are patterned on the lower glass substrate. The input of an electrical signal to each TFT is controlled through these electrodes. With this control, each TFT as the switching element is controlled.
  • Liquid crystal in an area between each pixel electrode and the counter electrode changes in orientation depending on the electric field generated between the upper and lower electrodes and functions as a liquid crystal shutter. That is, each pixel is driven by turning on/off the corresponding TFT as a switching element for a liquid crystal shutter.
  • Such a TFT has conventionally been provided in an amorphous Si (a-Si) or polycrystalline Si (poly-Si) film provided on a lower glass substrate. Since a TFT as a switching element is required to operate at high speed for high-speed control of pixel switching, the use of a single crystal Si TFT instead of an amorphous Si TFT or polycrystalline Si TFT has been considered, and the use of an SOI substrate having a single crystal silicon thin film on an insulating substrate has been considered. In other words, formation of TFTs in a single crystal Si layer provided on an insulator layer by means of bonding or the like allows much faster switching than the case of amorphous Si TFTs or polycrystalline Si TFTs.
  • Patent Document 1 Japanese Patent Laid-Open No. 11-145438
  • Patent Document 2 Japanese Patent Laid-Open No. 6-18926
  • Patent Document 3 Japanese Patent Laid-Open No. 11-163363
  • Patent Document 4 Japanese Patent Laid-Open No. 2003-282885
  • Patent Document 5 Japanese Patent Laid-Open No. 2002-110998
  • Patent Document 6 Japanese Patent No. 3048201
  • the SOI substrate When an SOI substrate is to be used as a substrate for an optical device as described above, the SOI substrate needs to have a single crystal silicon thin film on a transparent insulating substrate.
  • the single crystal silicon thin film is required to be a high-quality film with advantages such as high surface flatness, excellent in-plane film thickness uniformity, and few structural defects which may cause light scattering.
  • a relatively high temperature e.g., 500 to 1,200° C.
  • a relatively high temperature e.g., 500 to 1,200° C.
  • an SOI substrate is manufactured by bonding together a single crystal silicon substrate and a transparent insulating substrate (e.g., a quartz substrate)
  • a transparent insulating substrate e.g., a quartz substrate
  • heat treatment at a high temperature as described above causes trouble. More specifically, an undesirable phenomenon such as a fracture in a one with lower rigidity of the substrates (often the transparent insulating substrate) or local peeling at bonding surfaces may occur.
  • a microcrack in an area in the vicinity of the bonding surface of the single crystal silicon substrate may prevent smooth cleavage when thin-film single crystal silicon layer (SOI layer) is peeled to cause surface roughness.
  • the present invention has been made to meet the above-described demand, and has as its object to provide an SOI substrate comprising an SOI layer formed on a transparent insulating substrate by a bonding technique, wherein a peeled surface of the SOI layer has high flatness.
  • a method for manufacturing an SOI substrate comprises a first step of forming a hydrogen ion implantation layer at an average ion implantation depth L on one principal surface of a single crystal silicon substrate, a second step of subjecting at least one of one principal surface of a transparent insulating substrate and the one principal surface of the single crystal silicon substrate to surface treatment, a third step of bringing the one principal surface of the single crystal silicon substrate and the one principal surface of the transparent insulating substrate into close contact with each other, a fourth step of subjecting the single crystal silicon substrate and transparent insulating substrate to bonding by heating the single crystal silicon substrate and transparent insulating substrate at a temperature of 350° C.
  • a heat treatment temperature in the above-described fourth step is preferably 100 to 300° C.
  • a dose of hydrogen ions in the above-described first step is preferably 0.5 ⁇ 10 17 atoms/cm 2 or above, more preferably 1 ⁇ 10 17 atoms/cm 2 or above.
  • the dose of hydrogen ions in the above-described first step is preferably 3 ⁇ 10 17 atoms/cm 2 or below.
  • the above-described transparent insulating substrate is preferably one of a quartz substrate, a sapphire (alumina) substrate, a borosilicate glass substrate, and a crystallized glass substrate.
  • the above-described single crystal silicon substrate is preferably a substrate of nearly perfect crystal (NPC), single crystal silicon grown by a CZ method (Czochralski method) or a floating zone method (FZ method).
  • NPC nearly perfect crystal
  • CZ method Czochralski method
  • FZ method floating zone method
  • the surface treatment in the above-described second step preferably comprises at least one of plasma treatment and ozone treatment.
  • An RMS value for the roughness of a peeled surface of the above-described SOI layer is preferably 10 nm or below, more preferably 6 nm or below.
  • the temperature for bonding of a transparent insulating substrate and a single crystal Si substrate after formation of a hydrogen ion implantation layer is set to 350° C. or below. Accordingly, the amount of thermal distortion induced during a corresponding heat treatment process is suppressed, and an undesirable phenomenon due to the differences in physical property values between the single crystal Si substrate and the transparent insulating substrate, such as a substrate fracture or local peeling at bonding surfaces, can be avoided.
  • An SOI substrate thus obtained is excellent in surface flatness and in-plane film thickness uniformity and has few structural defects which cause light scattering. Therefore, it is possible to provide an SOI substrate especially suitable for manufacturing an optical device.
  • FIGS. 1(A)-1(H) show views for explaining an example of a manufacturing process for an SOI substrate according to the present invention
  • FIGS. 2(A) and 2(B) show views for illustrating a method for applying impact from the outside in a peeling process according to the present invention.
  • FIGS. 3(A)-3(C) show views for explaining a mechanical polishing process provided as needed.
  • the temperature for bonding of one principal surface of a transparent insulating substrate and a single crystal Si substrate having a hydrogen ion implantation layer formed in advance at an average ion implantation depth of one principal surface is set to 350° C. or below, preferably 100 to 300° C.
  • the transparent insulating substrate a quartz substrate, a sapphire (alumina) substrate, a borosilicate glass substrate, a crystallized glass substrate, or the like is selected. These substrates are relatively significantly different in thermal expansion coefficient and mechanical strength (a modulus of rigidity or the like) from the single crystal Si substrate, and a fracture or local peeling at bonding surfaces is likely to occur due to heat in a bonding process. Accordingly, the present invention suppresses the amount of induced thermal distortion by selecting a temperature of 350° C. or below as a bonding temperature and avoids the above-described undesirable phenomenon due to the differences in physical property values between the single crystal Si substrate and the transparent insulating substrate.
  • the heat treatment temperature of 350° C. or below is sufficiently low compared to a temperature required to change the state of bonds of a silicon atom, local damage in the hydrogen ion implantation layer induced by hydrogen ion implantation is maintained during a corresponding heat treatment process. For this reason, there occurs no microcrack or the like which may act as the origin of cleavage of a single crystal silicon thin film in a subsequent peeling process. As a result, the hydrogen ion-implanted state as a cleavage condition is maintained, and it is possible to obtain an SOI layer with suppressed surface roughness after peeling.
  • the upper limit for the dose of hydrogen ions to be implanted into the single crystal Si substrate is set to 3 ⁇ 10 17 atoms/cm 2 .
  • the upper limit is set to avoid a reduction in productivity but also because the dose at or above the value causes too much damage at the time of ion implantation, and consequently the number of cleavage origins formed in the single crystal silicon thin film becomes excessive to be prone to surface roughness in the SOI layer after peeling.
  • a value sufficient to cause damage required for cleavage to the single crystal silicon thin film is selected as the lower limit for the dose of hydrogen ions to be implanted and that the lower limit is preferably 0.5 ⁇ 10 17 atoms/cm 2 or above, more preferably 1 ⁇ 10 17 atoms/cm 2 or above.
  • a transparent insulating substrate to be bonded is a quartz substrate.
  • FIGS. 1(A)-1(H) show views for explaining an example of a manufacturing process for an SOI substrate according to the present invention.
  • a single crystal Si substrate 10 and a transparent insulating substrate 20 having the same diameter are prepared ( FIG. 1(A) ).
  • the single crystal Si substrate 10 is a commercially available Si substrate which is formed through growth by, e.g., the CZ method (Czochralski method).
  • the electrical characteristics such as conductivity type and resistivity, crystal orientation, and crystal diameter of the single crystal Si substrate 10 are appropriately selected depending on design values and processes for a device for which an SOI substrate according to the present invention is used or the display area of a device to be manufactured and the like.
  • a substrate of “nearly perfect crystal (NPC)”, single crystal silicon grown by the CZ method (Czochralski method) or the floating zone method (FZ method) may be used instead.
  • NPC nearly perfect crystal
  • CZ method Czochralski method
  • FZ method floating zone method
  • a uniform ion implantation layer 11 is formed at a prescribed depth (an average ion implantation depth L) in the vicinity of the surface of the single crystal Si substrate 10 ( FIG. 1(C) ).
  • a depth from the surface of the single crystal Si substrate 10 at which the ion implantation layer 11 is located (the average ion implantation depth L) is controlled by an acceleration voltage at the time of the ion implantation.
  • a microbubble layer is formed in an area equivalent to the average ion implantation depth L at the surface of the single crystal Si substrate 10 to be localized in the area.
  • the ion implantation depth L depends on how much thickness of the SOI layer is to be peeled.
  • the average ion implantation depth L for hydrogen ions is set to 0.5 ⁇ m or below, and ion implantation conditions are set as follows: dose, 0.5 ⁇ 10 17 to 3 ⁇ 10 17 atoms/cm 2 ; and acceleration voltage, 50 to 100 keV.
  • the temperature of the single crystal Si substrate 10 at the time of the ion implantation is kept at about 250 to 450° C.
  • an insulating film such as an oxide film may be formed in advance on an ion implantation surface of the single crystal Si substrate 10 , and ions may be implanted through the insulating film, as generally performed to suppress channeling of implanted ions in the process of implanting ions into Si crystals.
  • Bonding surfaces of the single crystal Si substrate 10 having the thus-formed ion implantation layer 11 and the transparent insulating substrate 20 are subjected to plasma treatment or ozone treatment aimed at surface cleaning, surface activation, and the like ( FIG. 1(D) ).
  • plasma treatment or ozone treatment aimed at surface cleaning, surface activation, and the like.
  • Such surface treatment is performed for the purpose of removing organic matter from a surface serving as a bonding surface, for the purpose of achieving surface activation by increasing OH groups on the surface, or for another purpose. It is not always necessary to subject both the bonding surfaces of the single crystal Si substrate 10 and transparent insulating substrate 20 to the treatment, and only one of the bonding surfaces may be subjected to the treatment.
  • a single crystal Si substrate and/or a transparent insulating substrate with clean surfaces which have been subjected in advance to RCA cleaning or the like are placed on a sample stage in a vacuum chamber, and plasma gas is introduced into the vacuum chamber such that a prescribed degree of vacuum is achieved.
  • the plasma gas used here as a gas for the surface treatment of the single crystal Si substrate include oxygen gas, hydrogen gas, argon gas, a mixture of these, and a mixture of hydrogen gas and helium gas.
  • the gas used can be appropriately changed depending on the surface state of the single crystal Si substrate, the purpose, and the like.
  • the surface treatment is also intended to oxidize the single crystal Si surface
  • gas containing at least oxygen gas is used as the plasma gas.
  • a substrate whose surfaces are oxidized such as a quartz substrate is used as the transparent insulating substrate, there is no specific limit on the type of the plasma gas to be selected.
  • radio-frequency plasma with a power of about 100 W is generated.
  • the surface(s) of the single crystal Si substrate and/or insulating substrate to be plasma-treated is (are) subjected to treatment for about 5 to 10 seconds, and the surface treatment ends.
  • a single crystal Si substrate and/or a transparent insulating substrate with clean surfaces which have been subjected in advance to RCA cleaning or the like are placed on a sample stage in a chamber in an atmosphere containing oxygen.
  • plasma gas such as nitrogen gas or argon gas is introduced into the chamber, radio-frequency plasma with a prescribed power is generated. Oxygen in the atmosphere is converted to ozone by the plasma, and the surface(s) of the single crystal Si substrate and/or transparent insulating substrate to be treated are subjected to the treatment for a prescribed period.
  • the surfaces as the bonding surfaces of the single crystal Si substrate 10 and transparent insulating substrate 20 having undergone the above-described surface treatment are brought into close contact with each other ( FIG. 1(E) ). Bonding is performed by heating the single crystal Si substrate 10 and transparent insulating substrate 20 at a temperature of 350° C. or below in this state ( FIG. 1(F) ).
  • the temperature of 350° C. or below is selected in consideration of the difference in thermal expansion coefficient between single crystal Si and quartz, the amount of distortion due to the difference in thermal expansion coefficient, the amount of distortion, and the thicknesses of the single crystal Si substrate 10 and transparent insulating substrate 20 . Assume that the thickness of the single crystal Si substrate 10 and that of the transparent insulating substrate 20 are approximately the same.
  • the thermal expansion coefficient (2.33 ⁇ 10 ⁇ 6 ) of single crystal Si and that (0.6 ⁇ 10 ⁇ 6 ) of quartz are significantly different, if the single crystal Si substrate 10 and transparent insulating substrate 20 are subjected to heat treatment at a temperature above 350° C., the difference in rigidity between both the substrates may cause a crack due to thermal distortion or peeling at the bonding surfaces or may cause a fracture in the single crystal Si substrate or quartz substrate in an extreme case. For this reason, 350° C. is selected as the upper limit for the heat treatment temperature, and the heat treatment is preferably performed in the temperature range of 100 to 300° C.
  • the surface (bonding surface) of at least one of the single crystal Si substrate 10 and the transparent insulating substrate 20 is subjected to surface treatment by the above-described plasma treatment or ozone treatment, or the like and is activated. It is thus possible to achieve bonding strength enough to endure mechanical peeling and mechanical polishing in subsequent processes without high-temperature heat treatment required for a conventional bonding SOI manufacturing process. Accordingly, occurrence of thermal distortion, cracks, peeling at the bonding surfaces, and the like caused by the differences in thermal expansion coefficient and mechanical strength properties between the single crystal Si substrate 10 and the transparent insulating substrate 20 are suppressed at the time of heat treatment at a high temperature.
  • an Si—Si bond in the ion implantation layer 11 is broken by applying impact from the outside, and a single crystal silicon thin film is mechanically peeled along a crystal surface at a position equivalent to the prescribed depth (average ion implantation depth L) in the vicinity of the surface of the single crystal Si substrate 10 .
  • an SOI layer 12 is peeled from a bulk portion 13 of the single crystal Si substrate 10 while being bonded on the one principal surface of the transparent insulating substrate 20 (FIG. 1 (G)), and an SOI substrate including the SOI layer 12 on the principal surface of the transparent insulating substrate 20 is obtained ( FIG. 1(H) ).
  • the mechanical peeling may also be performed at room temperature in the air.
  • the mechanical peeling may be performed while the sample is kept at a temperature free from the risk of significant thermal distortion, cracks, peeling at the bonding surfaces, and the like.
  • FIGS. 2(A) and 2(B) show views for illustrating a method for applying impact from the outside in the above-described peeling process.
  • various methods for applying impact For example, a method for applying impact by causing fluid such as gas or liquid to issue in a jet from a tip portion 31 of a nozzle 30 and spraying the fluid on a side surface of the single crystal Si substrate 10 (FIG. 2 (A)), a method for applying impact by pressing a tip portion 41 of a blade 40 against an area in the vicinity of the ion implantation layer 11 (FIG. 2 (B)), or the like can be employed.
  • the surface roughness of any SOI layer after peeling according to this example obtained in the above-described manner was 10 nm or below in RMS value. It was possible to obtain an SOI layer with an RMS value of 6 nm or below by optimizing the heat treatment temperature condition in the above-described bonding process and the hydrogen ion implantation conditions. Note that an RMS value is an average value obtained by measuring a 10 ⁇ m ⁇ 10 ⁇ m area on the surface of an SOI layer after peeling with an atomic force microscope (AFM).
  • AFM atomic force microscope
  • the present invention does not require high-temperature processing as in a conventional method in either of the process of bonding the single crystal Si substrate 10 and transparent insulating substrate 20 and the process of peeling the SOI layer, and processing can be consistently performed at a low temperature (350° C. or below).
  • a low temperature 350° C. or below.
  • Many of SOI substrate manufacturing methods known in the art include a high-temperature processing process and require a special contrivance to avoid cracks due to thermal distortion or peeling.
  • a reduction in process temperature according to the present invention is extremely advantageous in terms of stabilization and simplification of an SOI substrate manufacturing process.
  • Patent Document 1 Japanese Patent Laid-Open No. 11-145438 discloses a method in which a single crystal Si wafer and an insulating substrate are heated at 100 to 300° C. and are temporarily bonded together, the single crystal Si layer is thinned by etching, the single crystal Si wafer and insulating substrate are subjected to heat treatment at 350 to 450° C. and are finally bonded together, the single crystal Si layer is further thinned by polishing, the single crystal Si wafer and insulating substrate are heated at 500° C.
  • a temperature reduction can be achieved in either of the bonding process and peeling process.
  • the low-temperature process thus has the major advantage of being able to simultaneously realize simplification and stabilization of an SOI wafer manufacturing process.
  • a heat treatment process may be further added after the peeling process in FIG. 1(G) , as needed, to further improve the strength of bond between the SOI layer 12 and the transparent insulating substrate 20 .
  • the thickness of the SOI layer 12 immediately after the peeling process in FIG. 1(G) is generally 0.5 ⁇ m or below, even if the transparent insulating substrate 20 having the Si layer with this thickness at its surface is heat-treated at a relatively high temperature, a problem such as a fracture in the transparent insulating substrate 20 or peeling of the SOI layer 12 does not occur.
  • the heat treatment temperature in this process can be set to a relatively high temperature, and the heat treatment can be performed in the temperature range of, e.g., about 1,000 to 1,250° C.
  • FIG. 1 Basic processes of a method for manufacturing an SOI substrate according to the present invention are as illustrated in FIG. 1 .
  • the surface of the obtained SOI layer 12 may be subjected to mechanical polishing such as touch polishing.
  • FIGS. 3(A)-3(C) show views for explaining a mechanical polishing process provided as needed.
  • the film thickness of the SOI layer 12 immediately after the peeling process is about 0.3 ⁇ m.
  • the SOI layer is thinned to approximately 0.1 ⁇ m by mirror-polishing the surface of the SOI layer by the same procedure as that for mirror polishing in a normal Si substrate manufacturing process. With this mirror finishing, surface roughness such as haze generated on the surface of the SOI layer 12 in the peeling process is removed.
  • FIG. 3(B) shows the state of the SOI layer 12 after the above-described mirror polishing process.
  • the thickness has been reduced to approximately 0.1 ⁇ m, and the surface roughness induced in the previous process has been removed, by the mirror polishing.
  • remaining damage or crystal defects induced by the implantation of hydrogen ions and slight damage induced by the mirror polishing are in the Si crystal lattice of the SOI layer 12 .
  • a microscopic lattice defect due to such damage itself may act as a carrier recombination center to affect the behavior of carriers.
  • the microscopic lattice defect may also develop into a macroscopic defect such as a dislocation after heat treatment in a subsequent device manufacturing process and become a remote cause of degradation in the electrical characteristics of a device. For this reason, it is necessary to perform a process for removing the above-described damage in the SOI layer 12 . Note that such damage can be removed by heat treatment using, e.g., a heat treatment furnace or lamp heater.
  • FIG. 3(C) illustrates a case where the above-described damage removal has been performed across the SOI layer 12 .
  • the damage in the SOI layer 12 has been wholly removed by heat treatment. Note that the removal of the damage from the SOI layer can be simply and quickly monitored by carrier lifetime measurement or the like.
  • Such damage removal removes lattice distortion, a lattice defect, or the like which acts as a carrier recombination center (trapping center) in Si crystals and restores the electrical characteristics (carrier mobility, lifetime, and the like) of the SOI layer 12 to original values.
  • an SOI layer may be formed using a single crystal Si substrate having an oxide film formed in advance on a surface.
  • a single crystal Si substrate used in this example is one having a thermal oxide film with a thickness of 100 nm formed on the side of a bonding surface and having a diameter of 200 nm (8 inches). Note that the surface roughness of the thermal oxide film was expressed as an Ra value for a 10 ⁇ m ⁇ 10 ⁇ m measurement area obtained by an atomic force microscope and was 0.2 nm.
  • a quartz substrate with a diameter of 200 mm (8 inches) is used as a transparent insulating substrate to be bonded to the single crystal Si substrate.
  • a bonding surface of the transparent insulating substrate is subjected to polishing, and the surface roughness thereof is 0.19 nm in Ra value. Note that a surface roughness measurement condition is the same as that for the above-described thermal oxide film.
  • Hydrogen ions were implanted from the side of the thermal oxide film into the single crystal Si substrate at an acceleration voltage of 35 KeV with a dose of 2.5 ⁇ 10 17 atoms/cm 2 .
  • the average hydrogen ion implantation depth from the interface between the thermal oxide film and the single crystal Si substrate at this time is 0.3 ⁇ m.
  • both the substrates were set in a chamber for plasma treatment, and plasma gas (air) was introduced into the chamber.
  • the pressure in the chamber was then set to 2 torr. Under this reduced pressure, a 13.56 MHz radio frequency was applied across parallel plate electrodes having a diameter of 300 mm with a radio-frequency power of about 100 W.
  • the bonding surfaces of the single crystal Si substrate and quartz substrate were subjected to radio-frequency plasma treatment for 5 to 10 seconds.
  • the single crystal Si substrate and quartz substrate were put together and were brought into close contact with each other. Bonding was started by firmly pressing these substrates against each other with fingers. Since the bonding surfaces of both the substrates having undergone the plasma treatment were activated, high bonding strength would have been achieved even by such an extremely simple method. However, to further increase the bonding strength, the substrates were subjected to heat treatment at 250° C. for 30 hours while the substrates were bonded together. Visual observation of the bonding surfaces after the heat treatment confirmed uniform bonding of the substrates across the bonding surfaces. Note that although external force was applied with fingers to cause a shift between the substrates parallel to the bonding surfaces, the two substrates were not shifted relative to each other, and the state of bonding between the substrates remained unchanged.
  • Blades of paper cutting scissors were used for peeling to form an SOI layer.
  • the blades of the paper cutting scissors as a wedge were driven in the outer peripheral surface of the bonded substrates (the side surface of the substrates) at eight positions (at approximately 45° intervals), uniform peeling occurred across the bonded substrates, and an SOI layer which was a single crystal Si thin film was transferred and formed on the quartz substrate.
  • the surface roughness of the SOI layer after the peeling was expressed as a Ra value for a 10 ⁇ m ⁇ 10 ⁇ m measurement area obtained by an atomic force microscope and was 5.8 nm.
  • a bonding SOI substrate having a single crystal silicon thin film on a transparent insulating substrate wherein a peeled surface of an SOI layer formed on the transparent insulating substrate has high flatness.
  • the SOI substrate is excellent in surface flatness and in-plane film thickness uniformity and has few structural defects which cause light scattering. Therefore, the SOI substrate is an SOI substrate especially suitable for manufacturing an optical device.

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Application Number Priority Date Filing Date Title
JP2005366142 2005-12-20
JP2005366142A JP2007173354A (ja) 2005-12-20 2005-12-20 Ｓｏｉ基板およびｓｏｉ基板の製造方法
JP2005-366142 2005-12-20
PCT/JP2006/321885 WO2007072632A1 (ja) 2005-12-20 2006-11-01 Ｓｏｉ基板およびｓｏｉ基板の製造方法

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100187649A1 (en) * 2007-07-26 2010-07-29 Allibert Frederic Charge reservoir structure
US20100291753A1 (en) * 2007-06-22 2010-11-18 Semiconductor Energy Laboratory Co., Ltd. Semiconductor substrate, method for manufacturing semiconductor substrate, semiconductor device, and electronic device

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007074551A1 (ja) * 2005-12-27 2007-07-05 Shin-Etsu Chemical Co., Ltd. Ｓｏｉウェーハの製造方法及びｓｏｉウェーハ
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Citations (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0618926A (ja) 1992-07-02 1994-01-28 Sharp Corp 液晶表示用大型基板およびその製造方法
JPH11145438A (ja) 1997-11-13 1999-05-28 Shin Etsu Handotai Co Ltd Ｓｏｉウエーハの製造方法ならびにこの方法で製造されるｓｏｉウエーハ
JPH11163363A (ja) 1997-11-22 1999-06-18 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
EP0961312A2 (en) 1998-05-15 1999-12-01 Canon Kabushiki Kaisha SOI Substrate formed by bonding
JP3048201B2 (ja) 1991-09-18 2000-06-05 コミサリヤ・ア・レネルジ・アトミク 半導体材料薄膜の製造方法
JP2002110998A (ja) 2000-09-29 2002-04-12 Seiko Epson Corp 電気光学基板およびその製造方法、電気光学装置及び電子機器
US6388290B1 (en) * 1998-06-10 2002-05-14 Agere Systems Guardian Corp. Single crystal silicon on polycrystalline silicon integrated circuits
US6537370B1 (en) * 1998-09-10 2003-03-25 FRANCE TéLéCOM Process for obtaining a layer of single-crystal germanium on a substrate of single-crystal silicon, and products obtained
WO2003049189A1 (fr) 2001-12-04 2003-06-12 Shin-Etsu Handotai Co.,Ltd. Plaquette collee et procede permettant de produire cette plaquette collee
JP2003282885A (ja) 2002-03-26 2003-10-03 Sharp Corp 半導体装置およびその製造方法
JP2003347526A (ja) 2002-05-02 2003-12-05 Soi Tec Silicon On Insulator Technologies 材料の二層を剥離する方法
JP2004503111A (ja) 2000-07-12 2004-01-29 コミツサリア　タ　レネルジー　アトミーク 材料ブロックを切り取るための方法ならびに薄膜の形成方法
JP2004063730A (ja) 2002-07-29 2004-02-26 Shin Etsu Handotai Co Ltd Ｓｏｉウェーハの製造方法
US6720237B2 (en) * 2001-03-16 2004-04-13 Canon Kabushiki Kaisha Method for manufacturing a semiconductor film
US20040229444A1 (en) 2003-02-18 2004-11-18 Couillard James G. Glass-based SOI structures
US20040232488A1 (en) 2003-05-21 2004-11-25 Micron Technology, Inc. Silicon oxycarbide substrates for bonded silicon on insulator
US20040241958A1 (en) 2003-06-02 2004-12-02 International Business Machines Corporation Method of fabricating silicon devices on sapphire with wafer bonding at low temperature
WO2005027214A1 (ja) 2003-09-10 2005-03-24 Shin-Etsu Handotai Co., Ltd. 積層基板の洗浄方法及び基板の貼り合わせ方法並びに貼り合せウェーハの製造方法
US7112514B2 (en) * 2000-11-30 2006-09-26 Seiko Epson Corporation SOI substrate, element substrate, semiconductor device, electro-optical apparatus, electronic equipment, method of manufacturing the SOI substrate, method of manufacturing the element substrate, and method of manufacturing the electro-optical apparatus

Patent Citations (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3048201B2 (ja) 1991-09-18 2000-06-05 コミサリヤ・ア・レネルジ・アトミク 半導体材料薄膜の製造方法
JPH0618926A (ja) 1992-07-02 1994-01-28 Sharp Corp 液晶表示用大型基板およびその製造方法
JPH11145438A (ja) 1997-11-13 1999-05-28 Shin Etsu Handotai Co Ltd Ｓｏｉウエーハの製造方法ならびにこの方法で製造されるｓｏｉウエーハ
JPH11163363A (ja) 1997-11-22 1999-06-18 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
EP0961312A2 (en) 1998-05-15 1999-12-01 Canon Kabushiki Kaisha SOI Substrate formed by bonding
US6388290B1 (en) * 1998-06-10 2002-05-14 Agere Systems Guardian Corp. Single crystal silicon on polycrystalline silicon integrated circuits
US6537370B1 (en) * 1998-09-10 2003-03-25 FRANCE TéLéCOM Process for obtaining a layer of single-crystal germanium on a substrate of single-crystal silicon, and products obtained
JP2004503111A (ja) 2000-07-12 2004-01-29 コミツサリア　タ　レネルジー　アトミーク 材料ブロックを切り取るための方法ならびに薄膜の形成方法
JP2002110998A (ja) 2000-09-29 2002-04-12 Seiko Epson Corp 電気光学基板およびその製造方法、電気光学装置及び電子機器
US7112514B2 (en) * 2000-11-30 2006-09-26 Seiko Epson Corporation SOI substrate, element substrate, semiconductor device, electro-optical apparatus, electronic equipment, method of manufacturing the SOI substrate, method of manufacturing the element substrate, and method of manufacturing the electro-optical apparatus
US6720237B2 (en) * 2001-03-16 2004-04-13 Canon Kabushiki Kaisha Method for manufacturing a semiconductor film
WO2003049189A1 (fr) 2001-12-04 2003-06-12 Shin-Etsu Handotai Co.,Ltd. Plaquette collee et procede permettant de produire cette plaquette collee
JP2003282885A (ja) 2002-03-26 2003-10-03 Sharp Corp 半導体装置およびその製造方法
JP2003347526A (ja) 2002-05-02 2003-12-05 Soi Tec Silicon On Insulator Technologies 材料の二層を剥離する方法
JP2004063730A (ja) 2002-07-29 2004-02-26 Shin Etsu Handotai Co Ltd Ｓｏｉウェーハの製造方法
US20040229444A1 (en) 2003-02-18 2004-11-18 Couillard James G. Glass-based SOI structures
WO2005029576A2 (en) 2003-02-18 2005-03-31 Corning Incorporated Glass-based soi structures
US20040232488A1 (en) 2003-05-21 2004-11-25 Micron Technology, Inc. Silicon oxycarbide substrates for bonded silicon on insulator
US20040241958A1 (en) 2003-06-02 2004-12-02 International Business Machines Corporation Method of fabricating silicon devices on sapphire with wafer bonding at low temperature
WO2005027214A1 (ja) 2003-09-10 2005-03-24 Shin-Etsu Handotai Co., Ltd. 積層基板の洗浄方法及び基板の貼り合わせ方法並びに貼り合せウェーハの製造方法

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
U.S. Appl. No. 12/161,694, filed Jul. 22, 2008, Akiyama, et al.
U.S. Appl. No. 12/161,819, filed Jul. 23, 2008, Akiyama, et al.
U.S. Appl. No. 12/161,821, filed Jul. 23, 2008, Akiyama, et al.
U.S. Appl. No. 12/162,134, filed Jul. 25, 2008, Akiyama, et al.

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100291753A1 (en) * 2007-06-22 2010-11-18 Semiconductor Energy Laboratory Co., Ltd. Semiconductor substrate, method for manufacturing semiconductor substrate, semiconductor device, and electronic device
US8273611B2 (en) 2007-06-22 2012-09-25 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor substrate
US20100187649A1 (en) * 2007-07-26 2010-07-29 Allibert Frederic Charge reservoir structure
US8802539B2 (en) 2007-07-26 2014-08-12 Soitec Charge reservoir structure

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