US7195937B2 - Method for measuring withstand voltage of semiconductor epitaxial wafer and semiconductor epitaxial wafer - Google Patents

Method for measuring withstand voltage of semiconductor epitaxial wafer and semiconductor epitaxial wafer Download PDF

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US7195937B2
US7195937B2 US10/484,001 US48400104A US7195937B2 US 7195937 B2 US7195937 B2 US 7195937B2 US 48400104 A US48400104 A US 48400104A US 7195937 B2 US7195937 B2 US 7195937B2
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contact
epitaxial wafer
semiconductor epitaxial
breakdown
voltage
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Expired - Fee Related, expires
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US20050118736A1 (en
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Katsushi Akita
Masashi Yamashita
Makoto Kiyama
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Sumitomo Electric Industries Ltd
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Sumitomo Electric Industries Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line

Definitions

  • the present invention relates to semiconductor epitaxial wafers, and to methods of measuring the breakdown voltage of semiconductor epitaxial wafers.
  • gate-to-drain breakdown voltage is for example a voltage value defined as, “voltage at which a current of 1 mA per 1 mm gate width flows between gate-drain when a reverse voltage is applied across the two terminals.”
  • An object of the present invention brought about in order to resolve the foregoing issues, is thus to realize a measurement-facilitating method of measuring the breakdown voltage of a semiconductor epitaxial wafer, and to realize a semiconductor epitaxial wafer whose breakdown voltage is superior.
  • a method, involving the present invention, of measuring the breakdown voltage of a semiconductor epitaxial wafer is characterized in that a voltage is applied to a least one pair among a plurality of Schottky contacts formed onto a semiconductor epitaxial wafer and the breakdown voltage across the contacts is measured.
  • inter-contact breakdown voltage is measured with Schottky contacts only, ohmic contacts being unnecessary.
  • the fact that the manufacturing step of forming ohmic contacts is consequently omitted enables providing for facilitated testing measurement of the breakdown voltage of semiconductor epitaxial wafers.
  • inter-contact breakdown voltage is measured prior to fabricating working devices from wafer, a wafer that does not meet product specification can be excluded before being passed onto working-device fabrication steps. This consequently enables counting on reduction in time and expense losses compared with conventional measuring methods by which inter-contact breakdown voltage is measured after working devices are fabricated.
  • the surface of the semiconductor epitaxial wafer when the Schottky contacts are to be formed is preferably flat. In forming the Schottky contacts, because a step in which the wafer surface is etched is in this case unnecessary, the time required to produce the contacts can be curtailed.
  • the Schottky contacts are preferably formed onto the same surface. Forming the Schottky contacts using a photolithographic process is in that case facilitated.
  • the material for the Schottky contacts preferably contains one selected from the group consisting of Au, Pt, Pd, W, Ti, Al and Ni. Thus selecting a material suited to Schottky contacts enables more accurate breakdown-voltage measurement to be carried out.
  • the semiconductor epitaxial wafer surface is preferably cleaned with a cleaning solution containing at least one of: hydrochloric acid, phosphoric acid, ammonia, sulfuric acid, and aqueous hydrogen peroxide.
  • a cleaning solution containing at least one of: hydrochloric acid, phosphoric acid, ammonia, sulfuric acid, and aqueous hydrogen peroxide.
  • the structure of the semiconductor epitaxial wafer is preferably one in which the contact layer has been removed from the epitaxial structure for high electron mobility transistors. Measurement substantially equivalent to measuring the breakdown voltage of high election mobility transistors as working devices can in that case be made.
  • the material for the semiconductor epitaxial wafer be a compound expressed by: Al x Ga y In 1-x-y N (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, x+y ⁇ 1); Al x Ga y In 1-x-y As (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, x+y ⁇ 1); or Al x Ga y In 1-x-y P (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, x+y ⁇ 1).
  • a first contact, a second contact and a third contact corresponding respectively to a working-device gate, source and drain are formed onto the semiconductor epitaxial wafer.
  • the first contact, second contact and third contact can in that case be assumed to be the gate, source and drain of a working device, whereby the breakdown voltage can be measured with for example the source-to-drain distance, the gate length, etc. put into desired conditions.
  • angled portions of the second contact and third contact where they oppose each other have a curved form. Inasmuch as arc discharge arising between the neighboring first contact and second contact can in that case be suppressed, more accurate breakdown-voltage measurement can be carried out.
  • the width of the first contact is 0.8 ⁇ m or more, 5 ⁇ m or less, and the distance between the first contact and the second contact, and the distance between the first contact and the third contact, is 0.8 ⁇ M or more, 20 ⁇ m or less.
  • the contacts are large-sized, Schottky contacts can easily be fabricated by direct-contact optical exposure.
  • a constant current is preferably applied between the first contact and the second contact before voltage is applied across them. Stabilization of the breakdown voltage characteristics between the first contact and the second contact by so-called electrical stress is in that case effected.
  • a semiconductor epitaxial wafer having to do with the present invention is utilized as a substrate for FETs in which the gate-to-drain distance is L 1 and for which a breakdown voltage V 1 between the gate and the drain is sought, wherein the semiconductor epitaxial wafer is characterized in that given that the distance between the first contact and the second contact is L 2 , the breakdown voltage V 2 between the first contact and the second contact, measured by the foregoing breakdown-voltage-measurement method satisfies the following relation. V 2 ⁇ V 1 ⁇ L 2 /L 1 (1)
  • FIG. 1 is a plan view depicting a wafer involving an embodiment of the present invention
  • FIG. 2 is diagrams representing steps in the course of fabricating the wafer depicted in FIG. 1 ;
  • FIG. 3 is a section view through line III—III in FIG. 1 ;
  • FIG. 4 is a graph illustrating the relationship between voltage and current in a circuit.
  • FIG. 5 is a graph illustrating the relationship between voltage and current in a circuit following oxide-film removal.
  • FIG. 1 is a plan view representing a semiconductor epitaxial wafer used for breakdown-voltage measurement.
  • three Schottky contacts 12 are formed onto the semiconductor epitaxial wafer (referred to simply as “wafer” hereinafter) 10 .
  • wafer 10 With its uppermost layer (cap layer) being an n-type GaN epitaxial layer the wafer 10 is fabricated by a suitably chosen semiconductor manufacturing process to have a working-device field-effect transistor (FET).
  • FET working-device field-effect transistor
  • the topside of the wafer 10 is approximately planar, and the Schottky contacts 12 are formed on this same surface. (The Schottky contacts 12 are formed onto the wafer 10 by a method that will be described later.)
  • the Schottky contacts 12 assume forms corresponding to the gate, source and drain of the FET that is the working device.
  • Schottky contact 14 first contact
  • Schottky contact 16 second contact
  • Schottky contact 18 third contact
  • Schottky contact 14 corresponding to the gate is configured with two separated square contact portions 14 a , and a rectilinear contact portion 14 b that interconnects the square contact portions 14 a , 14 a .
  • the width of the rectilinear contact portion 14 b (corresponding to the FET gate length; length in the side-to-side direction in the figure) is 1 ⁇ m; likewise the length of the rectilinear contact portion 14 b (corresponding to the FET gate width; length in the up-and-down direction in the figure) is 100 ⁇ m.
  • Schottky contact 16 and Schottky contact 18 corresponding respectively to the source and drain are in opposition flanking the rectilinear contact portion 14 b of Schottky contact 14 , and have an approximately rectangular form in which the long edges parallel the lengthwise direction of the Schottky contact 14 .
  • Schottky contact 16 and Schottky contact 18 are approximately symmetrical with respect to the rectilinear contact portion 14 b of Schottky contact 14 .
  • the three Schottky contacts 12 are, moreover, constituted from Au. It should be understood that other than Au, whichever of Pt, Pd, W, Ti, Al or Ni can be selected as a material for the Schottky contacts, which likewise may be an alloy that includes whichever of Pt, Pd, W, Ti, Al or Ni. Thus selecting a material suited to the Schottky contacts 12 provides for performing the later-described breakdown-voltage measurement the more accurately.
  • the Schottky contacts 12 are lent an appropriately multilayer structure, in which case the material for each layer is selected from the abovementioned materials. These Schottky contacts 12 are formed onto the wafer 10 by a lift-off process. A method of forming the Schottky contacts 12 onto the wafer 10 will be explained while reference is made to FIG. 2 .
  • a negative resist 20 which is a photosensitive resin, is coated onto the entire surface of the wafer 10 ; (see FIG. 2A ).
  • a quartz mask 22 that has been patterned (stippled areas in the figure) with chrome into the form of the Schottky contacts described above is then laid onto the coated resist 20 , and the wafer 10 and the quartz mask 22 are brought into contact; (see FIG. 2B ) and exposed to ultraviolet rays with a mercury lamp (not illustrated) from above the quartz mask 22 .
  • a mercury lamp not illustrated
  • the quartz mask 22 is removed and at the same time, the wafer 10 is developed, transferring onto it a pattern that is the reverse of the pattern on the quartz mask 22 ; (see FIG. 2C ).
  • an Au layer 24 is built by EB vapor deposition; (see FIG. 2D ).
  • Schottky contacts 12 of the desired shape are formed; (see FIG. 2E ).
  • Schottky contacts 12 are formed on the surface of the wafer 10 by putting it through a Schottky-contact 12 fabrication process (photolithography operations) such as in the foregoing. What is particularly significant here is that etching is not carried out on the wafer 10 surface in fabricating the Schottky contacts 12 . The fact that an etching process, which would require a great deal of time, is thus not necessary serves to shorten the Schottky-contact 12 fabrication time.
  • breakdown voltage in the present embodiment is, wherein a voltage at which a dc current flows from Schottky contact 18 to Schottky contact 14 has been applied, the voltage per 1 mm length of Schottky contact 14 at which a current of 1 mA flows between Schottky contact 14 and Schottky contact 18 .
  • breakdown voltage here signifies, in the working device (FET), “voltage per 1 mm gate width when a current of 1 mA flows between gate-drain.” Accordingly, if for example the length of Schottky contact 14 (gate width of the working device) is 100 ⁇ m, the voltage when a current of 10 ⁇ 4 A flows between Schottky contact 14 (corresponding to the working-device gate) and Schottky contact 18 (corresponding to the working-device drain) would be the “breakdown voltage.”
  • Schottky contact 18 is grounded, and meanwhile a dc circuit 26 for applying a negative voltage to Schottky contact 14 is formed. Then prior to measuring breakdown voltage, a constant current of 10 ⁇ A is applied for a 10-second interval. While it is known that flowing a current generally enhances breakdown voltage, in this way flowing a constant current in the circuit 26 to impart electrical stress from Schottky contact 18 to Schottky contact 14 stabilizes the breakdown voltage characteristics. The breakdown voltage is subsequently measured by flowing a dc current in the circuit 26 .
  • FIG. 4 then is a graph for a situation in which the voltage in the circuit 26 was increased gradually from 0 V.
  • the horizontal axis in the graph is the value of the applied voltage, while the vertical axis is the value of the current flowing between Schottky contact 14 and Schottky contact 18 .
  • the current rose steeply until a voltage of about 2 V
  • the current thereafter ought to have saturated inasmuch as it was in the Schottky reverse direction, a definite saturation value could not be confirmed. This was an impairment to measuring the breakdown voltage with satisfactory accuracy.
  • the breakdown voltage V 2 between Schottky contact 14 and Schottky contact 18 should satisfy relation (2) below.
  • the FET breakdown voltage readily turns out to be the sought breakdown voltage V 1 or more.
  • the breakdown-voltage measurement can be conducted with ease, because the breakdown voltage V 1 for a working device can be tested for even in cases in which large-sized contacts 12 are formed by the more convenient direct-contact optical exposure technique.
  • the width of the first contact should be 0.8 ⁇ m or more, 5 ⁇ m or less; and the distance between the first contact and the second contact, and the distance between the first contact and the third contact should be 0.8 ⁇ m or more, 20 ⁇ m or less.
  • the cleaning solution for clearing the oxide film from the wafer surface is not limited to hydrochloric acid, but as long as it removes oxide film, may be phosphoric acid, ammonia, sulfuric acid, aqueous hydrogen peroxide, or may be a solution containing a plurality of these liquids in a mixture.
  • the wafer material is not limited to GaN, but may be expressed by whichever of: Al x Ga y In 1-x-y N (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, x+y ⁇ 1); Al x Ga y In 1-x-y As (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, x+y ⁇ 1); or Al x Ga y In 1-x-y P (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, x+y ⁇ 1) such as, for example, InP or AlGaN.
  • Schottky contact 16 and Schottky contact 18 may have approximately the same positional relationship to Schottky contact 14 , and either the one or the other Schottky contact 16 or Schottky contact 18 may be formed onto the wafer 10 , because it will lead to the same results for the breakdown-voltage measurement.
  • the applied voltage moreover, may be an ac voltage.
  • the wafer 10 may be a structure in which the contact layer (an n-type GaAs layer for example) is left out from the epitaxial wafer structure for a GaAs-type high-electron mobility transistor.
  • the contact layer an n-type GaAs layer for example
  • a measurement that is substantially the same as the breakdown voltage measurement for the high-electron mobility transistor can be made.
  • a measurement-facilitating method of measuring the breakdown voltage of a semiconductor epitaxial wafer, and a semiconductor epitaxial wafer whose breakdown voltage is superior are realized.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Automation & Control Theory (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
US10/484,001 2002-04-30 2003-01-23 Method for measuring withstand voltage of semiconductor epitaxial wafer and semiconductor epitaxial wafer Expired - Fee Related US7195937B2 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2002-128681 2002-04-30
JP2002128681A JP4126953B2 (ja) 2002-04-30 2002-04-30 半導体エピタキシャルウエハの耐圧測定方法
PCT/JP2003/000612 WO2003094223A1 (fr) 2002-04-30 2003-01-23 Procede de mesure de la tension de resistance d'une plaquette a semiconducteurs epitaxiale et plaquette a semiconducteurs epitaxiale

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US7195937B2 true US7195937B2 (en) 2007-03-27

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EP (1) EP1503408A4 (zh)
JP (1) JP4126953B2 (zh)
KR (1) KR100955368B1 (zh)
CN (1) CN1295772C (zh)
TW (1) TW200400582A (zh)
WO (1) WO2003094223A1 (zh)

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JPH0720339U (ja) * 1993-05-12 1995-04-11 日本鋪道株式会社 発生土処理装置
CN101388353B (zh) * 2007-09-10 2010-05-19 中芯国际集成电路制造(上海)有限公司 监测晶圆击穿电压稳定性的方法
JP2010272577A (ja) 2009-05-19 2010-12-02 Takehisa Sasaki 放射線検出素子、及び、放射線検出装置
CN103364694B (zh) * 2012-03-26 2016-06-01 上海华虹宏力半导体制造有限公司 对超测量源表范围的漏源击穿电压进行测量的装置及方法
CN103389443B (zh) * 2012-05-07 2015-12-09 无锡华润上华科技有限公司 绝缘体上硅mos器件动态击穿电压的测试方法
JP5913272B2 (ja) * 2013-12-11 2016-04-27 誉田 雄久 放射線検出素子、及び、放射線検出装置

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JPS6237969A (ja) 1985-08-13 1987-02-18 Oki Electric Ind Co Ltd 半導体装置の製造方法
JPH06232177A (ja) 1993-02-05 1994-08-19 Sumitomo Electric Ind Ltd 電界効果トランジスタおよびその製造方法
US5674778A (en) * 1994-11-08 1997-10-07 Samsung Electronics Co., Ltd. Method of manufacturing an optoelectronic circuit including heterojunction bipolar transistor, laser and photodetector
US6025613A (en) * 1997-02-12 2000-02-15 Nec Corporation Semiconductor device capable of reducing leak current and having excellent pinch-off characteristic and method of manufacturing the same
US6177322B1 (en) * 1998-10-23 2001-01-23 Advanced Mictro Devices, Inc. High voltage transistor with high gated diode breakdown voltage
US20010042872A1 (en) * 1998-02-12 2001-11-22 Kazuaki Kunihiro Field-effect transistor and method for manufacturing the field effect transistor

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JPS54131880A (en) * 1978-04-03 1979-10-13 Nec Corp Manufacture of schottky junction element
JPH03166745A (ja) * 1989-11-27 1991-07-18 Nippon Mining Co Ltd 電界効果トランジスタの評価方法
JP3206621B2 (ja) * 1993-07-28 2001-09-10 住友電気工業株式会社 電界効果トランジスタ

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Publication number Priority date Publication date Assignee Title
JPS6237969A (ja) 1985-08-13 1987-02-18 Oki Electric Ind Co Ltd 半導体装置の製造方法
JPH06232177A (ja) 1993-02-05 1994-08-19 Sumitomo Electric Ind Ltd 電界効果トランジスタおよびその製造方法
US5674778A (en) * 1994-11-08 1997-10-07 Samsung Electronics Co., Ltd. Method of manufacturing an optoelectronic circuit including heterojunction bipolar transistor, laser and photodetector
US6025613A (en) * 1997-02-12 2000-02-15 Nec Corporation Semiconductor device capable of reducing leak current and having excellent pinch-off characteristic and method of manufacturing the same
US20010042872A1 (en) * 1998-02-12 2001-11-22 Kazuaki Kunihiro Field-effect transistor and method for manufacturing the field effect transistor
US6177322B1 (en) * 1998-10-23 2001-01-23 Advanced Mictro Devices, Inc. High voltage transistor with high gated diode breakdown voltage

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Title
Ismail et al. An MOS transistor with Schottky source/drain contacts and a self-aligned low-resistance T-gate, Microelectronic Engineering, vol. 35, (1997), p. 361-363. *

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Publication number Publication date
JP4126953B2 (ja) 2008-07-30
EP1503408A4 (en) 2009-08-12
US20050118736A1 (en) 2005-06-02
TWI316277B (zh) 2009-10-21
WO2003094223A1 (fr) 2003-11-13
CN1295772C (zh) 2007-01-17
JP2003324137A (ja) 2003-11-14
KR20040101987A (ko) 2004-12-03
KR100955368B1 (ko) 2010-04-29
CN1547767A (zh) 2004-11-17
EP1503408A1 (en) 2005-02-02
TW200400582A (en) 2004-01-01

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