JP3884047B2 - 電界効果トランジスタの製造方法 - Google Patents
電界効果トランジスタの製造方法 Download PDFInfo
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- JP3884047B2 JP3884047B2 JP2005210312A JP2005210312A JP3884047B2 JP 3884047 B2 JP3884047 B2 JP 3884047B2 JP 2005210312 A JP2005210312 A JP 2005210312A JP 2005210312 A JP2005210312 A JP 2005210312A JP 3884047 B2 JP3884047 B2 JP 3884047B2
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- 238000004519 manufacturing process Methods 0.000 title claims description 50
- 238000000034 method Methods 0.000 title claims description 48
- 230000005669 field effect Effects 0.000 title claims description 38
- 239000000758 substrate Substances 0.000 claims description 40
- 239000002184 metal Substances 0.000 claims description 33
- 229910052751 metal Inorganic materials 0.000 claims description 33
- 238000005530 etching Methods 0.000 claims description 24
- 229920002120 photoresistant polymer Polymers 0.000 claims description 21
- 229920001577 copolymer Polymers 0.000 claims description 16
- 238000001312 dry etching Methods 0.000 claims description 10
- 229920003229 poly(methyl methacrylate) Polymers 0.000 claims description 10
- 239000004926 polymethyl methacrylate Substances 0.000 claims description 10
- 238000001020 plasma etching Methods 0.000 claims description 8
- 238000011161 development Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 5
- 238000001039 wet etching Methods 0.000 claims description 4
- 238000009616 inductively coupled plasma Methods 0.000 claims description 3
- 238000012545 processing Methods 0.000 claims description 3
- 230000000694 effects Effects 0.000 claims description 2
- 230000005684 electric field Effects 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 description 28
- 150000001875 compounds Chemical class 0.000 description 7
- 238000001459 lithography Methods 0.000 description 6
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 4
- 238000004151 rapid thermal annealing Methods 0.000 description 4
- 238000000609 electron-beam lithography Methods 0.000 description 3
- 238000009413 insulation Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000586 desensitisation Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66848—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET
- H01L29/66856—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET with an active layer made of a group 13/15 material
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Description
110 活性層
120 キャップ層
130 ソースドレインオーミック金属層
140 絶縁膜
150 第1感光膜
160 第2感光膜
170 第3感光膜
180 第4感光膜
190a 基板上の第1開口領域
190b及び190c 第1及び第2ゲートリセス領域
195a 第1感光膜パターン上の開口領域
195b 基板上の第2開口領域
195c 第3ゲートリセス領域
200 ゲート金属
Claims (12)
- (a)基板上のソース−ドレイン領域にオーミック金属層を形成する段階と、
(b)この段階の結果物の全体上部に絶縁膜及び多層の感光膜を形成した後、前記オーミック金属層以外の一側領域に、最下層の感光膜が露出されるようにお互い異なる形態の感光膜パターンを形成すると同時に、前記オーミック金属層以外の他側領域に、前記絶縁膜が露出されるようにお互い異なる形態の感光膜パターンを形成する段階と、
(c)前記感光膜パターンをエッチングマスクとして用いて、露出された前記絶縁膜及び前記最下層の感光膜パターンを同時にエッチングして前記基板及び前記絶縁膜を露出させる段階と、
(d)露出された前記基板にリセス工程を行った後、露出された前記絶縁膜をエッチングして前記基板を露出させる段階と、
(e)前記基板上に、お互い異なるエッチング深さを有するゲートリセス領域を形成した後、所定のゲート金属を蒸着し、前記感光膜パターンを除去する段階とを含む、電界効果トランジスタの製造方法。 - 前記段階(a)で、前記基板と前記オーミック金属層との間に所定の厚さの活性層及びキャップ層を順次形成する段階をさらに含むことを特徴とする請求項1に記載の電界効果トランジスタの製造方法。
- 前記段階(a)で、前記オーミック金属層は、前記ソース−ドレイン領域を感光膜パターンで定義した後、所定のオーミック金属を蒸着し、急速熱処理(RTA)によって形成することを特徴とする請求項1に記載の電界効果トランジスタの製造方法。
- 前記段階(b)で、前記絶縁膜の厚さは、前記感光膜のエッチング率とゲートのブリッジの高さによって決定されることを特徴とする請求項1に記載の電界効果トランジスタの製造方法。
- 前記段階(b)で、前記多層の感光膜は、コポリマー/ポリメタクリル酸メチル/コポリマー/ポリメタクリル酸メチルまたはコポリマー/ZEP/PMGI/ZEPからなることを特徴とする請求項1に記載の電界効果トランジスタの製造方法。
- 前記段階(b)は、
(b−1)前記多層の感光膜を適正のドーズで露光及び現像し、お互い異なるゲート領域にT型ゲートのヘッド領域を定義する段階と、
(b−2)前記お互い異なるゲート領域に相異なるドーズで露光及び現像し、前記絶縁膜及び最下層の感光膜が露出されるようにゲートのブリッジ領域を定義する段階とからなることを特徴とする請求項1に記載の電界効果トランジスタの製造方法。 - 前記段階(b−2)で、前記T型ゲートのブリッジ領域を定義するとき、一つのゲート領域の感光膜パターンは相対的に高いドーズで露光して最下層の感光膜現像の際にパターンが定義されるようにして感光膜パターンで前記絶縁膜が露出されるようにし、他のゲート領域の感光膜パターンは相対的に低いドーズで露光して現像の際に最下層の感光膜パターンが定義されないようにすることを特徴とする請求項6に記載の電界効果トランジスタの製造方法。
- 前記段階(b)で、前記感光膜パターンは、お互い異なるドーズで露光され、最下層感光膜の形成如何に応じてお互い異なる感光膜パターンを形成することを特徴とする請求項1に記載の電界効果トランジスタの製造方法。
- 前記段階(c)で、前記絶縁膜は、一部をドライエッチング工程を用いてエッチングした後、残りをBOE溶液で等方性のウェットエッチング工程を用いてエッチングすることを特徴とする請求項1に記載の電界効果トランジスタの製造方法。
- 前記ドライエッチング工程は、反応性イオンエッチング(RIE)、磁力で増加した反応性イオンエッチング(MERIE)または誘導結合プラズマ(ICP)のいずれか一つの装備によって行われることを特徴とする請求項9に記載の電界効果トランジスタの製造方法。
- 前記ドライエッチング工程は、CF4ガス、CF4とCHF3の混合ガス、及びCF4とO2の混合ガスを用いて行われることを特徴とする請求項10に記載の電界効果トランジスタの製造方法。
- 前記段階(e)で、前記お互い異なるエッチング深さを有するゲートリセス領域はリセス工程によって形成され、前記感光膜パターンはリフトオフ工程によって除去されることを特徴とする請求項1に記載の電界効果トランジスタの製造方法。
Applications Claiming Priority (1)
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KR1020040100421A KR100606290B1 (ko) | 2004-12-02 | 2004-12-02 | 전계효과 트랜지스터의 제조방법 |
Publications (2)
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JP2006165507A JP2006165507A (ja) | 2006-06-22 |
JP3884047B2 true JP3884047B2 (ja) | 2007-02-21 |
Family
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JP2005210312A Expired - Fee Related JP3884047B2 (ja) | 2004-12-02 | 2005-07-20 | 電界効果トランジスタの製造方法 |
Country Status (3)
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---|---|
US (1) | US7183149B2 (ja) |
JP (1) | JP3884047B2 (ja) |
KR (1) | KR100606290B1 (ja) |
Families Citing this family (28)
Publication number | Priority date | Publication date | Assignee | Title |
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US7932539B2 (en) * | 2005-11-29 | 2011-04-26 | The Hong Kong University Of Science And Technology | Enhancement-mode III-N devices, circuits, and methods |
US7972915B2 (en) * | 2005-11-29 | 2011-07-05 | The Hong Kong University Of Science And Technology | Monolithic integration of enhancement- and depletion-mode AlGaN/GaN HFETs |
US8044432B2 (en) * | 2005-11-29 | 2011-10-25 | The Hong Kong University Of Science And Technology | Low density drain HEMTs |
JP5552230B2 (ja) * | 2006-11-20 | 2014-07-16 | パナソニック株式会社 | 半導体装置及びその駆動方法 |
GB2449514B (en) * | 2007-01-26 | 2011-04-20 | Filtronic Compound Semiconductors Ltd | A diode assembly |
CN100524634C (zh) * | 2007-03-28 | 2009-08-05 | 中国科学院微电子研究所 | 一种制备晶体管t型纳米栅的方法 |
US8502323B2 (en) * | 2007-08-03 | 2013-08-06 | The Hong Kong University Of Science And Technology | Reliable normally-off III-nitride active device structures, and related methods and systems |
EP2040299A1 (en) * | 2007-09-12 | 2009-03-25 | Forschungsverbund Berlin e.V. | Electrical devices having improved transfer characteristics and method for tailoring the transfer characteristics of such an electrical device |
US8076699B2 (en) * | 2008-04-02 | 2011-12-13 | The Hong Kong Univ. Of Science And Technology | Integrated HEMT and lateral field-effect rectifier combinations, methods, and systems |
US20100084687A1 (en) * | 2008-10-03 | 2010-04-08 | The Hong Kong University Of Science And Technology | Aluminum gallium nitride/gallium nitride high electron mobility transistors |
KR101064726B1 (ko) * | 2008-11-24 | 2011-09-14 | 한국전자통신연구원 | 반도체 장치 및 그 제조 방법 |
US20120098599A1 (en) * | 2009-06-30 | 2012-04-26 | Univeristy Of Florida Research Foundation Inc. | Enhancement mode hemt for digital and analog applications |
KR101243836B1 (ko) * | 2009-09-04 | 2013-03-20 | 한국전자통신연구원 | 반도체 소자 및 그 형성 방법 |
KR101226955B1 (ko) | 2009-12-11 | 2013-01-28 | 한국전자통신연구원 | 전계 효과 트랜지스터의 제조방법 |
RU2463682C1 (ru) * | 2011-01-24 | 2012-10-10 | Открытое акционерное общество "Научно-исследовательский институт полупроводниковых приборов" (ОАО "НИИПП") | Способ изготовления полевого транзистора |
JP2013004572A (ja) * | 2011-06-13 | 2013-01-07 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
JP2013077635A (ja) * | 2011-09-29 | 2013-04-25 | Sumitomo Electric Ind Ltd | 半導体装置およびその製造方法 |
KR101923972B1 (ko) * | 2012-12-18 | 2018-11-30 | 한국전자통신연구원 | 트랜지스터 및 그 제조 방법 |
US9281204B2 (en) * | 2014-04-23 | 2016-03-08 | Freescale Semiconductor, Inc. | Method for improving E-beam lithography gate metal profile for enhanced field control |
US9502535B2 (en) | 2015-04-10 | 2016-11-22 | Cambridge Electronics, Inc. | Semiconductor structure and etch technique for monolithic integration of III-N transistors |
US9614069B1 (en) | 2015-04-10 | 2017-04-04 | Cambridge Electronics, Inc. | III-Nitride semiconductors with recess regions and methods of manufacture |
US9536984B2 (en) | 2015-04-10 | 2017-01-03 | Cambridge Electronics, Inc. | Semiconductor structure with a spacer layer |
WO2017015225A1 (en) | 2015-07-17 | 2017-01-26 | Cambridge Electronics, Inc. | Field-plate structures for semiconductor devices |
US10068976B2 (en) * | 2016-07-21 | 2018-09-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Enhancement mode field-effect transistor with a gate dielectric layer recessed on a composite barrier layer for high static performance |
WO2019045763A1 (en) * | 2017-08-31 | 2019-03-07 | Google Llc | FABRICATION OF A DEVICE USING A MULTILAYER STACK |
CN110808207B (zh) * | 2019-11-13 | 2023-09-26 | 中国电子科技集团公司第十三研究所 | 一种t型纳米栅及其制备方法 |
KR102395979B1 (ko) * | 2020-09-01 | 2022-05-09 | 포항공과대학교 산학협력단 | 레지스트 마스크, 도미노 리소그래피 및 이를 이용해 제작된 구조체 |
KR102356610B1 (ko) * | 2020-09-21 | 2022-02-07 | 포항공과대학교 산학협력단 | 레지스트 마스크, 쓰러짐 제어 리소그래피 및 이를 이용해 제작된 구조체 |
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KR100276077B1 (ko) | 1998-05-11 | 2001-01-15 | 이계철 | 미세 티자형 게이트 전극의 제작방법 |
KR100264532B1 (ko) | 1998-09-03 | 2000-09-01 | 이계철 | 모드 또는 문턱전압이 각기 다른 전계효과 트랜지스터 제조 방법 |
KR100379619B1 (ko) | 2000-10-13 | 2003-04-10 | 광주과학기술원 | 단일집적 e/d 모드 hemt 및 그 제조방법 |
US7084021B2 (en) * | 2003-03-14 | 2006-08-01 | Hrl Laboratories, Llc | Method of forming a structure wherein an electrode comprising a refractory metal is deposited |
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2004
- 2004-12-02 KR KR1020040100421A patent/KR100606290B1/ko not_active IP Right Cessation
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- 2005-07-14 US US11/180,726 patent/US7183149B2/en active Active
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Publication number | Publication date |
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US20060121658A1 (en) | 2006-06-08 |
KR20060061627A (ko) | 2006-06-08 |
JP2006165507A (ja) | 2006-06-22 |
KR100606290B1 (ko) | 2006-07-31 |
US7183149B2 (en) | 2007-02-27 |
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