US6197626B1 - Method for fabricating semiconductor device - Google Patents

Method for fabricating semiconductor device Download PDF

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US6197626B1
US6197626B1 US09/028,963 US2896398A US6197626B1 US 6197626 B1 US6197626 B1 US 6197626B1 US 2896398 A US2896398 A US 2896398A US 6197626 B1 US6197626 B1 US 6197626B1
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semiconductor film
region
catalyst metal
film
mask
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Shunpei Yamazaki
Hisashi Ohtani
Hideto Ohnuma
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H01L21/02686—Pulsed laser beam
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02422—Non-crystalline insulating materials, e.g. glass, polymers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02672—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using crystallisation enhancing elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • H01L27/1277—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor using a crystallisation promoting species, e.g. local introduction of Ni catalyst
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate

Definitions

  • the invention disclosed in this specification relates to a thin film transistor and a fabrication method thereof and more particularly to a circuit and a device constructed by using a thin film transistor.
  • a thin film transistor (hereinafter referred to as a TFT or the like) constructed by forming a thin film semiconductor or a silicon semiconductor film in particular on a substrate.
  • the active matrix type liquid crystal display has a structure in which the TFT is disposed as a switching device in each pixel electrode arranged in a matrix.
  • a liquid crystal display in which not only the matrix circuit but also a peripheral driving circuit thereof is constructed by TFTs (which is called a peripheral driving circuit integrated display).
  • the TFT is also used in various integrated circuits and multi-layered integrated circuit (three-dimensional IC).
  • the TFT using the amorphous silicon film has an electrical characteristic which is far lower than that using a single crystal semiconductor used in general semiconductor integrated circuits. Therefore, it is the present situation that it is used only in the limited uses such as a switching device of the active matrix circuit.
  • a crystal silicon film may be used, instead of the amorphous silicon film, in order to improve the characteristic of the TFT using the amorphous silicon film.
  • a silicon film having a crystallinity beside single crystal silicon is called poly-crystal silicon, poly-silicon, microcrystal silicon and the like.
  • Such a silicon film having the crystallinity may be obtained by forming the amorphous silicon film at first and then by crystallizing it by heating (annealing). This method is called solid phase growth because the amorphous state changes to the crystal state while keeping the solid state.
  • the Corning 7059® glass used for the active matrix type liquid crystal display has a glass strain point of 593° C. and there is a problem in performing the annealing at 600° C. or more when the increased area of the substrate is taken into consideration.
  • This technology allows a crystal silicon film having a large area to be obtained on a low cost glass substrate with a high productivity.
  • the crystal silicon obtained by such a method has an oriented crystal structure and shows very excellent characteristics in response to the orientation.
  • a method for fabricating a semiconductor device comprises, as its one exemplary fabrication steps are shown in FIGS. 1A through 2I, steps of forming a crystal silicon film 107 on an insulated surface by using metal element which promotes crystallization of silicon (FIGS. 1 A and 1 B); forming a mask 109 on the crystal silicon film (FIG. 1 C); gettering the metal element to specific regions 111 and 112 of the crystal silicon film by using the mask 119 (FIG. 2 E); and forming an active layer 116 of a device by using the mask 109 (which turns out to be a part 115 as its side is etched) (FIG. 2 H).
  • a method for fabricating a semiconductor device comprises steps of forming a crystal silicon film on an insulated surface by using metal element which promotes crystallization of silicon; forming a mask on the crystal silicon film; selectively doping element selected among nitrogen, phosphorus, arsenic, antimony and bismuth to the crystal silicon film by using the mask; performing a heat treatment to getter the metal element to regions which have been doped; and removing the doped regions by using the mask.
  • the dopant is phosphorus.
  • a method for fabricating a semiconductor device comprises steps of forming a crystal silicon film on an insulated surface by using metal element which promotes crystallization of silicon; forming a mask on the crystal silicon film; selectively doping element selected among nitrogen, phosphorus, arsenic, antimony and bismuth to the crystal silicon film by using the mask; performing a heat treatment to getter the metal element to regions which have been doped; and forming an active layer of a device by using the regions from which the metal element has been gettered by utilizing the mask.
  • a method for fabricating a semiconductor device comprises, as its concrete fabrication steps are shown in FIGS. 1A through 2I, steps of forming a crystal silicon film 107 on an insulated surface by using metal element which promotes crystallization of silicon (FIGS. 1 A and 1 B); forming a mask 109 on the crystal silicon film 107 (FIG. 1 C); selectively doping element selected among nitrogen, phosphorus, arsenic, antimony and bismuth (phosphorus in this case) to the crystal silicon film by using the mask 109 (FIG. 1 D); performing a heat treatment to getter the metal element to regions 111 and 112 which have been doped (FIG.
  • the above-mentioned steps are characterized in that phosphorus is doped by using the mask 109 and that a pattern 116 is obtained by using the pattern 115 which has been obtained by side-etching the mask 109 .
  • Ni nickel
  • the metal element which promotes the crystallization of silicon it is most preferable to use Ni (nickel) as the metal element which promotes the crystallization of silicon.
  • one or a plurality of types of metal elements selected among Fe, Co, Ni, Ru, Rh, Pd, Os, Ir, Pt, Cu and Au may be used as the metal element which promotes the crystallization of silicon.
  • a compound film represented as Si x Ge 1 ⁇ x (0 ⁇ x ⁇ 1) may be used instead of the crystal silicon film.
  • the amorphous silicon film i.e. the starting film, may be made of the compound film represented as Si x Ge 1 ⁇ x (0 ⁇ x ⁇ 1).
  • FIGS. 1A through 1D are diagrammatic views showing steps for fabricating a TFT
  • FIGS. 2E through 2I are diagrammatic views showing steps for fabricating the TFT
  • FIGS. 3J through 3M are diagrammatic views showing steps for fabricating the TFT
  • FIG. 4 is a chart showing concentration of nickel element in a region to which phosphorus has been doped and a region not doped;
  • FIGS. 5A through 5E are diagrammatic views showing steps for fabricating a TFT
  • FIGS. 6A through 6C are diagrammatic views showing steps for obtaining a crystal silicon film
  • FIGS. 7A through 7E are diagrammatic views showing steps for fabricating a PTFT and an NTFT on one and the same substrate;
  • FIGS. 8F through 8J are diagrammatic views showing steps for fabricating the PTFT and the NTFT on one and the same substrate;
  • FIGS. 9K through 9L are diagrammatic views showing steps for fabricating the PTFT and the NTFT on one and the same substrate;
  • FIGS. 10A through 10D are diagrammatic views showing steps for fabricating a bottom gate type TFT
  • FIGS. 11E through 11H are diagrammatic views showing steps for fabricating the bottom gate type TFT
  • FIGS. 12A through 12F show schematic structures of equipments utilizing the present invention.
  • FIGS. 13A through 13E are diagrammatic views showing a part of steps for fabricating a TFT.
  • FIGS. 1A-1D, 2 E- 2 I and 3 J- 3 M are diagrammatic views showing steps for fabricating a TFT according to a first embodiment.
  • a silicon oxide film is formed so as to be 300 nm in thickness as an underlying film on a glass substrate 101 as shown in FIG. 1A by means of plasma CVD or sputtering.
  • an amorphous silicon film 103 is formed so as to be 50 nm in thickness by means of low pressure thermal CVD.
  • the thickness of the amorphous silicon film may be selected from a range from 20 to 100 nm.
  • a compound containing silicon represented as Si x Ge 1 ⁇ x may be utilized.
  • a silicon oxide film not shown is formed so as to be 120 nm in thickness by means of plasma CVD. Then, this silicon oxide film is patterned to form a mask 104 .
  • a slit-like opening 105 is created on the mask 104 .
  • This opening 105 has a thin and long shape longitudinally from the front side to the depth direction of the figure as shown in FIG. 1 A.
  • the nickel element is held in contact selectively with the surface of the amorphous silicon film 103 in the region of the opening 105 .
  • methods for introducing nickel there are methods of plasma CVD, of sputtering, of plasma treatment by discharging from an electrode containing nickel, of gas adsorption, of ion implantation and the like.
  • this specimen is heated for 4 hours within a nitrogen atmosphere at 600° C.
  • the nickel element diffuses from the region where the opening 105 is provided into the amorphous silicon film and thereby, the crystallization advances as indicated by an arrow 106 as shown in FIG. 1B
  • This crystallization is observed as a singular one which advances along the direction parallel to the substrate.
  • a crystal silicon film 107 whose crystal growth has advanced in the direction parallel to the substrate as indicated by the arrow 106 is obtained.
  • the condition of the above-mentioned heating for the crystallization may be selected from a range from 550 to 700° C. When nickel element is used, it is not so effective to increase the heating temperature.
  • the mask 104 made of the silicon oxide film is removed.
  • infrared rays are irradiated to anneal the silicon film. This step reduces defects in the region where the crystallization has advanced and enhances the crystallinity.
  • a silicon oxide film and a silicon nitride film not shown are formed so as to be 200 nm in thickness, respectively, by means of plasma CVD.
  • a resist mask 108 is formed and the silicon oxide film and the silicon nitride film formed before are patterned by means of dry etching as shown in FIG. 1 C.
  • a state in which a pattern 109 of the silicon oxide film and a pattern 110 of the silicon nitride film are laminated is obtained.
  • the laminated pattern is formed on the region where the crystal silicon film 107 has been grown.
  • phosphorus is doped on the surface of the exposed silicon film as shown in FIG. 1 D.
  • phosphorus ions are accelerated and implanted to regions 111 and 112 by using plasma doping.
  • doping phosphorus ions by accelerating and implanting the ions is shown here, it is possible to adopt the following other methods as doping methods, each comprising steps of:
  • the condition of the heat treatment may be selected from a range from 400° C. to a strain point of the substrate. It may be selected from a range from 400 to 650° C. in general.
  • nickel element moves from a region 113 to the regions 111 and 112 as indicated by arrows 114 in FIG. 2 E. That is, the nickel element existing in the region 113 is gettered to the regions 111 and 112 .
  • Ni 3 P, Ni 5 P 2 , Ni 2 P, Ni 3 P 2 , Ni 2 P 3 , NiP 2 and NiP 3 and these combinations are very stable at least in an atmosphere in temperature of about 700° C. or less. Accordingly, nickel moves from the region 113 to the regions 111 and 112 unilaterally.
  • the concentration of nickel element in the region 113 decreases by several times as compared to that in the regions 111 and 112 through the step shown in FIG. 2 E.
  • FIG. 4 shows a result of concentration of the residual nickel element in the region where phosphorus has been doped (the region corresponding to the region 111 in FIG. 2E) and in the region not doped (the region corresponding to the region 113 in FIG. 2E) measured by SIMS (secondary ion mass spectroscopy) on a specimen processed under the similar condition with the present embodiment.
  • a measured curve A in FIG. 4 represents the concentration of nickel element in the region where phosphorus ions have been accelerated and implanted.
  • a measured curve B in FIG. 4 represents the concentration of nickel element in the region where no phosphorus ions have been accelerated and implanted.
  • isotropic etching is performed to the silicon oxide film pattern 109 by masking with the silicon nitride film pattern 110 as shown in FIG. 2 F. That is, the side of the silicon oxide film 109 is etched. Thus, a silicon oxide film pattern 115 whose periphery has been etched is obtained as shown in FIG. 2 F.
  • the silicon nitride film pattern 110 is removed as shown in FIG. 2 G.
  • This silicon film pattern 116 is formed by utilizing the region 113 where nickel has been gettered. This silicon film pattern 116 turns out to be an active layer of the TFT later.
  • the nickel element existing in high concentration in the regions 111 and 112 is suppressed from getting into the final remaining pattern 116 by adopting the steps shown in FIGS. 2F through 2G. That is, the etched region of the silicon oxide film 115 whose side has been etched in the step in FIG. 2F becomes the margin, preventing the nickel element existing in the regions 111 and 112 from entering the pattern 116 .
  • the silicon oxide film pattern 115 is removed next. Then, a silicon oxide film 117 is formed so as to be 100 nm in thickness so as to cover the silicon film pattern 116 by means of plasma CVD as shown in FIG. 2 I.
  • a porous anodic oxide film 120 (aluminum oxide film) is formed so as to be 500 nm in thickness by means of anodic oxidation as shown in FIG. 3 J. At this time, the porous anodic oxide film 120 is formed on the side of the pattern because the resist mask 119 exists. An aqueous solution containing 3% of oxalic acid is used as an electrolyte in forming the porous anodic oxide film 120 .
  • the resist mask 119 is removed and another anodic oxidation is performed.
  • an ethylene glycol solution containing 3% of tartaric acid neutralized by aqueous ammonia is used as an electrolyte.
  • a anodic oxide film 121 having a minute film quality is formed so as to be 80 nm in thickness.
  • the anodic oxide film 121 is formed on the circumference and the surface of the aluminum pattern 122 because the electrolyte infiltrates to the inside of the porous anodic oxide film 120 .
  • the remaining aluminum pattern 122 turns out to be a gate electrode. Thus, a state shown in FIG. 3J is obtained.
  • the exposed silicon oxide film 117 is removed by means of dry etching. Then, a remaining silicon oxide film 123 is obtained. Thus, a state shown in FIG. 3K is obtained.
  • NTFT N channel type TFT
  • plasma doping is used as a method for doping phosphorus.
  • a PTFT P channel type TFT
  • P channel type TFT may be fabricated by doping boron.
  • Phosphorus is doped selectively to the active layer pattern 116 .
  • a source region 11 , a low concentrate impurity region 12 , a channel region 13 , a low concentrate impurity region 14 and a drain region 15 are formed in a manner of self-alignment as shown in FIG. 3 L.
  • the regions 12 and 14 turn out to be the low concentrate impurity regions by the following reasons (“low concentrate” means that the concentration of impurity deciding a channel type is low as compared to that of the source and drain regions).
  • the silicon oxide film 123 remains on the regions 12 and 14 . Accordingly, part of phosphorus ions accelerated and implanted to the regions 12 and 14 are blocked by the silicon oxide film 123 . As a result, phosphorus is doped to the regions 12 and 14 in low concentrate as compared to that of the regions 11 and 15 .
  • the region 13 turns out to be a channel region, because the gate electrode 122 and the anodic oxide film 121 around that mask it and no phosphorus is doped there.
  • an offset gate region (which functions as a high resistant region similarly to the low concentrate impurity region) is formed in adjacent to the channel region by the thickness of the anodic oxide film 121 .
  • the thickness of the anodic oxide film 121 is as thin as 80 nm in the present embodiment, so that its existence is negligible when the turn-around of phosphorus ions during doping is taken into consideration.
  • an silicon oxide film 16 is formed as an interlayer insulating film by means of plasma CVD and a silicon nitride film 17 is formed further by means of plasma CVD as shown in FIG. 3 M.
  • a polyimide resin film 124 is formed. Using the resin film allows the surface thereof to be flattened. Beside polyimide, polyamide, polyimide amide, acryl, epoxy and the like may be used.
  • the present embodiment relates to an improvement of the fabrication steps shown in FIGS. 1A through 3M.
  • FIGS. 5A through 5E show part of steps for fabricating a TFT according to the second embodiment.
  • a crystal silicon film 503 which is crystallized at least partly in accordance to the fabrication steps shown in FIGS. 1A and 1B is obtained on a glass substrate 501 .
  • an underlying silicon oxide film 502 is formed on a glass substrate 501 .
  • a silicon oxide film not shown is formed. Then, the silicon oxide film is patterned by utilizing a resist mask 504 to obtain a pattern 505 as shown in FIG. 5 A.
  • phosphorus ions are accelerated and implanted by means of plasma doping.
  • the accelerated phosphorus ions are implanted to regions 506 and 507 shown in FIG. 5 B.
  • No phosphorus ions are implanted to a region 500 .
  • the side of the silicon oxide film pattern 505 is etched as indicated by the reference numeral ( 508 ) (side etching) by utilizing the resist mask 504 as shown in FIG. 5 C. Thereafter, the resist mask 504 is removed.
  • FIG. 5 D a heat treatment is implemented as shown in FIG. 5 D. This heat treatment is implemented within a nitrogen atmosphere at 600° C. for 2 hours.
  • nickel element moves from the region 500 to the regions 506 and 507 . That is, the nickel element contained in the region 500 is gettered to the regions 506 and 507 .
  • the silicon film is patterned by masking with the silicon oxide film pattern 509 as shown in FIG. 5 E.
  • the regions 506 and 507 are completely taken away and regions of the region 500 adjacent to the regions 506 and 507 (which correspond to the side etched regions in the above-mentioned step shown in FIG. 5C) are also removed to suppress the nickel element from entering the region which is utilized in the end as an active layer of a device.
  • the silicon oxide film pattern 509 is removed to obtain the silicon film pattern 510 .
  • the TFT is fabricated by using this silicon film pattern 510 as its active layer.
  • the present embodiment is a case when crystallization is implemented by a method which is different from the crystal growth in the direction parallel to the substrate as shown in the first embodiment.
  • the present embodiment also uses nickel to obtain a crystal silicon film.
  • the method of the present embodiment is to crystallize the whole surface of an amorphous silicon film uniformly by introducing nickel element on the whole surface, not to grow crystal in the direction parallel to the substrate by selectively introducing nickel element as described in the first embodiment.
  • FIGS. 6A through 6C show steps for fabricating a crystal silicon film according to the present embodiment.
  • a silicon oxide film 602 is formed as an underlying film on a glass substrate 601 .
  • an amorphous silicon film 603 is formed by means of low pressure thermal CVD or plasma CVD. Thus, a state shown in FIG. 6A is obtained.
  • a nickel acetate solution is applied on the whole surface of the amorphous silicon film 603 .
  • an extra solution is spun away by using a spinner. It is noted that it is desirable to form a very thin oxide film on the surface of the amorphous silicon film 603 before applying the solution to improve the wettability (hydrophilic property) of the surface of the silicon film to suppress the solution from being repelled.
  • the oxide film may be formed by irradiating UV rays within an oxygen atmosphere, by treating by aqueous ozone, or the like.
  • a heat treatment is implemented to obtain a crystal silicon film 604 as shown in FIG. 6 C.
  • This heat treatment may be performed within an nitrogen atmosphere at 600° C. for 4 hours.
  • This heat treatment step allows a state in which the whole film has been crystallized uniformly, not the crystal growth in the specific direction as shown in FIG. 1, to be obtained.
  • This fabrication steps are characterized in that they are simple as compared to the fabrication steps shown in FIGS. 1A through 1D.
  • a TFT having a higher performance may be obtained by utilizing the crystal obtained by using the lateral growth shown in FIGS. 1A through 1D when the TFT is to be fabricated.
  • Steps for fabricating a PTFT and an NTFT in the same time will be shown in the present embodiment.
  • An arrangement for gettering nickel element from the channel and the low concentrate impurity region to the source and drain regions, in addition to the gettering of nickel element from the active layer, will be shown.
  • FIGS. 7A-7E, 8 F- 8 J, and 9 K- 9 L show the fabrication steps of the present embodiment.
  • an underlying film 702 is formed on a glass substrate 701 and a crystal silicon film (or a silicon film which is crystallized partly) 703 is obtained as shown in FIG. 7A by the previously described methods.
  • a silicon oxide film and a silicon nitride film not shown are laminated and are patterned by resist masks 707 and 709 .
  • a pattern of laminated films composed of a silicon oxide film pattern 704 and a silicon nitride film pattern 706 is obtained.
  • a pattern of laminated films composed of a silicon oxide film pattern 705 and a silicon nitride film pattern 708 is obtained.
  • a state shown in FIG. 7A is obtained.
  • the resist masks 707 and 709 are removed and phosphorus ions are doped by means of plasma doping as shown in FIG. 7 B.
  • the phosphorus ions are doped into regions 710 , 711 and 712 .
  • nickel element is gettered to the regions 710 , 711 and 712 by implementing a heat treatment.
  • the side of the silicon oxide film pattern 704 is etched by utilizing the silicon nitride film pattern 706 as shown in FIG. 7 C.
  • a silicon oxide film pattern 713 whose side has been etched as indicated by the reference numeral ( 715 ) is obtained.
  • a silicon oxide film pattern 714 whose side has been etched is obtained.
  • Silicon film patterns 716 and 717 obtained here are composed of the regions from which the nickel element has been gettered to the regions 710 , 711 and 712 and in which the concentration of nickel element has been dropped.
  • a silicon oxide film 718 which functions as a gate insulating film is formed by means of plasma CVD. Further, aluminum patterns 719 and 720 are formed by forming an aluminum film and by patterning it by using resist masks 71 and 72 . Thus, a state shown in FIG. 7E is obtained.
  • porous anodic oxide films 721 and 724 are formed by anodic oxidation as shown in FIG. 8 F. Then, the resist masks 71 and 72 are removed and anodic oxide films 723 and 726 having minute film quality are formed. Gate electrodes 722 and 725 are defined in this state.
  • phosphorus is doped as shown in FIG. 8 G. This doping is performed to cause the nickel to be gettered again to the doped regions.
  • a heat treatment is performed at 400° C. for 1 hour.
  • the nickel element remaining in a region 731 is gettered to regions 727 and 728 .
  • the nickel element remaining in a region 732 is gettered to regions 729 and 730 .
  • the nickel element is gettered from the regions 731 and 732 again thoroughly. That is, the nickel element is removed thoroughly from the regions 731 and 732 as shown in FIG. 8 H. It is noted that it is important to perform this heat treatment step under the condition (mainly upper limit temperature) in which the gate electrodes 722 and 725 can sustain.
  • this treatment may be performed in a temperature in which the glass substrate can sustain. In this case, a higher gettering effect can be obtained.
  • the regions 727 , 728 , 729 and 730 are regions which turn out to be sources and drains in the end, the TFTs are not influenced so much in their operation even if the concentration of nickel element is high more or less.
  • the regions 731 and 732 are regions where the channels and low concentrate impurity regions are formed, so that they are sensitive to the existence of nickel element.
  • the channel region is the region where a carrier density is changed by an electric field applied from the gate electrode, the existence of the metal element which traps them gives an adverse effect on its operation.
  • the low concentrate impurity region or the low concentrate impurity region on the drain side in particular has a function of relaxing a high electric field applied between the channel region and the drain region and a relatively high electric field is applied there.
  • Nickel element within a semiconductor functions as a trap level of the carriers.
  • the trap level exists in the region where the relatively high electric field is applied, there arises changes in the motion of the carriers and in the characteristics of the semiconductor. Accordingly, the nickel element remaining in the low concentrate impurity region may cause problems such that a leak current is generated and a withstand voltage drops.
  • the exposed silicon oxide film 718 is etched as shown in FIG. 8 I. Then, remaining silicon oxide films 733 and 734 are obtained in this state. Further, the porous anodic oxide films 721 and 724 are removed as shown in FIG. 8 I.
  • Phosphorus is doped again in the state shown in FIG. 8 I. In this step, phosphorus is doped in high concentration to a region 735 , in low concentration to a region 736 , in low concentration to a region 738 and in high concentration to a region 739 .
  • a drain region 740 , a low concentrate impurity region 741 , a channel region 742 , a low concentrate impurity region 743 and a source region 744 of the NTFT are formed in a manner of self-alignment.
  • a resist mask 745 is formed on the NTFT and boron is doped this time by means of plasma doping.
  • the conductive type of the regions to which phosphorus has been doped before is reversed by this doping and turns out to be P type.
  • a source region 745 , a low concentrate impurity region 746 , a channel region 747 , a low concentrate impurity region 748 and a drain region 749 of the PTFT are formed as shown in FIG. 8J in a manner of self-alignment.
  • a silicon oxide film 750 , a silicon nitride film 751 and a resin film 752 are formed as interlayer insulating films as shown in FIG. 9 K. Then, contact holes are created to form a source electrode 753 and a drain electrode 754 of the PTFT as well as a source electrode 756 and a drain electrode 755 of the NTFT.
  • the NTFT and the PTFT may be formed on one and the same substrate as shown in FIG. 9 L through the same fabrication steps.
  • the step for gettering nickel from the active layer composing the TFT (step in FIG. 7C) and the step for gettering nickel from the channel region and the low concentrate impurity region (step in FIG. 8H) are performed in the present embodiment to thoroughly prevent the nickel element from influencing on the device characteristics of the TFT.
  • the device having a better characteristic and high reliability may be obtained. This is important in constructing integrated circuits.
  • the present embodiment relates to an arrangement for obtaining a crystal silicon film by a method different from the fabrication steps shown in FIGS. 1A and 1B.
  • This embodiment utilizes the methods as described in Japanese Patent Application No. 8-335152 which has been applied by the present applicant, which in turn corresponds to a pending U.S. application Ser. No. 08/785,489, the disclosure of which is incorporated herein by reference.
  • FIGS. 1A and 1B An outline of the fabrication steps will be explained by using FIGS. 1A and 1B.
  • a quartz substrate is used instead of the glass substrate as a substrate 101 because this process requires a heat treatment in a high temperature of 900° C. or more which is unsustainable for the glass substrate.
  • a silicon oxide film 102 is formed as an underlying film on the quartz substrate 101 . It is noted that because the quartz substrate having a good flatness is available, the underlying film needs not be formed in such a case.
  • an amorphous silicon film is formed so as to be 50 nm in thickness by means of low pressure thermal CVD. Further, a mask 104 made of a silicon oxide film is formed as shown in FIG. 1 A.
  • the mask 104 is removed and another heat treatment is implemented.
  • This heat treatment is implemented within an oxygen atmosphere containing 3 volume % of HCl at 950° C. for 30 minutes.
  • a thermal oxide film is formed in a thickness of 30 nm and the thickness of the silicon film is reduced from 50 nm to 35 nm.
  • the present embodiment is characterized in this step. That is, in this step, nickel element is removed from the whole film to the atmosphere in the shape of nickel chloride.
  • the crystallinity of the film is remarkably improved as interstitial silicon atoms and silicon atoms unstably combined within the film are consumed for the formation of the thermal oxide film. That is, the density of defects within the film is dramatically reduced.
  • the thermal oxide film thus formed is removed. After that, the TFT is fabricated in accordance to the steps in and after FIG. 1 C.
  • the quartz substrate (or ceramic substrate) needs to be used as the substrate in the present embodiment because no effect of forming the thermal oxide film is obtained unless the temperature is at least 900° C. or more. However, it allows a device having a very high characteristic to be obtained.
  • the present embodiment allows to obtain the device whose characteristic is stabilized further by the synergetic effect of the effect obtained by performing the step for forming the thermal oxide film and the gettering effect of nickel as shown in the first embodiment.
  • the fabrication steps of the present embodiment may be utilized also in the fabrication steps shown in FIGS. 6A through 6C.
  • the present embodiment is a case of fabricating a bottom gate type TFT (an inversely staggered TFT in this case).
  • a silicon oxide film 1002 is formed as an underlying film on a glass substrate 1001 as shown in FIG. 10 A.
  • a gate electrode 1003 is formed by using a silicide material.
  • a silicon oxide film 1000 which covers the gate electrode 1003 and functions as a gate insulating film is formed.
  • a crystal silicon film 1004 is formed by the methods shown in FIGS. 1 and 6. Thus, a state shown in FIG. 10A is obtained.
  • a silicon oxide film pattern 1005 and a silicon nitride film pattern 1006 are obtained by using a resist mask 1007 as shown in FIG. 10 B. Then, phosphorus is doped. As a result, phosphorus ions are accelerated and implanted to regions 1008 and 1009 . No phosphorus ions are implanted to a region 1010 .
  • the side of the silicon oxide film pattern 1005 is etched by using the silicon nitride film pattern 1006 to form a pattern 1011 as shown in FIG. 10 D.
  • the silicon nitride film 1006 is removed and the silicon film region 1010 is patterned by utilizing the silicon oxide film pattern 1011 .
  • a pattern 1012 made of the crystal silicon film is obtained as shown in FIG. 11 E.
  • a mask 1013 made of a silicon nitride film is disposed as shown in FIG. 11 F and phosphorus is doped by means of plasma doping.
  • a source region 1014 , a channel region 1015 and a drain region 1016 are formed.
  • a silicon oxide film 1017 and a resin film 1018 are formed as shown in FIG. 11 G.
  • the bottom gate type TFT may be obtained.
  • the present embodiment is a case of using doped silicon or silicide for the gate electrode in the steps for fabricating the TFT shown in FIGS. 7 through 9.
  • the gettering effect may be enhanced further because a temperature as high as 600° C. may be applied in the step shown in FIG. 8 C.
  • FIGS. 12A through 12F show the outline of each equipment.
  • FIG. 12A shows a portable information processing terminal having a communication function utilizing telephone lines.
  • This electronic equipment is provided with an integrated circuit 2006 using thin film transistors within a main body 2001 . It also comprises an active matrix type liquid crystal display 2005 , a camera section for taking in images and a control switch 2004 .
  • FIG. 12B shows an electronic equipment called a head mount display.
  • This equipment is arranged so as to mount its main body 2101 on a head by a band 2103 and has a function of displaying images artificially in front of eyes.
  • the images are created by liquid crystal display 2102 corresponding to right and left eyes.
  • Such an electronic equipment uses circuits using thin film transistors in order to miniaturize its size and lighten its weight.
  • FIG. 12C shows an electronic equipment having a function of displaying map data and various data based on signals from satellites.
  • the data from the satellites received by an antenna 2204 is processed by an electronic circuit provided within a main body 2201 and necessary information is displayed on a liquid crystal display 2202 .
  • the equipment is controlled by control switches 2202 .
  • a circuit using thin film transistors is used also in such an equipment in order to miniaturize the whole structure.
  • FIG. 12D shows a portable telephone.
  • This electronic equipment comprises an antenna 2306 , a voice output section 2302 , a liquid crystal display 2304 , control switches 2305 and a voice input section 2303 on a main body 2301 .
  • An electronic equipment shown in FIG. 12E is a portable image pickup device called a video camera.
  • This electronic equipment comprises a liquid crystal display 2402 mounted on a closing member of a main body 2401 and control switches 2404 mounted on the closing member.
  • An electronic equipment shown in FIG. 12F is a projector type liquid crystal display.
  • This equipment comprises a light source 2502 , a liquid crystal display 2503 and an optical system 2504 in a main body 2501 and has a function of projecting images on a screen 2505 .
  • the liquid crystal display in each electronic equipment described above either transmission type or reflection type display may be used.
  • the transmission type display is advantageous in terms of displaying characteristics
  • the reflection type is advantageous in pursuing lower power consumption, miniaturization and lightening.
  • a flat panel display such as an active matrix type EL display and a plasma display may be utilized.
  • FIGS. 13A through 13E show the fabrication steps of the present embodiment. At first, an underlying film 1302 is formed on a glass substrate 1301 and a crystal silicon film 1303 is obtained by utilizing nickel element as shown in FIG. 13 A.
  • a mask 1312 made of a silicon oxide film is formed.
  • phosphorus is doped.
  • the phosphorus is doped to regions 1313 and 1315 as shown in FIG. 13 B. No phosphorus is doped to a region 1304 .
  • a heat treatment is performed in the state shown in FIG. 13B to getter the nickel element existing in the region 1304 to the regions 1313 and 1315 .
  • the regions 1313 and 1315 are removed by using the mask 1312 made of the silicon oxide film as shown in FIG. 13 C.
  • the mask 1312 made of the silicon oxide film is removed to obtain a state shown in FIG. 13 E. Thereafter, a TFT is fabricated by utilizing the pattern 1307 made of the crystal silicon film.
  • the regions 111 and 112 are removed by utilizing the silicon oxide film pattern 109 before etching its side and then the side of the pattern 109 as well as the peripheral part of the exposed region 113 are etched.
  • the utilization of the invention disclosed in the present specification allows the technology of obtaining the TFT whose device characteristic varies less to be provided in obtaining the TFT by using the crystal silicon film obtained by using metal element.

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US20010016376A1 (en) 2001-08-23
JP3844552B2 (ja) 2006-11-15
KR100544040B1 (ko) 2006-05-30
EP0862201A3 (en) 1999-10-13
TW430868B (en) 2001-04-21
CN1195879A (zh) 1998-10-14
KR100627598B1 (ko) 2006-09-25
EP0862201A2 (en) 1998-09-02
JPH10242476A (ja) 1998-09-11
KR20060086811A (ko) 2006-08-01
US6448118B2 (en) 2002-09-10
KR19980071715A (ko) 1998-10-26

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