US20160233141A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
US20160233141A1
US20160233141A1 US15/018,563 US201615018563A US2016233141A1 US 20160233141 A1 US20160233141 A1 US 20160233141A1 US 201615018563 A US201615018563 A US 201615018563A US 2016233141 A1 US2016233141 A1 US 2016233141A1
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United States
Prior art keywords
substrate
heat sink
semiconductor device
bonded
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
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US15/018,563
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English (en)
Inventor
Masao HIROBE
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Amkor Technology Singapore Holding Pte Ltd
Original Assignee
J Devices Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by J Devices Corp filed Critical J Devices Corp
Assigned to J-DEVICES CORPORATION reassignment J-DEVICES CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HIROBE, MASAO
Publication of US20160233141A1 publication Critical patent/US20160233141A1/en
Priority to US16/592,213 priority Critical patent/US11488886B2/en
Assigned to AMKOR TECHNOLOGY JAPAN, INC. reassignment AMKOR TECHNOLOGY JAPAN, INC. CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: J-DEVICES CO., LTD.
Assigned to AMKOR TECHNOLOGY JAPAN, INC. reassignment AMKOR TECHNOLOGY JAPAN, INC. CORRECTIVE ASSIGNMENT TO CORRECT THE CONVEYING PARTY NAME PREVIOUSLY RECORDED AT REEL: 53597 FRAME: 184. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Assignors: J-DEVICES CORPORATION
Assigned to Amkor Technology Singapore Holding Pte. Ltd. reassignment Amkor Technology Singapore Holding Pte. Ltd. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: AMKOR TECHNOLOGY JAPAN, INC.
Priority to US17/977,957 priority patent/US20230111868A1/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1027—IV
    • H01L2924/10272—Silicon Carbide [SiC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/1033—Gallium nitride [GaN]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H01L2924/16153—Cap enclosing a plurality of side-by-side cavities [e.g. E-shaped cap]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H01L2924/1616—Cavity shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Definitions

  • the present invention relates to a semiconductor device and in particular to a technique for a flip-chip bonding (FCB) package with a low-stress heat sink.
  • FCB flip-chip bonding
  • a Japanese Patent Laid-Open No. 2012-33559 discloses a semiconductor device in which a heat radiation member is embedded in a sealing member for embedding a semiconductor chip to improve heat radiation. According to the semiconductor device disclosed in the Japanese Patent Laid-Open No. 2012-33559, an appropriate surface area of the heat radiation member can improve the heat radiation of the semiconductor device, which allows the thermal resistance thereof to be reduced.
  • a semiconductor device including a substrate whose surface is made of an insulation material, a semiconductor chip flip-chip connected on the substrate, and a heat sink bonded to the semiconductor chip via a thermal interface material and fixed to the substrate outside the semiconductor chip, wherein the heat sink has a protrusion part protruding toward the substrate and bonded to the substrate via a conductive resin between a part bonded to semiconductor chip and a part fixed to the substrate and the heat sink has a stress absorbing part.
  • the stress absorbing part may has lower rigidity than the part excluding the stress absorbing part of the heat sink.
  • the stress absorbing part may be thinned by a groove provided on the surface of the heat sink opposing the substrate.
  • the number of the grooves provided thereon may be two or more.
  • the protrusion part may be arranged to surround the semiconductor chip and the stress absorbing part may be arranged inside or outside the protrusion part.
  • the stress absorbing part may be arranged adjacent to the protrusion part.
  • the stress absorbing part may include a bottomed hole provided in the surface of the heat sink opposing the substrate or a through hole.
  • the heat sink may be made of Cu, Al, or AlSiCu ceramic.
  • the protrusion part may be bonded an electrode arranged on the substrate via the conductive resin, and the electrode may be electrivally connected to a ground.
  • FIG. 1 is a schematic diagram of a semiconductor device according to a first embodiment of the present invention
  • FIG. 2 is a cross section of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 3A is a top view of a heat sink of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 3B is a cross section of the heat sink of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 4A is a top view of a heat sink of a semiconductor device according to a second embodiment of the present invention.
  • FIG. 4B is a cross section of the heat sink of the semiconductor device according to the second embodiment of the present invention.
  • FIG. 5A is a top view of a heat sink of a semiconductor device according to a third embodiment of the present invention.
  • FIG. 5B is a cross section of the heat sink of the semiconductor device according to the third embodiment of the present invention.
  • FIG. 6A is a top view of a heat sink of a semiconductor device according to a fourth embodiment of the present invention.
  • FIG. 6B is a cross section of the heat sink of the semiconductor device according to the fourth embodiment of the present invention.
  • FIG. 7A is a top view of a heat sink of a semiconductor device according to a fifth embodiment of the present invention.
  • FIG. 7B is a cross section of the heat sink of the semiconductor device according to the fifth embodiment of the present invention.
  • FIG. 8 is a cross section of a semiconductor device according to a comparative example
  • FIG. 9 is a cross section of a semiconductor device according to a comparative example.
  • FIG. 10 is a cross section of the semiconductor device according to the first embodiment of the present invention.
  • the present invention provides a highly reliable semiconductor device which prevents the heat sink from being peeled off from the substrate by stress accompanied with thermal expansion and thermal shrinkage.
  • the semiconductor device according to the present invention is described below with reference to the attached drawings.
  • the semiconductor device according to the present invention can be implemented in many different embodiments and shall not be interpreted by limiting to the description of the embodiments shown below.
  • the same components or the conponents having similar functions are given the same reference number and a repetitive description thereof is omitted.
  • the structure of the semiconductor device according to the first embodiment is described with reference to FIGS. 1 to 3 .
  • FIG. 1 is a schematic diagram showing a structure of a semiconductor device 100 according to a first embodiment of the present invention.
  • the semiconductor device 100 comprises a substrate 10 , a semiconductor chip 30 is arranged on the substrate 10 and a heat sink 20 is arranged on the substrate 10 and the semiconductor chip 30 .
  • the substrate 10 and the heat sink 20 are arranged in opposition to each other. Both the substrate 10 and the heat sink 20 has substantially the same area.
  • the semiconductor device 100 is nearly cubic.
  • FIG. 2 is a cross section along the line I-I′ in FIG. 1 in the semiconductor device 100 according to the first embodiment of the present invention.
  • the substrate 10 is a package substrate (a supporting substrate) and an organic substrate using an organic material such as polyimide or epoxy resin.
  • the substrate 10 may be a multilayered buildup substrate. Electrodes electrically connected with the semiconductor chip 30 and a protrusion part 22 are arranged on a surface of the substrate 10 opposing the heat sink 20 . An electrode electrically connected with elements except the semiconductor chip 30 , an external device, or another substrate may be appropriately arranged on another surface of the substrate 10 . Except for the electrodes described above, the surfaces of the substrate 10 are generally composed of insulation materials such as the organic material forming the substrate 10 , an epoxy resin coating material coated on the substrate 10 , thermosetting epoxy insulation film, or the like.
  • the semiconductor chip 30 is arranged on the substrate 10 .
  • the semiconductor chip 30 is flip-chip connected to the substrate 10 via a conductive bump 49 .
  • Cupper (Cu), silver (Ag), gold (Au), and solder may be used as the bump 49 .
  • the semiconductor chip 30 is a semiconductor element such as an IC chip, an LSI chip, or the like.
  • a semiconductor element using silicon (Si) as a main material is used as the semiconductor chip 30 , however, silicon carbide (SiC) or gallium nitride (GaN) may be used as main materials of the semiconductor chip 30 .
  • the first embodiment shows an example where one semiconductor element is arranged on the substrate, however, a plurality of semiconductor elements may be arranged side by side or a plurality of semiconductor elements may be stacked one on top of another on the substrate.
  • An underfill 45 for fixing the semiconductor chip 30 is arranged between the substrate 10 and the semiconductor chip 30 .
  • Epoxy resin, cyanate ester resin, acryl resin, polyimide resin, silicone resin or the like may be used as the underfill 45 .
  • the heat sink 20 is arranged on the semiconductor chip 30 via a thermal interface material 47 .
  • a known thermal conduction material (TIM) is used as the thermal interface material 47 .
  • a heat radiation sheet, graphite, thermal conduction greaseor the like, for example, may be used as the thermal interface material 47 .
  • a material high in thermal conductivity and adhesive property is used as the thermal interface material 47 to effectively transfer the heat of the semiconductor chip 30 to the heat sink 20 .
  • Cupper (Cu), aluminum (Al), AlSiCu ceramics or the like may be used as the heat sink 20 .
  • a fixing part 28 protruding toward the substrate 10 is provided near the outer periphery of the heat sink 20 .
  • the fixing part 28 of the heat sink 20 is fixed to the substrate 10 by an adhesive 41 .
  • the adhesive 41 may be insulative or conductive. If the protrusion part 22 and a stress absorbing part 26 described later are neglected, the heat sink 20 has a shape of a lid having the fixing part 28 protruding toward the substrate 10 , near the outer periphery of the heat sink 20 .
  • the side face of the substrate 10 and that of the heat sink 20 are arranged on substantially the same plane, however, the side face of the heat sink 20 may be positioned nearer the center of the semiconductor device 100 than the side face of the substrate 10 , or contrarily, the side face of the heat sink 20 may be positioned farther from the center of the semiconductor device 100 than the side face of the substrate 10 .
  • the heat sink 20 has the protrusion part 22 protruding toward the opposing substrate 10 in addition to the fixing part 28 described above.
  • the protrusion part 22 is arranged between a part bonded to the semiconductor chip 30 and the fixing part 28 .
  • the protrusion part 22 is bonded to the substrate 10 via a conductive adhesive 43 .
  • An electrode electrically connected to the ground of the substrate 10 is arranged on the part of the substrate 10 bonded to the protrusion part 22 .
  • the protrusion part 22 is electrically connected with the ground of the substrate 10 via the electrode and arranged to stabilize the ground of the substrate 10 . It is preferable that the protrusion part 22 is arranged in a position near the semiconductor chip 30 from the viewpoint of the stabilization of the ground.
  • the stress absorbing part 26 is arranged between the part bonded to the semiconductor chip 30 and the protrusion part 22 on the heat sink 20 of the semiconductor device 100 according to the first embodiment of the present invention. More specifically, a recessed groove 24 is formed between the part bonded to the semiconductor chip 30 and the protrusion part 22 on the surface of the heat sink 20 opposing the substrate 10 . If the fixing part 28 and the protrusion part 22 on the heat sink 20 are neglected, the heat sink 20 has a fixed thickness, however, the stress absorbing part 26 is formed such that the part where the groove 24 is arranged is thinner than the periphery of the groove 24 .
  • the fixing part 28 , the protrusion part 22 , and the groove 24 of the heat sink 20 may be formed by etching.
  • FIG. 3A is a top view of the heat sink 20 of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 3B is a cross section of the heat sink 20 along the line I-I′ in FIG. 3A .
  • a rectangular area 30 ′ surrounded by a dotted line shows a position where the heat sink 20 is bonded to the semiconductor chip 30 (not shown).
  • the protrusion part 22 is arranged in a rectangular shape so as to surround the area 30 ′ bonded to the semiconductor chip 30 .
  • the fixing part 28 bonded and fixed to the substrate 10 (not shown) is arranged on the outer periphery of the heat sink 20 .
  • the groove 24 (the stress absorbing part 26 ) is arranged between the area 30 ′ bonded to the semiconductor chip 30 and the protrusion part 22 .
  • the groove 24 is arranged in proximity to a position where the protrusion part 22 is arranged. More preferably, the groove 24 is arranged adjacent to the position where the protrusion part 22 is arranged.
  • the groove 24 (the stress absorbing part 26 ) is also arranged in a rectangular shape so as to surround the area 30 ′ bonded to the semiconductor chip 30 .
  • the substrate 10 and the semiconductor chip 30 included in the semiconductor device 100 use an organic substrate and silicon as main materials respectively.
  • the thermal expansion coefficient of the substrate 10 is about 15 ppm and that of the semiconductor chip 30 is about 3.4 ppm.
  • the value of the thermal expansion coefficient of the substrate 10 is greater than the value of that of the semiconductor chip 30 .
  • the semiconductor device 100 is totally convexly-warped toward the upper surface (toward the upper side in FIG. 2 and the surface on which the heat sink 20 is arranged) because the substrate 10 is greater in shrinkage.
  • the substrate 10 is firmly bonded and fixed to the heat sink 20 by the adhesive 41 in the neighborhood of the outer circumference of the semiconductor device 100 .
  • the heat sink 20 is firmly bonded and fixed to the semiconductor chip 30 by the thermal interface material 47 .
  • the heat sink 20 is firmly bonded and fixed to the substrate 10 and the semiconductor chip 30 , so that the heat sink 20 is subjected to stress in a warping direction at a low temperature in the temperature cyclic test.
  • the heat sink 20 of the semiconductor device 100 has the recessed groove 24 between the part bonded to the semiconductor chip 30 and the fixing part 28 fixed to the substrate 10 .
  • the stress absorbing part 26 is formed in the heat sink 20 by the groove 24 .
  • the groove 24 is provided for the heat sink 20 to form the stress absorbing part 26 in which the heat sink 20 at the part where the groove 24 is formed is thinner than the heat sink 20 at the part where the groove 24 is not formed.
  • the stress absorbing part 26 can reduce the distortion of the heat sink 20 caused by heat.
  • the stress absorbing part 26 of the heat sink 20 has lower rigidity than the surroundings thereof. Thus, arranging the part having low rigidity in the heat sink 20 allows the thermal stress of the heat sink 20 to be reduced.
  • the stress absorbing part 26 is arranged in the heat sink 20 to allow the warp of the semiconductor device 100 to be reduced at a low temperature in the temperature cyclic test. This can reduce stress caused by a warp of the semiconductor device 100 at the part where the protrusion part 22 of the heat sink 20 is bonded to the substrate 10 , which can prevent the protrusion part 22 from being peeled off from the substrate 10 at the part.
  • FIG. 4A is a top view of the heat sink 20 of the semiconductor device according to the second embodiment.
  • FIG. 4B is a cross section of the heat sink 20 along the line I-I′ in FIG. 4A .
  • the second embodiment is characterized in that two grooves 24 a and 24 b are arranged in the heat sink 20 to form the stress absorbing part 26 .
  • the grooves 24 a and 24 b are formed between an area 30 ′ bonded to the semiconductor chip 30 and the protrusion part 22 .
  • the groove 24 a is preferably arranged in proximity to a position where the protrusion part 22 is arranged.
  • the groove 24 a is more preferably arranged adjacent to the position where the protrusion part 22 is arranged.
  • the groove 24 a is formed in a rectangular shape viewed from the top so as to surround the area 30 ′.
  • the grooves 24 b is arranged between the groove 24 a and the area 30 ′ bonded to the semiconductor chip 30 .
  • the groove 24 b is formed also in a rectangular shape viewed from the top so as to surround the area 30 ′.
  • the two grooves 24 a and 24 b are arranged between the area 30 ′ bonded to the semiconductor chip 30 and the protrusion part 22 to further reduce the rigidity of the stress absorbing part 26 than that in the first embodiment, which allows the stress to be further reduced at the part where the protrusion part 22 of the heat sink 20 is bonded to the substrate 10 .
  • FIG. 5A is a top view of the heat sink 20 of the semiconductor device according to the third embodiment.
  • FIG. 5B is a cross section of the heat sink 20 along the line I-I′ in FIG. 5A .
  • the third embodiment is characterized in that a bottomed hole 24 c is arranged in the heat sink 20 to form the stress absorbing part 26 .
  • the bottomed hole 24 c is arranged between the area 30 ′ bonded to the semiconductor chip 30 and the protrusion part 22 .
  • the bottomed hole 24 c is arranged in proximity to the position where the protrusion part 22 is arranged. More preferably, the bottomed hole 24 c is arranged adjacent to the position where the protrusion part 22 is arranged. As can be seen from FIG.
  • a plurality of the bottomed holes 24 c are arranged in the heat sink 20 at regular intervals along the protrusion part 22 so as to surround the area 30 ′. Furthermore, a plurality of the bottomed holes 24 c may be further arranged at regular intervals along the inside of an area where the bottomed holes 24 c are arranged so as to surround the area 30 ′.
  • the groove 24 is not formed in the heat sink 20 unlike the first embodiment, instead, a plurality of the bottomed holes 24 c are arranged in the heat sink 20 to form the stress absorbing part 26 , which can reduce stress caused by a warp of the semiconductor device 100 at the part where the protrusion part 22 is bonded to the substrate 10 , as is the case with the first embodiment.
  • FIG. 6A is a top view of the heat sink 20 of the semiconductor device according to the fourth embodiment.
  • FIG. 6B is a cross section of the heat sink 20 along the line I-I′ in FIG. 6A .
  • the fourth embodiment is characterized in that a through hole 24 d , which serves as the stress absorbing part 26 and passes from the surface opposing the substrate 10 to the surface being the outside of the semiconductor device, is arranged in the heat sink 20 .
  • the through hole 24 d may be arranged in the same position as that where the bottomed hole 24 c shown in the third embodiment is arranged.
  • the through hole 24 d is arranged in proximity to the position where the protrusion part 22 is arranged. More preferably, the through hole 24 d is arranged adjacent to the position where the protrusion part 22 is arranged.
  • rigidity is lowered around the part where a plurality of the through holes 24 d (the stress absorbing parts 26 ) are arranged in the heat sink 20 . This can reduce stress caused by a warp of the semiconductor device 100 at the part where the protrusion part 22 is bonded to the substrate 10 , as is the case with the first embodiment.
  • FIG. 7A is a top view of the heat sink 20 of the semiconductor device according to the fifth embodiment.
  • FIG. 7B is a cross section of the heat sink 20 along the line I-I′ in FIG. 7A .
  • the fifth embodiment is characterized in that a groove 24 e is arranged outside the protrusion part 22 , that is to say, between the protrusion part 22 and the fixing part 28 to form the stress absorbing part 26 , unlike the first embodiment.
  • the groove 24 e is arranged in proximity to the position where the protrusion part 22 is arranged. More preferably, the groove 24 e is arranged adjacent to the position where the protrusion part 22 is arranged.
  • the groove 24 e is arranged outside the protrusion part 22 to also allow the stress to be reduced at the part where the protrusion part 22 is bonded to the substrate 10 , as is the case with the first embodiment in which the groove 24 is arranged inside the protrusion part 22 .
  • the first to fifth embodiments of the present invention are described above with reference to FIGS. 1 to 7B .
  • the present invention is not limited to the above embodiments.
  • the present invention can be implemented by appropriately modifying the above embodiments within a range not deviated from the gist of the invention or combining the embodiments with each other.
  • the first embodiment shows an example where the groove 24 is continuously arranged in a rectangular shape.
  • the groove 24 may be intermittently arranged so as to surround the area 30 ′.
  • a groove may be arranged in parallel to each side of the protrusion part 22 formed in a rectangular shape and bottomed holes or through holes may be formed at parts corresponding to the corners thereof.
  • the grooves 24 and 24 e may be arranged inside and outside of the position where the protrusion part 22 is arranged respectively by combining the first embodiment with the fifth embodiment.
  • the groove 24 may be formed in other different shapes such as a circular, a triangular shape, and others.
  • the stress absorbing part 26 formed by the groove 24 or the like only has to be arranged between the part where the heat sink 20 is bonded to the semiconductor chip 30 and the fixing part 28 where the heat sink 20 is bonded and fixed to the substrate 10 . It is preferable that the stress absorbing part 26 is arranged in a position near the protrusion part 22 from the viewpoint of the reduction of stress at the part where the protrusion part 22 is bonded to the substrate 10 .
  • the first to third and fifth embodiments describe that the groove 24 or the like are arranged in the surface, opposing the substrate 10 , of the heat sink 20 , however the embodiments of the present invention are not limited to the above.
  • the groove and the bottomed hole may be arranged in the surface opposite to the surface opposing the substrate 10 , that is to say, in the surface exposed outside the semiconductor device 100 .
  • the following shows the results of a stress simulation for the semiconductor device according to an embodiment of the present invention and a comparative example thereof.
  • FIG. 8 is a cross section of a semiconductor device 700 according to the comparative example.
  • the semiconductor device 700 comprises a glass ceramic substrate 710 .
  • the glass ceramic substrate small in transmission loss is often used in a semiconductor package of a high-speed device.
  • a semiconductor chip 730 is flip-chip connected on the glass ceramic substrate 710 via a bump 749 and a lid-like heat sink 720 is bonded to the upper surface of the semiconductor chip 730 via a thermal interface material 747 .
  • the heat sink 720 is bonded and fixed to the glass ceramic substrate 710 by an adhesive 741 at the outer circumferential part of the glass ceramic substrate 710 .
  • An underfill 745 is arranged between the substrate 710 and the semiconductor chip 30 .
  • the heat sink 720 has a protrusion part 722 protruding toward the glass ceramic substrate 710 outside the area bonded to the semiconductor chip 730 .
  • the protrusion part 722 is bonded to the glass ceramic substrate 710 via a conductive adhesive 743 and electrically connected to the ground of the glass ceramic substrate 710 .
  • the lid-like heat sink 720 uses copper
  • the semiconductor chip 730 uses silicon
  • the glass ceramic substrate 710 uses glass ceramic.
  • the thermal expansion coefficients of the materials used as the components are given below. Those of copper, silicon, and glass ceramic are about 15 ppm, about 3.4 ppm, and about 9.5 ppm respectively. For this reason, at a low temperature ( ⁇ 55° C., for example) in the temperature cyclic test at the manufacturing process of semiconductor device 700 , the semiconductor device 700 is convexly-warped upward in FIG. 8 caused by the mismatch among the thermal expansion coefficients of the components. However, for the glass ceramic substrate 710 , the warp is suppressed comparatively smaller, which hardly causes a problem that the parts where the components are boned to each other are peeled off.
  • FIG. 9 shows a cross section of a semiconductor device 800 according to a comparative example.
  • the semiconductor device 800 shown in FIG. 9 is the same as the semiconductor device 700 shown in FIG. 8 in structure, however, the semiconductor device 800 is different from the semiconductor device 700 in that an organic substrate 810 is used as a package substrate.
  • a lid-like heat sink 820 uses copper
  • a semiconductor chip 830 uses silicon
  • the organic substrate 810 is a substrate including an organic material.
  • the thermal expansion coefficients of the materials used as the components are given below. Those of copper, silicon, and the organic substrate are about 15 ppm, about 3.4 ppm, and about 15 ppm respectively. Therefore, the organic substrate 810 shown in FIG. 9 is greater than the glass ceramic substrate 710 shown in FIG. 8 in the thermal expansion coefficient. At a low temperature ( ⁇ 55° C., for example) in the temperature cyclic test, even the semiconductor device 800 using the organic substrate 810 as the package substrate is convexly-warped upward in FIG. 9 .
  • the parts where the components are boned to each other can be peeled off because the organic substrate 810 is greater than the glass ceramic substrate 710 shown in FIG. 8 in the warp.
  • the application of stress to the part where the protrusion part 822 of the heat sink 820 is bonded to the organic substrate 810 can cause release the protusion part 822 and the organic substrate 810 , which may cause a problem that makes it difficult to keep the stability of a ground potential.
  • FIG. 10 shows a cross section of a semiconductor device 100 according to one embodiment of the present invention.
  • the semiconductor device 100 shown in FIG. 10 is the same as the semiconductor device 100 described in the first embodiment in structure. Materials used as the main components of the semiconductor device 100 are given below.
  • the substrate 10 uses the organic substrate including an organic material
  • the heat sink uses copper
  • the adhesive 41 uses epoxy resin
  • the underfill 45 uses epoxy resin
  • the conductive adhesive 43 uses Ag paste
  • the thermal interface material 47 uses a metal.
  • the heat sink 20 is in a square shape, the length “a” of one side thereof is 26.5 mm and the thickness “b” thereof is 0.5 mm, the width “c” of the groove 24 is 4 mm and the depth “d” thereof is 0.3 mm, the length “e” of the protrusion part 22 is 0.3 mm and the thickness “f” thereof in the planar direction is 0.5 mm, the length “g” of the fixing part 28 is 0.7 mm and the thickness “h” thereof in the planar direction is 2 mm, and a distance “i” between the two protrusion parts 22 where the semiconductor chip 30 is arranged is 16 mm.
  • the semiconductor chip 30 is in a square shape, the length “j” of one side thereof is 11 mm, and the semiconductor chip 30 is arranged at the center of the square substrate 10 and the heat sink 20 .
  • the length “k” of one side of the substrate 10 is 27 mm and the thickness “m” thereof is 0.99 mm.
  • the width of the stress absorbing part 26 is 4 mm and the thickness thereof is 0.3 mm.
  • the semiconductor device according to the comparative example shall not have the groove 24 (the stress absorbing part 26 ) in FIG. 10 and others shall be the same in structure.
  • a table 1 shows temperature and stress at the maximum stress in the part where the protrusion part 22 is bonded to the substrate 10 (referred to as a ground connection part) at a temperature cyclic test ( ⁇ 55° C. to 125° C.).
  • the maximum stress at the ground connection part in the semiconductor device without the groove 24 according to the comparative example was 3.75 Mpa.
  • the maximum stress at the ground connection part in the semiconductor device with the groove 24 (i.e., with the stress absorbing part 26 ) according to the example was 3.52 Mpa. Therefore, it is clear from the simulation that the example according to an embodiment of the present invention could reduce more stress applied to the ground connection part than the comparative example at a temperature of ⁇ 55° C.
  • a table 2 shows the experimental results of the temperature cyclic test ( ⁇ 55° C. to 125° C.) for the semiconductor devices according to the example and the comparative example with the dimensions and structure same as those set in the above simulation.
  • the number of the semiconductor devices subjected to the temperature cyclic test is taken as a denominator and the number of the semiconductor devices rejected in conduction tests applied to the devices is taken as a numerator.
  • the reason the semiconductor devices are rejected in the conduction tests seems to be that a part of the protrusion part 22 is peeled off from the substrate 10 or the protrusion part 22 is wholly peeled off from the substrate 10 at the part where the protrusion part 22 of the heat sink 20 is bonded to the substrate 10 .
  • the semiconductor device with the groove 24 (with the stress absorbing part 26 ) of the example according to an embodiment of the present invention could more substantially reduce the ratio in which semiconductor devices are rejected in the conduction tests carried out after the temperature cyclic tests than the semiconductor device without the groove 24 of the comparative example. For this reason, it was confirmed that the example according to an embodiment of the present invention was effective for preventing the protrusion part 22 from being peeled off from the substrate at the part where the protrusion part 22 is bonded to the substrate 10 .
  • the stress absorbing part having low rigidity is provided for the heat sink to allow reducing stress caused by the warp of the semiconductor device at the part where the protrusion part of the heat sink is bonded to the substrate and preventing the protrusion part from being peeled off from the substrate at the part where the protrusion part is bonded to the substrate.
  • This can hold a stable electrical connection between the heat sink and the ground. Consequently, a highly reliable semiconductor device can be provided.

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  • Engineering & Computer Science (AREA)
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US15/018,563 2015-02-09 2016-02-08 Semiconductor device Abandoned US20160233141A1 (en)

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US16/592,213 US11488886B2 (en) 2015-02-09 2019-10-03 Semiconductor device
US17/977,957 US20230111868A1 (en) 2015-02-09 2022-10-31 Semiconductor device

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