TWI709205B - 半導體裝置 - Google Patents

半導體裝置 Download PDF

Info

Publication number
TWI709205B
TWI709205B TW105103225A TW105103225A TWI709205B TW I709205 B TWI709205 B TW I709205B TW 105103225 A TW105103225 A TW 105103225A TW 105103225 A TW105103225 A TW 105103225A TW I709205 B TWI709205 B TW I709205B
Authority
TW
Taiwan
Prior art keywords
substrate
semiconductor device
protrusion
heat dissipation
dissipation plate
Prior art date
Application number
TW105103225A
Other languages
English (en)
Other versions
TW201640629A (zh
Inventor
廣部正雄
Original Assignee
日商安靠科技日本公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日商安靠科技日本公司 filed Critical 日商安靠科技日本公司
Publication of TW201640629A publication Critical patent/TW201640629A/zh
Application granted granted Critical
Publication of TWI709205B publication Critical patent/TWI709205B/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3675—Cooling facilitated by shape of device characterised by the shape of the housing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3672—Foil-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29193—Material with a principal constituent of the material being a solid not provided for in groups H01L2224/291 - H01L2224/29191, e.g. allotropes of carbon, fullerene, graphite, carbon-nanotubes, diamond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3736—Metallic materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/059—Being combinations of any of the materials from the groups H01L2924/042 - H01L2924/0584, e.g. oxynitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1027—IV
    • H01L2924/10272—Silicon Carbide [SiC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/1033—Gallium nitride [GaN]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H01L2924/16153—Cap enclosing a plurality of side-by-side cavities [e.g. E-shaped cap]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H01L2924/1616—Cavity shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Ceramic Engineering (AREA)
  • Cooling Or The Like Of Electrical Apparatus (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

配置於半導體晶片及基板之散熱板因伴隨熱膨脹或熱收縮之應力，而有自散熱板及基板剝離之問題。本發明之其中一目的在於解決此問題而提供包括基板、半導體晶片及散熱板之半導體裝置。基板表面包含絕緣材料。半導體晶片以覆晶方式連接於基板上。散熱板經由熱介面材料黏著於半導體晶片，且於半導體晶片之外側固定至基板。散熱板具有突起部及應力吸收部。突起部位於散熱板黏著於半導體晶片之部分及固定於基板之部分之間，並朝向基板突出且藉由導電性樹脂黏著於基板。根據本發明能夠防止散熱板因伴隨熱膨脹或熱收縮之應力而自散熱板及基板剝離。

Description

半導體裝置
本發明關於一種半導體裝置，特別是關於具有低應力散熱板之覆晶接合（flip chip bonding）封裝中之技術。
隨著半導體裝置之高速化及輸入／輸出（I／O）之數量增加，來自半導體裝置之發熱量亦增大。因此，已知有於半導體晶片上黏著散熱板之半導體封裝。另外，還有以高速裝置之低噪化為目的，而已知有將散熱板連接至封裝基板之接地件（ground）以使接地件安定之技術。
舉例而言，為了提升散熱性，如參照專利文獻1（日本專利公開案2012-33559號公報）揭示於埋設有半導體晶片之密封部材之內部埋設散熱部材之半導體裝置。根據專利文獻1所揭示之半導體裝置，散熱部件之表面積若是適當，則可提升半導體裝置之散熱性，而能夠企圖降低熱阻抗。
然而，為了提升散熱性而設置之散熱板，卻可能有因伴隨熱膨脹或熱收縮之應力而發生剝離等問題。
本發明之一目的在於解決散熱板因伴隨熱膨脹及熱收縮之應力而剝離之問題。
關於本發明之一實施型態之半導體裝置，其包含基板、半導體晶片及散熱板。基板之表面之材質包含絕緣材料。半導體晶片以覆晶方式連接於基板上。散熱板經由熱介面材料黏著於半導體晶片，且於半導體晶片之外側固定至基板。散熱板具有突起部及應力吸收部。突起部位於散熱板黏著於半導體晶片之部分及散熱板固定於基板之部分之間。突起部朝向基板突出且藉由導電性樹脂黏著於基板。
前述應力吸收部之剛性亦可小於前述散熱板除了前述應力吸收部以外之部分之剛性。
亦可藉由設置於前述散熱板之朝向前述基板之表面之溝槽而薄化前述應力吸收部。
其中，前述溝槽之數量亦可設置成二個。
再者，前述散熱板之前述突起部亦可設置成於前述半導體晶片之周圍突出，前述散熱板之前述應力吸收部亦可配置於前述突起部之內側或外側。
前述應力吸收部亦可配置成相鄰於前述突起部。
其中，前述應力吸收部亦可包含設置於前述散熱板之朝向前述基板之表面之有底孔或貫通孔。
再者，前述散熱板之材質亦可包含銅（Cu）、鋁（Al）或鋁矽銅（AlSiCu）陶瓷。
本發明所提供之半導體裝置，能夠防止散熱板因伴隨熱膨脹及熱收縮之應力而剝離，而提升可靠度。
以下，將參照圖式說明關於本發明之實施型態。然而，關於本發明之半導體裝置能夠以多種相異之態樣實施，而並非限定解釋為以下所示之實施型態之記載內容。另外，以本實施型態參照之圖式圖式中，相同部分或具有相同功能之部分將附上相同符號，且省略重覆的說明。
＜第一實施型態＞
使用圖1至圖3說明關於第一實施型態之半導體裝置之結構。
以下將說明半導體裝置之整體結構。
圖1為繪示關於本發明之第一實施型態之半導體裝置100之整體構造之概略圖。半導體裝置100中，半導體晶片30配置於基板10上，散熱板20配置於基板10及半導體晶片30上。基板10與散熱板20相互面對配置，二者之面積概略一致，而半導體裝置100具有略為立方體之形狀。
以下將說明半導體裝置之剖面圖。
圖2為關於本發明之第一實施型態之半導體裝置100中，繪製圖1沿I－I’線剖面之剖面圖。
基板10可為封裝基板（支撐基板），亦可為使用聚醯亞胺（polyimide）或環氧（epoxy）樹脂等之有機材料之有機基板。基板10亦可為多層結構之積聚（build up）基板。基板10之朝向散熱板20之表面設置有半導體晶片30及用以電性連接於突起部22之電極。於基板10之其他表面亦可適當配置半導體晶片30以外之元件，或者用以電性連接於外部裝置或基板等之電極。基板10之表面除了上述電及以外，可藉由構成基板10之有機材料及塗佈於基板10之環氧系之樹脂塗層劑或熱硬化性之環氧系絕緣薄膜等，而以絕緣材料構成整體。
半導體晶片30配置成經由導電性凸塊（bump）49而覆晶連接於基板10上，其中能夠使用銅（Cu）、銀（Ag）、金（Au）及焊料或焊錫等材料做為凸塊49。半導體晶片30可為積體電路晶片（integral circuit chip）或大規模積體電路晶片（large scaled integration chip，LSI chip）等之半導體元件。半導體晶片30雖可使用以矽（Si）做為主材料之半導體元件，但亦可為以碳化矽（SiC）或氮化鎵（GaN）等材料做為主材料之半導體元件。此外，雖然第一實施型態中例示為一個半導體元件配置於基板上，但亦可配置成於基板上並列多個半導體元件，或亦可堆疊多個半導體元件。
基板10與半導體晶片30之間配置有用以固定半導體晶片30之底膠45。底膠45能夠使用環氧樹脂、氰酸酯（cyanate ester）樹脂、丙烯酸樹脂、聚醯亞胺樹脂、矽氧樹脂等材料。
散熱板20經由熱界面材料47而配置於半導體晶片30上。熱界面材料47亦可使用已知之熱傳導材料（TIM），例如散熱片、石墨（graphite）、散熱膏（thermal grease）等材料。熱界面材料47為了將半導體晶片30之發熱有效率地熱傳遞至散熱板20，而可使用高度熱傳導性高且優良黏著性之材料。此外，散熱板20亦可使用銅（Cu）、鋁（Al）、鋁矽銅（AlSiCu）陶瓷等材料。
散熱板20之外周附近具有朝向基板10突出之固定部28。基板10藉由黏著劑41而與散熱板20之固定部28固定。其中，黏著劑41可具有絕緣性，亦可具有導電性。暫時忽略不觀看將於之後說明之突起部22及應力吸收部26時，散熱板20具有蓋狀之形狀，其中此蓋狀具有散熱板20之外周附近朝向基板10突出之固定部28。基板10之側面及散熱板20之側面雖以配置於略為相同平面上之方式形成，但散熱板20之側面亦可位於比基板10之側面更接近半導體裝置100之中心之位置。或者反過來散熱板20之側面亦可位於比基板10之側面更遠離半導體裝置100之中心之位置。
散熱板20除了上述固定部28以外，更具有朝向基板10之方向突出之突起部22。突起部22配置於與半導體晶片30黏著之部分與固定部28之間。突起部22經由導電性黏著劑43而黏著於基板10。基板10之黏著於突起部22之部分，可配置有電性連接於基板10之接地件之電極。亦即，突起部22電性連接於基板10之接地件，而配置成用以安定化基板10之接地件。其中，從接地件安定化之觀點看來，突起部22可配置成接近半導體晶片30之位置。
關於本發明之第一實施型態之半導體裝置100之散熱板20中，應力吸收部26配置於與半導體晶片30黏著之部分及突起部22之間。更具體而言，於散熱板20朝向基板10之表面，可於與半導體晶片30黏著之部分及突起部22之間形成凹狀的溝槽24。於散熱板20中，暫時忽略不觀看固定部28及突起部22之場合下，散熱板20雖具有一定厚度，而配置有溝槽24之部分之厚度薄於其周邊，從而於此形成應力吸收部26。其中，散熱板20之固定部28、突起部22及溝槽24等，可藉由蝕刻方式形成。
以下將說明散熱板20之俯視結構。
圖3A為關於本發明之第一實施型態之半導體裝置之散熱板20之俯視圖，圖3B為圖3A中沿I－I’線剖面之剖面圖。虛線所圍繞而成之矩形區域30’，表示半導體晶片30（未繪示於圖3A及圖3B）黏著於散熱板20之位置。突起部22可配置成矩形且圍繞黏著半導體晶片30之區域。更甚者，於散熱板20之外周部配置有黏著且固定於基板10（未繪示於圖3A及圖3B）之固定部28。於第一實施型態中，黏著半導體晶片30之區域與形成有突起部22之部分之間，配置有溝槽24（應力吸收部26）。其中，溝槽24可配置成接近配置有突起部22之位置。更甚者，溝槽24更可配置成相鄰於配置有突起部22之位置。溝槽24（應力吸收部26）與突起部22同樣可形成為矩形且圍繞半導體晶片30之黏著區域。
構成半導體裝置100之基板10及半導體晶片30，可分別以有機基板及矽做為主材料。基板10之熱膨脹係數約為15 ppm，半導體晶片30之熱膨脹係數約為3.4 ppm。如此一來，基板10之熱膨脹係數之數值大於半導體晶片30之熱膨脹係數之數值。因此，於溫度循環試驗之低溫時（例如攝氏負55度），因基板10之收縮量較大，故半導體裝置100會朝向整體之上面（圖2之上側，配置有散熱板20之表面）凸起翹曲。於此，基板10及散熱板20於外周附近以黏著劑41紮實地黏著及固定。再者，散熱板20及半導體晶片30以熱界面材料47紮實地黏著及固定。如此一來，由於散熱板20紮實地黏著且固定於基板10及半導體晶片30，於溫度循環試驗之低溫時，會增加散熱板20於翹曲方向上之應力。
關於本發明之第一實施型態之半導體裝置100之散熱板20，具有溝槽24位於與半導體晶片30黏著之部分及與基板固定之固定部28之間。藉由此溝槽24而於散熱板20形成應力吸收部26。亦即藉由於散熱板20設置溝槽24，使得散熱板20之形成有溝槽24之部分之厚度薄於散熱板20之未形成有溝槽24之部分，從而形成具有較薄厚度之應力吸收部26。藉由應力吸收部26而能夠緩和散熱板20因熱而導致之歪曲。換言之，散熱板20之應力吸收部26之剛性低於其周圍之剛性。如此一來，藉由散熱板20形成有低剛性之部分，而能夠緩和散熱板20之熱應力。舉例而言，藉由散熱板20包含應力吸收部26，而能夠於溫度循環試驗中之低溫時降低半導體裝置100之翹曲現象。因此，能夠降低因半導體裝置100之翹曲而產生於散熱板20之突起部22與基板10之間之黏著部之應力，進而能夠防止此黏著部剝離。
＜第二實施型態＞
以下將一邊參照圖4A及圖4B，一邊說明關於本發明之第二實施型態之半導體裝置之概要。
圖4A為關於本發明之第二實施型態之半導體裝置之散熱板20之俯視圖，圖4B為圖4A中沿I－I’線剖面之剖面圖。於第二實施型態中，其特徵在於散熱板20配置有溝槽24a及溝槽24b之二個溝槽，而藉此形成為應力吸收部26。溝槽24a及溝槽24b形成於黏著半導體晶片30之區域30’與突起部22之間。溝槽24a與第一實施型態之溝槽24同樣可配置成接近配置有突起部22之位置。更甚者，溝槽24a更可配置成相鄰於配置有突起部22之位置。此外，溝槽24a於俯視時之形狀亦可與第一實施型態之溝槽24同樣形成為矩形。溝槽24b可配置於溝槽24a與黏著半導體晶片30之區域30’之間，且俯視時之形狀亦可與溝槽24a同樣形成為矩形。
於第二實施型態中，由於黏著半導體晶片30之區域30’與突起部22之間配置有溝槽24a及溝槽24b之二個溝槽，相較於第一實施型態更可降低應力吸收部26之剛性，故更能夠緩和散熱板20之突起部22與基板10之間之黏著部之應力。
＜第三實施型態＞
以下將一邊參照圖5A及圖5B，一邊說明關於本發明之第三實施型態之半導體裝置之概要。
圖5A為關於第三實施型態之半導體裝置之散熱板20之俯視圖，圖5B為圖5A中沿I－I’線剖面之剖面圖。於第三實施型態中，其特徵在於散熱板20配置有底孔24c，而藉此形成為應力吸收部26。有底孔24c形成於黏著半導體晶片30之區域30’與突起部22之間。有底孔24c可配置成接近配置有突起部22之位置。更甚者，有底孔24c更可配置成相鄰於配置有突起部22之位置。參照圖5A時，可知多個有底孔24c可沿著突起部22以保持一定間隔之方式配置成矩形。更甚者，沿著配置有此些有底孔24c之區域內側，還有多個有底孔24c以保持一定間隔之方式配置成矩形。
如此一來，於第三實施型態中，雖並非如第一實施型態於散熱板20形成溝槽24，但因於散熱板20配置多個凹狀的有底孔24c而藉此形成應力吸收部26，故與第一實施型態同樣地能夠降低因半導體裝置100之翹曲現象而產生於突起部22與基板10之間之黏著部之應力。
＜第四實施型態＞
以下將一邊參照圖6A及圖6B，一邊說明關於本發明之第四實施型態之半導體裝置之概要。
圖6A為關於第四實施型態之半導體裝置之散熱板20之俯視圖，圖6B為圖6A中沿I－I’線剖面之剖面圖。於第四實施型態中，其特徵在於散熱板20配置做為應力吸收部26之貫通孔24d。貫通孔24d自散熱板20之朝向基板10之表面貫通至半導體裝置之外側之表面。貫通孔24d亦可配置成與第三實施型態所示配置有底孔24c之位置相同之位置。貫通孔24d可配置成接近配置有突起部22之位置。更甚者，貫通孔24d更可配置成相鄰於配置有突起部22之位置。
於第四實施型態中，散熱板20之配置有多個貫通孔24d（應力吸收部26）之部分之周圍其剛性降低。因此，與第一實施型態同樣地能夠降低因半導體裝置100之翹曲現象而產生於突起部22與基板10之間之黏著部之應力。
＜第五實施型態＞
以下將一邊參照圖7A及圖7B，一邊說明關於本發明之第五實施型態之半導體裝置之概要。
圖7A為關於第五實施型態之半導體裝置之散熱板20之俯視圖，圖7B為圖7A中沿I－I’線剖面之剖面圖。第五實施型態與第一實施型態相異，於第五實施型態中，其特徵在於溝槽24e位於突起部22之外側，亦即配置於突起部22與固定部28之間，而藉此形成為應力吸收部26。溝槽24e可配置成接近配置有突起部22之位置。更甚者，溝槽24e更可配置成相鄰於配置有突起部22之位置。即使溝槽24e配置於突起部22之外側，與溝槽24配置於突起部22內側之第一實施型態同樣地能夠降低突起部22與基板10之間之黏著部之應力。
＜其他實施型態＞
以上，雖參照圖1至圖7B說明本發明之第一實施型態至第五實施型態，但本發明並非限定於上述之實施型態。於未脫離本發明之要旨之範圍內，亦能夠適當變更上述各個實施型態，或者藉由組合各個實施型態而實施。
舉例而言，於第一實施型態中，雖例示溝槽24配置成連續的矩形，但溝槽24亦可間斷地形成。此外，雖所形成之溝槽實質上平行於形成為矩形之突起部22之各個邊長，但亦可在對應於角落之部分形成有底孔或貫通孔。再者，亦可組合第一實施形態及第五實施形態，而於配置有突起部22之位置之內側及外側分別形成溝槽24及溝槽24e。另外，雖例示將溝槽24形成為凹狀，但亦可為半圓、三角形等其他形狀。其中，藉由溝槽24而形成之應力吸收部26，可形成於散熱板20黏著於半導體晶片30之部分及散熱板20黏著固定於基板10之固定部28之間。而且，從降低突起部22與基板10之間之黏著部之應力的觀點看來，應力吸收部26可形成於接近突起部22之位置。
再者，第一實施形態至第三實施形態及第五實施形態中雖以溝槽24、24a、24b、24e及有底孔24c配置於散熱板20之朝向基板之表面之方式說明實施形態，但本發明實施形態並非限定於此。亦可於將溝槽24、24a、24b、24e及有底孔24c形成於散熱板20之朝向基板之表面之相反表面，亦即露出於半導體裝置100之外部之表面。
＜模擬＞
以下表示關於本發明之實施例之半導體裝置及關於比較例之半導體裝置之應力模擬結果。
以下將說明比較例之結構。
圖8為繪示關於比較例之半導體裝置700之剖面圖。半導體裝置700具有玻璃陶瓷基板710。由於玻璃陶瓷基板710之訊號傳輸損耗較小，故可採用於高速裝置之半導體封裝。半導體晶片730經由凸塊749覆晶連接於玻璃陶瓷基板710上，蓋狀之散熱板720經由熱界面材料747黏著於半導體晶片730之上表面。散熱板720於玻璃陶瓷基板710之外周部經由黏著劑741黏著固定於玻璃陶瓷基板710。底膠745配置於玻璃陶瓷基板710與半導體晶片730之間。
散熱板720於黏著半導體晶片730之區域之外側具有朝向玻璃陶瓷基板710突出之突起部722。突起部722經由導電性黏著劑743黏著於玻璃陶瓷基板710，且電性連接於玻璃陶瓷基板710之接地件。
半導體裝置700之主要構成要素之材料中，蓋狀之散熱板720可使用銅，半導體晶片730可使用矽，玻璃陶瓷基板710可使用玻璃陶瓷。於此，此些構成要素之材料中，其熱膨脹係數分別如下。銅約為15 ppm，矽約為3.4 ppm，玻璃陶瓷約為9.5 ppm。因此，半導體裝置700之製造流程中之溫度循環試驗之低溫時（例如攝氏負55度），由於各個構成要素之熱膨脹係數並不匹配，故半導體裝置700會朝向於圖8之上方凸起翹曲。但是，玻璃陶瓷基板710之場合中，若是將翹曲現象抑制成較小，則幾乎不會發生各個構成要素之間之黏著部之剝離等問題。
近年來，積聚基板等之有機基板中，亦開發出能夠對應高速裝置之基板。有機基板的價格低於玻璃陶瓷基板，故增加採用有機基板做為高速裝置之封裝基板之機會。圖9為關於比較例之半導體裝置800之剖面圖。圖9之半導體裝置800之結構雖然與圖8所示之半導體裝置700相同，但仍有使用有機基板810做為封裝基板之差異點。蓋狀之散熱板820經由熱界面材料847黏著於半導體晶片830。半導體晶片830經由凸塊849覆晶連接於有機基板810上。底膠845配置於有機基板810與半導體晶片830之間。散熱板820於有機基板810之外周部經由黏著劑841黏著固定於有機基板810。散熱板820之凸起部822經由導電性黏著劑843黏著於有機基板810，且電性連接於有機基板810之接地件。
半導體裝置800之主要構成要素之材料中，蓋狀之散熱板820可使用銅，半導體晶片830可使用矽，有機基板810可使用含有機材料之基板。其中，此些構成要素之材料中，其熱膨脹係數分別如下。銅約為15 ppm，矽約為3.4 ppm，含有機材料之基板約為15 ppm。因此，比較圖8之玻璃陶瓷基板710及圖9之有機基板810之熱膨脹係數，則有機基板810之熱膨脹係數較大。使用有機基板810做為封裝基板之半導體裝置800中，於溫度循環試驗之低溫時（例如攝氏負55度），半導體裝置800會朝向於圖9之上方凸起翹曲。此時，由於有機基板810之翹曲現象大於圖8所示之玻璃陶瓷基板710之翹曲現象，故可能會發生各個構成要素間之黏著部之剝離。特別是因散熱板820之突起部822與有機基板810之間之黏著部之應力增加而發生剝離之場合時，會有難以保持接地件電位之安定化之問題。
以下將說明實施例。
圖10為繪示關於本發明之一實施型態之半導體裝置100之剖面圖。圖10所示之半導體裝置100具有與第一實施形態所說明之半導體裝置100相同之結構。於半導體裝置100中，可使用有機基板做為基板10，且可使用含銅（Cu）之散熱板20。而且，可使用環氧樹脂做為黏著劑41，可使用環氧樹脂做為底膠45，可使用銀（Ag）膠做為導電性黏著劑43，且可使用金屬做為熱界面材料47。於此，散熱板20可為正方形，一邊之長度a可為26.5 mm，厚度b可為0.5 mm，溝槽24之寬度c可為4 mm，溝槽24之深度d可為0.3 mm，突起部22之長度e可為0.3 mm，突起部22之俯視方向之厚度f可為0.5 mm，固定部28之長度g可為0.7 mm，固定部28之俯視方向之厚度h可為2 mm，夾住半導體晶片30之突起部22之二邊之間隔i可為16 mm。此外，半導體晶片30可為正方形，一邊之長度j可為11 mm，且可配置於正方形之基板10及散熱板20之中央。再者，基板10之一邊之長度k可為27 mm，厚度m可為0.99 mm。其中，應力吸收部26之寬度可為4 mm，厚度可為0.3 mm。
另一方面，關於比較例之半導體裝置，則未具有圖10中之溝槽24（應力吸收部26），其餘為相同結構。於溫度循環試驗時（例如攝氏負55度至攝氏125度），突起部22與基板10之連接部分（稱之為接地件連接部）發生最大應力時之溫度及應力，如表1所示。
表1
Figure 105103225-A0304-0001
關於未具有溝槽24之比較例之半導體裝置中，接地件連接部之最大應力為3.75 MPa。另一方面，具有溝槽24（亦即具有應力吸收部26）之實施例之接地件連接部之最大應力為3.52 MPa。因此，根據模擬結果，可知實施例相較於比較例，更能夠降低於攝氏負55度時施加於接地件連接部之應力。
＜實驗結果＞
接下來，關於實施例之半導體裝置及關於比較例之半導體裝置具有與上述模擬中所設定之尺寸相同之結構，以此進行溫度循環試驗（攝氏負55度至攝氏125度）之實驗結果如表2所示。表2之數值中，進行溫度循環試驗之半導體裝置之數量為分母，半導體裝置之導通確認為錯誤（NG）之數量為分子。其中，半導體裝置之導通確認為錯誤（NG）的狀況，為考量到其原因在於散熱板20之突起部22與基板10之間之黏著部分之一部分或全部剝離。
表2
Figure 105103225-A0304-0002
參照表2時，關於未具有溝槽24之比較例之半導體裝置之場合中，雖然於800次循環時之導通確認為全部無問題，但於1000次循環時則30個中有6個為錯誤（NG），於1200次循環時則22個中有13個為錯誤（NG），於1500次循環時則7個中有4個為錯誤（NG）。另一方面，關於具有溝槽24（具有應力吸收部26）之實施例之半導體裝置中，於800次循環、於1000次循環、於1200次循環之各個試驗中，雖然分別令30個、30個、28個半導體裝置進行試驗，但皆未出現錯誤（NG）。於1500次循環時則26個中有3個為錯誤（NG）。
如上所述，與關於未具有溝槽24之比較例之半導體裝置相比較，能夠確認關於具有溝槽24（具有應力吸收部26）之實施例之半導體裝置可大幅減少溫度循環試驗中導通確認為錯誤（NG）之比例。因此，能夠確認實施例具有防止突起部22與基板10之間之黏著部剝離之效果。
根據本發明，藉由於散熱板設置剛性較低之應力吸收部，而於半導體裝置之翹曲現象發生時，能夠降低散熱板之突起部與基板之間之黏著部之應力，而能夠防止突起部與基板之間之黏著部之剝離。因此，能夠保持散熱板與接地件之間之安定的電性連接關係。藉此，能夠提供高度可靠性之半導體裝置。
100、700、800‧‧‧半導體裝置 10‧‧‧基板 20、720、820‧‧‧散熱板 22、722、822‧‧‧突起部 24、24a、24b、24e‧‧‧溝槽 24c‧‧‧有底孔 24d‧‧‧貫通孔 26‧‧‧應力吸收部 28‧‧‧固定部 30、730、830‧‧‧半導體晶片 30’‧‧‧區域 41、741、841‧‧‧黏著劑 43、743、843‧‧‧導電性黏著劑 45、745、845‧‧‧底膠 47、747、847‧‧‧熱界面材料 49、749、849‧‧‧凸塊 710‧‧‧玻璃陶瓷基板 810‧‧‧有機基板 a、e、g、j、k‧‧‧長度 b、f、h、m‧‧‧厚度 c‧‧‧寬度 d‧‧‧深度 i‧‧‧間隔
圖1為關於本發明之第一實施型態之半導體裝置之概略圖。 圖2為關於本發明之第一實施型態之半導體裝置之剖面圖。 圖3A為關於本發明之第一實施型態之半導體裝置之俯視圖。 圖3B為關於本發明之第一實施型態之半導體裝置之剖面圖。 圖4A為關於本發明之第二實施型態之半導體裝置之散熱板之俯視圖。 圖4B為關於本發明之第二實施型態之半導體裝置之散熱板之剖面圖。 圖5A為關於本發明之第三實施型態之半導體裝置之散熱板之俯視圖。 圖5B為關於本發明之第三實施型態之半導體裝置之散熱板之剖面圖。 圖6A為關於本發明之第四實施型態之半導體裝置之散熱板之俯視圖。 圖6B為關於本發明之第四實施型態之半導體裝置之散熱板之剖面圖。 圖7A為關於本發明之第五實施型態之半導體裝置之散熱板之俯視圖。 圖7B為關於本發明之第五實施型態之半導體裝置之散熱板之剖面圖。 圖8為關於比較例之半導體裝置之剖面圖。 圖9為關於比較例之半導體裝置之剖面圖。 圖10為關於本發明之第一實施型態之半導體裝置之剖面圖。
100‧‧‧半導體裝置
10‧‧‧基板
20‧‧‧散熱板
22‧‧‧突起部
24‧‧‧溝槽
26‧‧‧應力吸收部
28‧‧‧固定部
30‧‧‧半導體晶片
41‧‧‧黏著劑
43‧‧‧導電性黏著劑
45‧‧‧底膠
47‧‧‧熱界面材料
49‧‧‧凸塊

Claims (14)

  1. 一種半導體裝置，包括：基板，該基板之表面包含絕緣材料；半導體晶片，以覆晶(flip chip)方式連接於該基板上；以及散熱板，經由熱介面材料黏著於該半導體晶片，且於該半導體晶片之外側固定至該基板，其中該散熱板具有突起部及應力吸收部，該突起部位於該散熱板黏著於該半導體晶片之部分和該散熱板固定於該基板之部分之間，該突起部朝向該基板突出且黏著於該基板；該應力吸收部包括在該散熱板中的溝槽，該散熱板在該溝槽的厚度小於該散熱板在該突起部和該散熱板固定於該基板之該部分之間的厚度。
  2. 如請求項1所述之半導體裝置，其中該散熱板在該溝槽附近之剛性小於該散熱板除了該溝槽以外之部分之剛性。
  3. 如請求項1或2所述之半導體裝置，其中該溝槽是在該散熱板之朝向該基板之表面上。
  4. 如請求項3所述之半導體裝置，其進一步包括額外的溝槽，其是在該散熱板的該應力吸收部中。
  5. 如請求項1所述之半導體裝置，其中該散熱板之該突起部設置成於該半導體晶片之周圍突出，該散熱板之該應力吸收部配置於該突起部和該半導體晶片之間。
  6. 如請求項5所述之半導體裝置，其中該應力吸收部配置成相鄰於該突起部。
  7. 如請求項1所述之半導體裝置，其中該突起部經由導電性樹脂黏著於該基板。
  8. 如請求項1所述之半導體裝置，其中該散熱板之材質包含銅、鋁或鋁矽銅陶瓷。
  9. 如請求項1所述之半導體裝置，其中該散熱板之該突起部設置成於該半導體晶片之周圍突出，該散熱板之該應力吸收部配置於該突起部和該散熱板固定於該基板之該部分之間。
  10. 一種半導體裝置，包括：基板，該基板之表面包含絕緣材料；半導體晶片，以覆晶方式連接於該基板上；以及散熱板，經由熱介面材料黏著於該半導體晶片，且於該半導體晶片之外側固定至該基板，其中該散熱板具有突起部及應力吸收部，該突起部位於該散熱板黏著於該半導體晶片之部分和該散熱板固定於該基板之部分之間，該突起部朝向該基板突出且黏著於該基板；以及該應力吸收部包括孔，該孔是在該突起部和該半導體晶片之間的該散熱板中。
  11. 如請求項10所述之半導體裝置，其中該應力吸收部包括底孔，其在該散熱板之朝向該基板之表面中。
  12. 如請求項10所述之半導體裝置，其中該應力吸收部包括貫通孔，其在該散熱板之朝向該基板之表面中。
  13. 如請求項10所述之半導體裝置，其中該散熱板之材質包含 銅、鋁或鋁矽銅陶瓷。
  14. 如請求項10所述之半導體裝置，其中該突起部經由導電性樹脂黏著於該基板。
TW105103225A 2015-02-09 2016-02-02 半導體裝置 TWI709205B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2015-023153 2015-02-09
JP2015023153A JP6421050B2 (ja) 2015-02-09 2015-02-09 半導体装置

Publications (2)

Publication Number Publication Date
TW201640629A TW201640629A (zh) 2016-11-16
TWI709205B true TWI709205B (zh) 2020-11-01

Family

ID=56566128

Family Applications (3)

Application Number Title Priority Date Filing Date
TW105103225A TWI709205B (zh) 2015-02-09 2016-02-02 半導體裝置
TW109133883A TWI795677B (zh) 2015-02-09 2016-02-02 半導體裝置及製造其之方法
TW112105352A TW202329358A (zh) 2015-02-09 2016-02-02 半導體裝置及製造其之方法

Family Applications After (2)

Application Number Title Priority Date Filing Date
TW109133883A TWI795677B (zh) 2015-02-09 2016-02-02 半導體裝置及製造其之方法
TW112105352A TW202329358A (zh) 2015-02-09 2016-02-02 半導體裝置及製造其之方法

Country Status (5)

Country Link
US (3) US20160233141A1 (zh)
JP (1) JP6421050B2 (zh)
KR (3) KR102490814B1 (zh)
CN (2) CN111446217B (zh)
TW (3) TWI709205B (zh)

Families Citing this family (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI555147B (zh) * 2015-03-20 2016-10-21 矽品精密工業股份有限公司 散熱型封裝結構及其散熱件
WO2017094180A1 (ja) * 2015-12-04 2017-06-08 三菱電機株式会社 パワー半導体装置
US10607963B2 (en) * 2016-09-15 2020-03-31 International Business Machines Corporation Chip package for two-phase cooling and assembly process thereof
JP2018060986A (ja) * 2016-10-07 2018-04-12 株式会社ジェイデバイス 半導体装置
US10587044B2 (en) * 2016-10-24 2020-03-10 Anokiwave, Inc. Flip-chip beamforming integrated circuit with integral thermal mass
US20180166356A1 (en) * 2016-12-13 2018-06-14 Globalfoundries Inc. Fan-out circuit packaging with integrated lid
EP3340291A1 (en) * 2016-12-23 2018-06-27 Infineon Technologies AG Method for procuding an electronic module assembly and electronic module assembly
US10224262B2 (en) * 2017-05-12 2019-03-05 Globalfoundries Inc. Flexible heat spreader lid
US10319609B2 (en) 2017-06-21 2019-06-11 International Business Machines Corporation Adhesive-bonded thermal interface structures
JP6867243B2 (ja) * 2017-06-26 2021-04-28 新光電気工業株式会社 放熱板及びその製造方法と電子部品装置
US10002821B1 (en) 2017-09-29 2018-06-19 Infineon Technologies Ag Semiconductor chip package comprising semiconductor chip and leadframe disposed between two substrates
WO2019116457A1 (ja) * 2017-12-13 2019-06-20 三菱電機株式会社 半導体装置及び電力変換装置
CN109950214A (zh) * 2017-12-20 2019-06-28 安世有限公司 芯片级封装半导体器件及其制造方法
DE102017223619B3 (de) 2017-12-21 2019-05-09 Robert Bosch Gmbh Steuergerät für eine elektrische Maschine
CN110473839A (zh) * 2018-05-11 2019-11-19 三星电子株式会社 半导体封装系统
KR102607055B1 (ko) * 2018-05-11 2023-11-30 삼성전자주식회사 반도체 패키지 시스템
US10991638B2 (en) * 2018-05-14 2021-04-27 Samsung Electronics Co., Ltd. Semiconductor package system
KR102607109B1 (ko) * 2018-05-14 2023-11-30 삼성전자주식회사 반도체 패키지 시스템
JP7127498B2 (ja) * 2018-11-09 2022-08-30 住友電装株式会社 放熱部材及び電気接続箱
WO2020206675A1 (en) * 2019-04-12 2020-10-15 Nokia Shanghai Bell Co., Ltd. Heat dissipation
US20210035921A1 (en) * 2019-07-30 2021-02-04 Intel Corporation Soldered metallic reservoirs for enhanced transient and steady-state thermal performance
US11637051B2 (en) * 2019-10-18 2023-04-25 Qualcomm Incorporated Integrated device coupled to a step heat sink configured to provide shielding
CN110798167A (zh) * 2019-11-25 2020-02-14 开元通信技术（厦门）有限公司 声波器件及其制作方法
JP2021099229A (ja) * 2019-12-20 2021-07-01 ソニーセミコンダクタソリューションズ株式会社 電位測定装置
EP3926669A3 (en) 2020-05-29 2022-05-11 Google LLC Methods and heat distribution devices for thermal management of chip assemblies
US11876345B2 (en) 2020-09-08 2024-01-16 Hewlett Packard Enterprise Development Lp Thermal management for hybrid lasers
DE102020212532A1 (de) 2020-10-05 2022-04-07 Robert Bosch Gesellschaft mit beschränkter Haftung Vorrichtung mit einem Bauelement, einem Kühlkörper und einer wärmeleitenden Schicht
FR3115653B1 (fr) * 2020-10-22 2022-09-09 Continental Automotive Gmbh Elément de boitier électronique comprenant un radiateur et procédé d’ajustement associé
US20220361338A1 (en) * 2021-05-07 2022-11-10 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package with stress reduction design and method for forming the same
JP7183354B1 (ja) * 2021-07-27 2022-12-05 三菱電機株式会社 半導体モジュール
US20230065147A1 (en) * 2021-08-30 2023-03-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and manufacturing method thereof
GB2611028A (en) * 2021-09-17 2023-03-29 Aptiv Tech Ltd A method of fitting a cooling device to a circuit board and a circuit board cooling device
CN113990809B (zh) * 2021-12-17 2022-04-29 中兴通讯股份有限公司 封装结构、电路板组件和电子设备
DE102022205647A1 (de) * 2022-06-02 2023-12-07 Continental Autonomous Mobility Germany GmbH Kühlanordnung, Steuereinrichtung, Kühlkörper sowie Herstellungsverfahren

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10125830A (ja) * 1996-10-24 1998-05-15 Hitachi Ltd 高周波モジュールおよびその製造方法
US5931222A (en) * 1995-11-30 1999-08-03 International Business Machines Coporation Adhesion promoting layer for bonding polymeric adhesive to metal and a heat sink assembly using same
US6472741B1 (en) * 2001-07-14 2002-10-29 Siliconware Precision Industries Co., Ltd. Thermally-enhanced stacked-die ball grid array semiconductor package and method of fabricating the same
TW200516736A (en) * 2003-11-05 2005-05-16 Siliconware Precision Industries Co Ltd Semiconductor package with heat sink
TW200623365A (en) * 2004-12-22 2006-07-01 Siliconware Precision Industries Co Ltd Heat dissipating semiconductor package and fabrication method thereof
US20110018125A1 (en) * 2009-07-21 2011-01-27 Stmicroelectronics Asia Pacific Pte Ltd (Singapore) Semiconductor package with a stiffening member supporting a thermal heat spreader
US20120182694A1 (en) * 2011-01-14 2012-07-19 Taiwan Semiconductor Manufacturing Company, Ltd. Lid Design for Reliability Enhancement in Flip Chip Package

Family Cites Families (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59231841A (ja) * 1983-06-14 1984-12-26 Mitsubishi Electric Corp 半導体装置
JP3419915B2 (ja) * 1994-11-17 2003-06-23 株式会社東芝 リードレスタイプ半導体モジュール
US6020221A (en) * 1996-12-12 2000-02-01 Lsi Logic Corporation Process for manufacturing a semiconductor device having a stiffener member
US6313521B1 (en) * 1998-11-04 2001-11-06 Nec Corporation Semiconductor device and method of manufacturing the same
JP4420538B2 (ja) * 1999-07-23 2010-02-24 アバゴ・テクノロジーズ・ワイヤレス・アイピー（シンガポール）プライベート・リミテッド ウェーハパッケージの製造方法
KR100446290B1 (ko) 2001-11-03 2004-09-01 삼성전자주식회사 댐을 포함하는 반도체 패키지 및 그 제조방법
US6504723B1 (en) * 2001-11-15 2003-01-07 Intel Corporation Electronic assembly having solder thermal interface between a die substrate and a heat spreader
US6775140B2 (en) * 2002-10-21 2004-08-10 St Assembly Test Services Ltd. Heat spreaders, heat spreader packages, and fabrication methods for use with flip chip semiconductor devices
TW578284B (en) * 2002-12-24 2004-03-01 Advanced Semiconductor Eng Heat separator for chip package and the bonding method thereof
TWI315094B (en) * 2003-04-25 2009-09-21 Advanced Semiconductor Eng Flip chip package
US6906413B2 (en) * 2003-05-30 2005-06-14 Honeywell International Inc. Integrated heat spreader lid
JP4469563B2 (ja) * 2003-06-05 2010-05-26 株式会社ソニー・コンピュータエンタテインメント 電子機器、電磁波放射抑制部材
CN101111935B (zh) * 2005-01-25 2011-02-02 富士通株式会社 半导体装置
US7250576B2 (en) * 2005-05-19 2007-07-31 International Business Machines Corporation Chip package having chip extension and method
US7439617B2 (en) * 2006-06-30 2008-10-21 Intel Corporation Capillary underflow integral heat spreader
US20080128897A1 (en) * 2006-12-05 2008-06-05 Tong Wa Chao Heat spreader for a multi-chip package
JP2008305958A (ja) * 2007-06-07 2008-12-18 Fujitsu Microelectronics Ltd 半導体装置
CN201111935Y (zh) 2007-09-12 2008-09-10 昆山致桥电子商业有限公司 一种抽拉式屏幕
US9147649B2 (en) * 2008-01-24 2015-09-29 Infineon Technologies Ag Multi-chip module
US7619308B1 (en) * 2008-05-02 2009-11-17 Sun Microsystems, Inc. Multi-lid semiconductor package
US7928562B2 (en) * 2008-07-22 2011-04-19 International Business Machines Corporation Segmentation of a die stack for 3D packaging thermal management
JP5431793B2 (ja) * 2009-05-29 2014-03-05 新光電気工業株式会社 放熱部品、電子部品装置及び電子部品装置の製造方法
JP5733893B2 (ja) * 2009-12-22 2015-06-10 新光電気工業株式会社 電子部品装置
CN201708146U (zh) * 2010-05-26 2011-01-12 比亚迪股份有限公司 一种散热装置及具有该散热装置的半导体模块
JP2012033559A (ja) 2010-07-28 2012-02-16 J Devices:Kk 半導体装置
JP5588895B2 (ja) * 2011-02-28 2014-09-10 日立オートモティブシステムズ株式会社 パワー半導体モジュール，パワー半導体モジュールの製造方法及び電力変換装置
US9887144B2 (en) * 2011-09-08 2018-02-06 Taiwan Semiconductor Manufacturing Company, Ltd. Ring structure for chip packaging
US20130119529A1 (en) * 2011-11-15 2013-05-16 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having lid structure and method of making same
US20150129189A1 (en) * 2012-02-09 2015-05-14 Nokia Solutions And Networks Oy Method and Apparatus for Reducing the Mechanical Stress when Mounting Assemblies with Thermal Pads
JP5928222B2 (ja) * 2012-07-30 2016-06-01 株式会社ソシオネクスト 半導体装置および半導体装置の製造方法
JP5935598B2 (ja) * 2012-08-27 2016-06-15 株式会社デンソー 半導体装置
US9041192B2 (en) * 2012-08-29 2015-05-26 Broadcom Corporation Hybrid thermal interface material for IC packages with integrated heat spreader
US8921994B2 (en) * 2012-09-14 2014-12-30 Freescale Semiconductor, Inc. Thermally enhanced package with lid heat spreader
US20140091461A1 (en) * 2012-09-30 2014-04-03 Yuci Shen Die cap for use with flip chip package
US9136159B2 (en) * 2012-11-15 2015-09-15 Amkor Technology, Inc. Method and system for a semiconductor for device package with a die-to-packaging substrate first bond
JP6056490B2 (ja) * 2013-01-15 2017-01-11 株式会社ソシオネクスト 半導体装置とその製造方法
JP6045709B2 (ja) * 2013-09-04 2016-12-14 三菱電機株式会社 半導体モジュール及びインバータ装置
US9437519B2 (en) * 2014-02-25 2016-09-06 International Business Machines Corporation Tim strain mitigation in electronic modules
JP2015216199A (ja) * 2014-05-09 2015-12-03 新光電気工業株式会社 半導体装置、熱伝導部材及び半導体装置の製造方法
JP6314731B2 (ja) * 2014-08-01 2018-04-25 株式会社ソシオネクスト 半導体装置及び半導体装置の製造方法
US9418909B1 (en) * 2015-08-06 2016-08-16 Xilinx, Inc. Stacked silicon package assembly having enhanced lid adhesion

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5931222A (en) * 1995-11-30 1999-08-03 International Business Machines Coporation Adhesion promoting layer for bonding polymeric adhesive to metal and a heat sink assembly using same
JPH10125830A (ja) * 1996-10-24 1998-05-15 Hitachi Ltd 高周波モジュールおよびその製造方法
US6472741B1 (en) * 2001-07-14 2002-10-29 Siliconware Precision Industries Co., Ltd. Thermally-enhanced stacked-die ball grid array semiconductor package and method of fabricating the same
TW200516736A (en) * 2003-11-05 2005-05-16 Siliconware Precision Industries Co Ltd Semiconductor package with heat sink
TW200623365A (en) * 2004-12-22 2006-07-01 Siliconware Precision Industries Co Ltd Heat dissipating semiconductor package and fabrication method thereof
US20110018125A1 (en) * 2009-07-21 2011-01-27 Stmicroelectronics Asia Pacific Pte Ltd (Singapore) Semiconductor package with a stiffening member supporting a thermal heat spreader
US20120182694A1 (en) * 2011-01-14 2012-07-19 Taiwan Semiconductor Manufacturing Company, Ltd. Lid Design for Reliability Enhancement in Flip Chip Package

Also Published As

Publication number Publication date
CN111446217A (zh) 2020-07-24
US20200035582A1 (en) 2020-01-30
TWI795677B (zh) 2023-03-11
KR20160098046A (ko) 2016-08-18
JP2016146427A (ja) 2016-08-12
CN105870080B (zh) 2020-05-19
TW202329358A (zh) 2023-07-16
US20230111868A1 (en) 2023-04-13
KR20230016237A (ko) 2023-02-01
US11488886B2 (en) 2022-11-01
US20160233141A1 (en) 2016-08-11
CN105870080A (zh) 2016-08-17
TW201640629A (zh) 2016-11-16
KR20230169877A (ko) 2023-12-18
KR102490814B1 (ko) 2023-01-20
JP6421050B2 (ja) 2018-11-07
CN111446217B (zh) 2024-02-09
KR102608133B1 (ko) 2023-11-30
TW202107651A (zh) 2021-02-16

Similar Documents

Publication Publication Date Title
TWI709205B (zh) 半導體裝置
KR101332866B1 (ko) 반도체 장치
TWI584428B (zh) 降低封裝翹曲之散熱型半導體封裝構造
TWI555147B (zh) 散熱型封裝結構及其散熱件
US9559026B2 (en) Semiconductor package having a multi-layered base
US20230238302A1 (en) Semiconductor package having liquid-cooling lid
JP2016096329A (ja) 複数の光素子からの熱除去
JP2007142097A (ja) 半導体装置
JP2012015225A (ja) 半導体装置
TWI460831B (zh) 電子組裝體
TWI509756B (zh) 薄膜覆晶封裝結構
TWI449138B (zh) 封裝載板
TWI629755B (zh) 大面積半導體晶片用的低熱應力封裝體、半導體裝置及減少半導體裝置熱應力的方法
US11114387B2 (en) Electronic packaging structure
JP2013012570A (ja) 半導体装置および半導体装置の製造方法
TWI701747B (zh) 半導體裝置及其製造方法
US20180233477A1 (en) Electronic packaging structure
JP6527777B2 (ja) 半導体装置及びそれを有する実装基板
JP2016103569A (ja) 半導体素子の実装構造
TW202240813A (zh) 半導體裝置及其製造方法
JP2018137406A (ja) 電子機器及び電子機器の製造方法
TW201820572A (zh) 晶片封裝結構及其製造方法
JP2017028183A (ja) 半導体素子の実装構造