TWI449138B - 封裝載板 - Google Patents
封裝載板 Download PDFInfo
- Publication number
- TWI449138B TWI449138B TW100101977A TW100101977A TWI449138B TW I449138 B TWI449138 B TW I449138B TW 100101977 A TW100101977 A TW 100101977A TW 100101977 A TW100101977 A TW 100101977A TW I449138 B TWI449138 B TW I449138B
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- Prior art keywords
- layer
- substrate
- high thermal
- package carrier
- insulating
- Prior art date
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- 239000010410 layer Substances 0.000 claims description 138
- 239000000758 substrate Substances 0.000 claims description 58
- 229910052751 metal Inorganic materials 0.000 claims description 23
- 239000002184 metal Substances 0.000 claims description 23
- 239000011810 insulating material Substances 0.000 claims description 21
- 238000010438 heat treatment Methods 0.000 claims description 16
- 238000009413 insulation Methods 0.000 claims description 9
- 239000012790 adhesive layer Substances 0.000 claims description 8
- 229910000679 solder Inorganic materials 0.000 claims description 6
- 229910010293 ceramic material Inorganic materials 0.000 claims description 3
- 239000006023 eutectic alloy Substances 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 description 8
- 239000008393 encapsulating agent Substances 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- 238000005245 sintering Methods 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000035882 stress Effects 0.000 description 3
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000005187 foaming Methods 0.000 description 1
- 229910002804 graphite Inorganic materials 0.000 description 1
- 239000010439 graphite Substances 0.000 description 1
- 238000007731 hot pressing Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052755 nonmetal Inorganic materials 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
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- H—ELECTRICITY
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/44—Manufacturing insulated metal core circuits or other insulated electrically conductive core circuits
- H05K3/445—Manufacturing insulated metal core circuits or other insulated electrically conductive core circuits having insulated holes or insulated via connections through the metal core
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
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- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3731—Ceramic materials or glass
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3736—Metallic materials
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
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- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/64—Heat extraction or cooling elements
- H01L33/641—Heat extraction or cooling elements characterized by the materials
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- H05K2201/06—Thermal details
- H05K2201/068—Thermal details wherein the coefficient of thermal expansion is important
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
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- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
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- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Surface Heating Bodies (AREA)
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Description
本發明是有關於一種封裝載板,且特別是有關於一種高導熱需求之封裝基板。
晶片封裝的目的是提供晶片適當的訊號路徑、導熱路徑及結構保護。傳統的打線(wire bonding)技術通常採用導線架(leadframe)作為晶片的承載器(carrier)。隨著晶片的接點密度逐漸提高,導線架已無法再提供更高的接點密度,故可利用具有高接點密度的封裝基板(package substrate)來取代之,並藉由金屬導線或凸塊(bump)等導電媒體,將晶片封裝至封裝基板上。
在習知之封裝製程中,由於晶片的熱膨脹係數與封裝基板的熱膨脹係數的差異甚大,因此晶片無法與封裝基板形成良好的接合,使得晶片或位於晶片與封裝基板之間的凸塊可能自封裝基板上剝離。此外,隨著積體電路之積集度的增加,由於晶片與封裝基板之間的熱膨脹係數不匹配(mismatch),其所產生的熱應力(thermal stress)與翹曲(warpage)的現象也日漸嚴重,而此結果將導致晶片與封裝基板之間的可靠度(reliability)下降。
本發明提供一種封裝載板,可有效降低承載一發熱元件時之熱膨脹差異,可提高使用的可靠度。
本發明提出一種封裝載板,適於承載一發熱元件。封裝載板包括一基材、一高導熱絕緣結構以及一圖案化導電層。基材具有一表面。高導熱絕緣結構配置於基材的部分表面上。圖案化導電層配置於基材的部分表面上,且部分圖案化導電層覆蓋高導熱絕緣結構。發熱元件適於配置於位於高導熱絕緣結構上的圖案化導電層上,且高導熱絕緣結構的熱膨脹係數介於基材的熱膨脹係數與發熱元件的熱膨脹係數之間。
在本發明之一實施例中,上述之基材的表面具有一凹穴,而高導熱絕緣結構位於凹穴內,且突出於基材的表面。
在本發明之一實施例中,上述之封裝載板更包括一輔助介質層,高導熱絕緣結構包括一第一金屬層、一第二金屬層以及一高導熱絕緣材料層。高導熱絕緣結構透過輔助介質層而固定於凹穴內。高導熱絕緣材料層配置於第一金屬層與第二金屬層之間。第二金屬層位於高導熱絕緣材料層與圖案化導電層之間。第一金屬層位於高導熱絕緣材料層與輔助介質層之間。
在本發明之一實施例中,上述之輔助介質層包括一導熱膠層、一銲料層或一共熔合金層(eutectic)。
在本發明之一實施例中,上述之高導熱絕緣結構包括一陶瓷材料層、一高導熱膠層或一高導熱絕緣材料層。
在本發明之一實施例中,上述之封裝載板更包括一絕緣通孔結構,基材具有一貫孔。絕緣通孔結構配置於貫孔內。絕緣通孔結構包括一絕緣層以及一導電層。絕緣層覆蓋貫孔的內壁,而導電層覆蓋絕緣層且延伸至絕緣層的相對兩表面,並與圖案化導電層電性絕緣。圖案化導電層更配置於基材相對於表面的另一表面上。
在本發明之一實施例中,上述之發熱元件包括一電子晶片或一光電元件。
在本發明之一實施例中,上述之發熱元件透過打線接合而電性連接至圖案化導電層。
在本發明之一實施例中,上述之發熱元件透過覆晶接合而電性連接至圖案化導電層。
在本發明之一實施例中,上述之發熱元件為一晶片封裝體,而晶片封裝體包括一晶片以及一承載板,且晶片配置於承載板上。
基於上述,由於本發明之高導熱絕緣結構的熱膨脹係數是介於基材的熱膨脹係數與發熱元件的熱膨脹係數之間。因此,發熱元件、高導熱絕緣結構以及基材彼此之間的熱膨脹係數差異可漸近式的逐漸減少。如此一來,可避免發熱元件、高導熱絕緣結構以及基材之間因熱膨脹係數差異過大而導致相互之間的應力增加,可有效防止發熱元件剝落、壞損的現象產生,進而可提高封裝載板的使用可靠度。
為讓本發明之上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。
圖1為本發明之一實施例之一種封裝載板承載一發熱元件的剖面示意圖。請參考圖1,在本實施例中,封裝載板100a適於承載一發熱元件10,而發熱元件10例如是一電子晶片或一光電元件,但並不以此為限。其中,電子晶片可以是一積體電路晶片,其例如為一繪圖晶片、一記憶體晶片、一半導體晶片等單一晶片或是一晶片模組。光電元件例如是一發光二極體(LED)、一雷射二極體或一氣體放電光源等。當然,發熱元件10也可以是任何發熱之物件如運轉中之馬達或加熱器等。在此,發熱元件10是以一半導體晶片作為舉例說明。
詳細來說,封裝載板100a包括一基材110、一高導熱絕緣結構120a以及一圖案化導電層130。基材110具有一表面112a、相對於表面112a的一另一表面112b以及一凹穴114,其中基材110的材質包括具有高導熱性的金屬,例如是銅或鋁,合金,例如是銅合金或鋁合金,或非金屬,但不以此為限。其中,基材110可快速傳導發熱元件10所產生的熱能,以降低發熱元件10的工作溫度。
高導熱絕緣結構120a配置於基材110的凹穴114內且突出於基材110的表面112a,其中高導熱絕緣結構120a例如是先透過印刷的方式塗佈或填充於基材110的凹穴114內,而後再經由燒結所形成。高導熱絕緣結構120a例如是一陶瓷材料層、一高導熱膠層或一高導熱絕緣材料層,其中高導熱膠層大部分是由環氧樹脂(epoxy)混合陶瓷粉末,例如是氧化鋁(Al2O3)、氮化鋁(AlN)或氮化硼(BN)所製成,而高導熱絶緣材料層例如是石墨、碳、氧化鋁(Al2O3)或氮化鋁(AlN)等材料以鍍膜、發泡、燒結或熱壓等方式所製成。此外,若高導熱絕緣結構120a為高導熱膠層時,其厚度例如是介於2毫米至8毫米之間。若高導熱絕緣結構120a為高導熱絶緣材料層時,其厚度例如是介於20毫米至30毫米之間。
圖案化導電層130配置於基材110的部分表面112a以及相對表面112a的另一表面112b上,且部分圖案化導電層130完全覆蓋高導熱絕緣結構120a。也就是說,本實施例之封裝載板100a實質上為一雙面線路承載板。此外,發熱元件10適於透過一銲料層40而配置於位於高導熱絕緣結構120a上的圖案化導電層130上。特別是,高導熱絕緣結構120a的熱膨脹係數介於基材110的熱膨脹係數與發熱元件10的熱膨脹係數之間。
另外,本實施例之封裝載板100a可更包括一絕緣通孔結構170,而基材110更具有一貫孔116。絕緣通孔結構170配置於貫孔116內,且絕緣通孔結構170是由一絕緣層172以及一導電層174所構成。其中,絕緣層172覆蓋貫孔116的內壁,而導電層174覆蓋絕緣層172且延伸至絕緣層172的相對兩表面,並與圖案化導電層130電性絕緣。特別是,在本實施例中導電層174與圖案化導電層130例如是由同一道製層所形成的膜層,而發熱元件10(例如是半導體晶片)例如是透過多條銲線30以打線接合的方式而電性連接至圖案化導電層130以及導電層174上。此外,亦可藉由一封裝膠體50來包覆發熱元件10、這些銲線30以及部分封裝載板100a,用以保護發熱元件10與這些銲線30及封裝載板100a之間的電性連接關係。
由於本實施例之高導熱絕緣結構120a的熱膨脹係數是介於基材110的熱膨脹係數與發熱元件10的熱膨脹係數之間。因此,發熱元件10、高導熱絕緣結構120a以及基材110彼此之間的熱膨脹係數差異可漸近式的逐漸減少。如此一來,可避免發熱元件10、高導熱絕緣結構120a以及基材110之間因熱膨脹係數差異過大而導致相互之間的應力增加,可有效防止發熱元件10剝落、壞損的現象產生,進而可提高封裝載板100a的使用可靠度。
值得一提的是,本發明並不限定發熱元件10與封裝載板100a的接合形態以及發熱元件10的型態,雖然此處所提及的發熱元件10具體化是透過打線接合而電性連接至封裝載板100a的圖案化導電層130以及導電層174。但,於其他實施例中,請參考圖2,發熱元件10亦可透過多個凸塊60以覆晶接合的方式而電性連接至位於高導熱絕緣結構120a上之圖案化導電層130上;或者是,請參考圖3,發熱元件10為一晶片封裝體20,而晶片封裝體20例如是由一晶片22、一承載板24以及一封裝膠體26所組成,其中晶片22配置於承載板24上且透過多條銲線32而電性連接至承載板24,而封裝膠體26包覆晶片22、這些銲線32以及部分承載板24,以保護晶片10、這些銲線32以及承載板24之間的電性連接關係。上述之發熱元件10與封裝載板100a的接合形態以及發熱元件10的形態僅為舉例說明之用,並非用以限定本發明。
再者,本發明亦不限定封裝載板100a的形態,雖然此處所提及的封裝載板100a為一雙面線路承載板,且基材110具有凹穴114。但,於其他實施例中,請參考圖4,封裝載板100b亦可為一單面線路承載板,且基材110b不具有凹穴,其中高導熱絕緣結構120b直接配置於基材110b的表面112a’,且圖案化導電層130b僅配置於基材110b的部分表面112a’上且部分圖案化導電層130b覆蓋高導熱絕緣結構120b。
此外,請參考圖5,封裝載板100c亦可更包括一輔助介質層160,而高導熱絕緣結構120c包括一第一金屬層122、一第二金屬層124以及一高導熱絕緣材料層126,其中高導熱絕緣結構120c透過輔助介質層160而固定於凹穴114內。高導熱絕緣材料層126配置於第一金屬層122與第二金屬層124之間,第二金屬層124位於高導熱絕緣材料層126與圖案化導電層130之間,而第一金屬層122位於高導熱絕緣材料層126與輔助介質層160之間。特別是,圖1所提及之高導熱絕緣結構120a具體化是先透過印刷而後燒結的方式所構成,但於圖5之實施例中,封裝載板100c的高導熱絕緣結構120c的形成方式為先將第一金屬層122以及第二金屬層124堆疊於高導熱絕緣材料層126上,再經由輔助介質層160以表面黏著的方式配置於凹穴114內。此外,輔助介質層160例如是一導熱膠層、一銲料層或一共熔合金層(eutectic)。因此,圖1所繪示之封裝載板100a僅為舉例說明,並非用以限定本發明。
此外,於其他未繪示的實施例中,發熱元件10亦可選擇性地配置於如前述實施例所提及之不具凹穴114之基材110b且為單面線路結構之封裝載板100b或具有表面黏著型之高導熱絕緣結構120c之封裝載板100c,本領域的技術人員當可參照前述實施例的說明,依據實際需求,而選用前述構件,以達到所需的技術效果。
以上僅介紹本發明之封裝載板100a、100b、100c的結構,並未介紹本發明之封裝基板100a、100b、100c的製作方法。對此,以下將以另一實施例配合圖6A至圖6G來詳細說明上述實施例之封裝載板100a的製作方法。在此必須說明的是,下述實施例沿用前述實施例的元件標號與部分內容,其中採用相同的標號來表示相同或近似的元件,並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例,下述實施例不再重複贅述。
圖6A至圖6G為本發明之一實施例之一種封裝載板的製作方法的剖面示意圖。請先參考圖6A,依照本實施例的封裝載板100a的製作方法,首先,提供一基材110,其中基材110具有一表面112a以及一相對於表面112a的另一表面112b。
接著,請參考圖6B,透過沖切、雷射或蝕刻技術來形成一凹穴114於基材110的表面112a上。在此必須說明的是,於封裝載板100b的製作中,此形成凹穴114的步驟省略。亦即,此步驟為選擇性的製程步驟,可依據使用者的需求而自行選擇是否進行此步驟。
接著,請參考圖6C,先透過印刷的方式塗佈或填充高導熱絕緣材料於基材110的凹穴114內,而後再經由燒結而形成高導熱絕緣結構120a。之後,形成一貫穿基材110之表面112a與另一表面112b的貫孔116。在此必須說明的是,於封裝載板100b的製作中,此形成貫孔116的步驟省略。亦即,此步驟為選擇性的製程步驟,可依據使用者的需求而自行選擇是否進行此步驟。
接著,請參考圖6D,填充一絕緣材料層172a於貫孔116內,其中絕緣材料層172a填滿貫孔116。
接著,請參考圖6E,形成一貫穿絕緣材料層172a的貫孔172b,以定義出一絕緣層172。
然後,請參考圖6E,形成一導電層130a於基材110的表面112a與另一表面112b,其中導電層130a覆蓋高導熱絕緣結構120a以及於絕緣層172(意即覆蓋絕緣材料層172a之貫孔172b的內壁)。
最後,請參考圖6F,圖案化導電層130a,以形成一圖案化導電層130。其中,圖案化導電層130的一部分配置於基材110的部分表面112a以及相對表面112a的另一表面112b上,且部分圖案化導電層130覆蓋高導熱絕緣結構120a。圖案化導電層130的另一部分(意即導電層174)覆蓋絕緣層172且延伸至絕緣層172的相對兩表面,並與圖案化導電層130電性絕緣。至此,已大致完成封裝載板100a的製作。
綜上所述,由於本發明之高導熱絕緣結構的熱膨脹係數是介於基材的熱膨脹係數與發熱元件的熱膨脹係數之間。因此,發熱元件、高導熱絕緣結構以及基材彼此之間的熱膨脹係數差異可漸近式的逐漸減少。如此一來,可避免發熱元件、高導熱絕緣結構以及基材之間因熱膨脹係數差異過大而導致相互之間的應力增加,可有效防止發熱元件剝落、壞損的現象產生,進而可提高封裝載板的使用可靠度。
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作些許之更動與潤飾,故本發明之保護範圍當視後附之申請專利範圍所界定者為準。
10...發熱元件
20...晶片封裝體
22...晶片
24...承載板
26、50...封裝膠體
30、32...銲線
40...銲料層
60...凸塊
100a、100b、100c...封裝載板
110、110b...基材
112a、112a’...表面
112b、112b’...另一表面
114...凹穴
116、172b...貫孔
120a、120b、120c...高導熱絕緣結構
122...第一金屬層
124...第二金屬層
126...高導熱絕緣材料層
130、130b‧‧‧圖案化導電層
130a、174‧‧‧導電層
160‧‧‧輔助介質層
170‧‧‧絕緣通孔結構
172‧‧‧絕緣層
172a‧‧‧絕緣材料層
圖1為本發明之一實施例之一種封裝載板承載一發熱元件的剖面示意圖。
圖2為本發明之另一實施例之一種封裝載板承載一發熱元件的剖面示意圖。
圖3為本發明之再一實施例之一種封裝載板承載一發熱元件的剖面示意圖。
圖4為本發明之一實施例之一種封裝載板的剖面示意圖。
圖5為本發明之另一實施例之一種封裝載板的剖面示意圖
圖6A至圖6G為本發明之一實施例之一種封裝載板的製作方法的剖面示意圖。
10...發熱元件
30...銲線
40...銲料層
50...封裝膠體
100a...封裝載板
110...基材
112a...表面
112b...另一表面
114...凹穴
116...貫孔
120a...高導熱絕緣結構
130...圖案化導電層
170...絕緣通孔結構
172...絕緣層
174...導電層
Claims (9)
- 一種封裝載板,適於承載一發熱元件,該封裝載板包括:一基材,具有一表面;一高導熱絕緣結構,配置於該基材的部分該表面上;一圖案化導電層,配置於該基材的部分該表面上,且部分該圖案化導電層覆蓋該高導熱絕緣結構,其中該發熱元件適於配置於位於該高導熱絕緣結構上的該圖案化導電層上,且該高導熱絕緣結構的熱膨脹係數介於該基材的熱膨脹係數與該發熱元件的熱膨脹係數之間;以及一絕緣通孔結構,該基材具有一貫孔,該絕緣通孔結構配置於該貫孔內,其中該絕緣通孔結構包括一絕緣層以及一導電層,該絕緣層覆蓋該貫孔的內壁,該導電層覆蓋該絕緣層且延伸至該絕緣層的相對兩表面,並與該圖案化導電層電性絕緣,而該圖案化導電層更配置於該基材相對於該表面的另一表面上。
- 如申請專利範圍第1項所述之封裝載板,其中該基材的該表面具有一凹穴,而該高導熱絕緣結構位於該凹穴內,且突出於該基材的該表面。
- 如申請專利範圍第2項所述之封裝載板,更包括一輔助介質層,該高導熱絕緣結構包括一第一金屬層、一第二金屬層以及一高導熱絕緣材料層,該高導熱絕緣結構透過該輔助介質層而固定於該凹穴內,其中該高導熱絕緣材料層配置於該第一金屬層與該第二金屬層之間,該第二金 屬層位於該高導熱絕緣材料層與該圖案化導電層之間,而該第一金屬層位於該高導熱絕緣材料層與該輔助介質層之間。
- 如申請專利範圍第3項所述之封裝載板,其中該輔助介質層包括一導熱膠層、一銲料層或一共熔合金層(eutectic)。
- 如申請專利範圍第1項所述之封裝載板,其中該高導熱絕緣結構包括一陶瓷材料層或一高導熱膠層。
- 如申請專利範圍第1項所述之封裝載板,其中該發熱元件包括一電子晶片或一光電元件。
- 如申請專利範圍第1項所述之封裝載板,其中該發熱元件透過打線接合而電性連接至該圖案化導電層。
- 如申請專利範圍第1項所述之封裝載板,其中該發熱元件透過覆晶接合而電性連接至該圖案化導電層。
- 如申請專利範圍第1項所述之封裝載板,其中該發熱元件為一晶片封裝體,而該晶片封裝體包括一晶片以及一承載板,且該晶片配置於該承載板上。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW100101977A TWI449138B (zh) | 2011-01-19 | 2011-01-19 | 封裝載板 |
US13/037,377 US20120181066A1 (en) | 2011-01-19 | 2011-03-01 | Package carrier |
CN201110071472.2A CN102610586B (zh) | 2011-01-19 | 2011-03-24 | 封装载板 |
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TW100101977A TWI449138B (zh) | 2011-01-19 | 2011-01-19 | 封裝載板 |
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JP6575321B2 (ja) * | 2015-11-20 | 2019-09-18 | 住友ベークライト株式会社 | 樹脂組成物、回路基板、発熱体搭載基板および回路基板の製造方法 |
CN105914283B (zh) * | 2016-04-18 | 2019-01-11 | 乐健科技(珠海)有限公司 | 散热基板、功率模块及制备散热基板的方法 |
CN110265365A (zh) * | 2019-06-12 | 2019-09-20 | 江门建滔电子发展有限公司 | 一种高耐热封装载板 |
CN113460948A (zh) * | 2021-06-30 | 2021-10-01 | 西人马联合测控(泉州)科技有限公司 | 一种芯片封装结构和芯片封装方法 |
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US20040038471A1 (en) * | 2000-09-06 | 2004-02-26 | Noriaki Sakamoto | Semiconductor device and method of manufacturing the same |
TW200826312A (en) * | 2006-12-06 | 2008-06-16 | Chipmos Technologies Inc | Light emitting chip package and light source module |
CN101846247A (zh) * | 2005-12-22 | 2010-09-29 | 松下电工株式会社 | 具有led的照明器具 |
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JPH0377393A (ja) * | 1989-08-21 | 1991-04-02 | Ok Print:Kk | 配線基板装置 |
JP3445511B2 (ja) * | 1998-12-10 | 2003-09-08 | 株式会社東芝 | 絶縁基板、その製造方法およびそれを用いた半導体装置 |
JP2002076193A (ja) * | 2000-08-30 | 2002-03-15 | Kyocera Corp | 半導体素子収納用パッケージおよびパッケージ実装基板 |
JP2002203942A (ja) * | 2000-12-28 | 2002-07-19 | Fuji Electric Co Ltd | パワー半導体モジュール |
JP2006024653A (ja) * | 2004-07-06 | 2006-01-26 | Tokyo Electron Ltd | 貫通基板および貫通基板の製造方法 |
US20060097385A1 (en) * | 2004-10-25 | 2006-05-11 | Negley Gerald H | Solid metal block semiconductor light emitting device mounting substrates and packages including cavities and heat sinks, and methods of packaging same |
CN201017879Y (zh) * | 2007-02-15 | 2008-02-06 | 威盛电子股份有限公司 | 芯片组装体与芯片封装体 |
US8269336B2 (en) * | 2008-03-25 | 2012-09-18 | Bridge Semiconductor Corporation | Semiconductor chip assembly with post/base heat spreader and signal post |
CN101630668B (zh) * | 2008-07-15 | 2011-09-28 | 展晶科技(深圳)有限公司 | 化合物半导体元件及光电元件的封装结构及其制造方法 |
CN101908510B (zh) * | 2009-06-03 | 2012-05-09 | 钰桥半导体股份有限公司 | 具有散热封装结构的半导体装置及其制作方法 |
US8324653B1 (en) * | 2009-08-06 | 2012-12-04 | Bridge Semiconductor Corporation | Semiconductor chip assembly with ceramic/metal substrate |
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- 2011-01-19 TW TW100101977A patent/TWI449138B/zh not_active IP Right Cessation
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US20040038471A1 (en) * | 2000-09-06 | 2004-02-26 | Noriaki Sakamoto | Semiconductor device and method of manufacturing the same |
CN101846247A (zh) * | 2005-12-22 | 2010-09-29 | 松下电工株式会社 | 具有led的照明器具 |
TW200826312A (en) * | 2006-12-06 | 2008-06-16 | Chipmos Technologies Inc | Light emitting chip package and light source module |
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CN102610586B (zh) | 2015-09-02 |
US20120181066A1 (en) | 2012-07-19 |
CN102610586A (zh) | 2012-07-25 |
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