CN102610586A - 封装载板 - Google Patents
封装载板 Download PDFInfo
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- CN102610586A CN102610586A CN2011100714722A CN201110071472A CN102610586A CN 102610586 A CN102610586 A CN 102610586A CN 2011100714722 A CN2011100714722 A CN 2011100714722A CN 201110071472 A CN201110071472 A CN 201110071472A CN 102610586 A CN102610586 A CN 102610586A
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- 239000000463 material Substances 0.000 claims abstract description 52
- 229910052751 metal Inorganic materials 0.000 claims description 23
- 239000002184 metal Substances 0.000 claims description 23
- 239000011810 insulating material Substances 0.000 claims description 20
- 230000004888 barrier function Effects 0.000 claims description 17
- 230000000153 supplemental effect Effects 0.000 claims description 14
- 239000003292 glue Substances 0.000 claims description 5
- 229910000679 solder Inorganic materials 0.000 claims description 5
- 230000005496 eutectics Effects 0.000 claims description 4
- 229910010293 ceramic material Inorganic materials 0.000 claims description 3
- 239000000758 substrate Substances 0.000 abstract description 6
- 238000010438 heat treatment Methods 0.000 abstract description 4
- 238000004806 packaging method and process Methods 0.000 description 12
- 238000004519 manufacturing process Methods 0.000 description 8
- 238000000034 method Methods 0.000 description 7
- 239000000084 colloidal system Substances 0.000 description 4
- 239000012774 insulation material Substances 0.000 description 4
- 238000012856 packing Methods 0.000 description 4
- 238000005245 sintering Methods 0.000 description 4
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 3
- 238000007639 printing Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000035882 stress Effects 0.000 description 3
- 229910017083 AlN Inorganic materials 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000010339 dilation Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000005187 foaming Methods 0.000 description 1
- 229910002804 graphite Inorganic materials 0.000 description 1
- 239000010439 graphite Substances 0.000 description 1
- 238000007731 hot pressing Methods 0.000 description 1
- 229910052755 nonmetal Inorganic materials 0.000 description 1
- 230000037361 pathway Effects 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
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Abstract
本发明公开一种封装载板,其适于承载一发热元件。封装载板包括一基材、一高导热绝缘结构以及一图案化导电层。基材具有一表面。高导热绝缘结构配置于基材的部分表面上。图案化导电层配置于基材的部分表面上,且部分图案化导电层覆盖高导热绝缘结构。发热元件适于配置于位于高导热绝缘结构上的图案化导电层上。高导热绝缘结构的热膨胀系数介于基材的热膨胀系数与发热元件的热膨胀系数之间。
Description
技术领域
本发明涉及一种封装载板,且特别是涉及一种高导热需求的封装基板。
背景技术
芯片封装的目的是提供芯片适当的信号路径、导热路径及结构保护。传统的打线(wire bonding)技术通常采用导线架(leadframe)作为芯片的承载器(carrier)。随着芯片的接点密度逐渐提高,导线架已无法再提供更高的接点密度,故可利用具有高接点密度的封装基板(package substrate)来取代之,并通过金属导线或凸块(bump)等导电媒体,将芯片封装至封装基板上。
在现有的封装制作工艺中,由于芯片的热膨胀系数与封装基板的热膨胀系数的差异甚大,因此芯片无法与封装基板形成良好的接合,使得芯片或位于芯片与封装基板之间的凸块可能自封装基板上剥离。此外,随着集成电路的积成度的增加,由于芯片与封装基板之间的热膨胀系数不匹配(mismatch),其所产生的热应力(thermal stress)与翘曲(warpage)的现象也日渐严重,而此结果将导致芯片与封装基板之间的可靠度(reliability)下降。
发明内容
本发明的目的在于提供一种封装载板,可有效降低承载一发热元件时的热膨胀差异,可提高使用的可靠度。
本发明提出一种封装载板,适于承载一发热元件。封装载板包括一基材、一高导热绝缘结构以及一图案化导电层。基材具有一表面。高导热绝缘结构配置于基材的部分表面上。图案化导电层配置于基材的部分表面上,且部分图案化导电层覆盖高导热绝缘结构。发热元件适于配置于位于高导热绝缘结构上的图案化导电层上,且高导热绝缘结构的热膨胀系数介于基材的热膨胀系数与发热元件的热膨胀系数之间。
在本发明的一实施例中,上述的基材的表面具有一凹穴,而高导热绝缘结构位于凹穴内,且突出于基材的表面。
在本发明的一实施例中,上述的封装载板还包括辅助介质层,高导热绝缘结构包括一第一金属层、一第二金属层以及一高导热绝缘材料层。高导热绝缘结构通过辅助介质层而固定于凹穴内。高导热绝缘材料层配置于第一金属层与第二金属层之间。第二金属层位于高导热绝缘材料层与图案化导电层之间。第一金属层位于高导热绝缘材料层与辅助介质层之间。
在本发明的一实施例中,上述的辅助介质层包括一导热胶层、一焊料层或一共熔合金层(eutectic)。
在本发明的一实施例中,上述的高导热绝缘结构包括一陶瓷材料层、一高导热胶层或一高导热绝缘材料层。
在本发明的一实施例中,上述的封装载板更包括一绝缘通孔结构,基材具有一贯孔。绝缘通孔结构配置于贯孔内。绝缘通孔结构包括一绝缘层以及一导电层。绝缘层覆盖贯孔的内壁,而导电层覆盖绝缘层且延伸至绝缘层的相对两表面,并与图案化导电层电性绝缘。图案化导电层更配置于基材相对于表面的另一表面上。
在本发明的一实施例中,上述的发热元件包括一电子芯片或一光电元件。
在本发明的一实施例中,上述的发热元件通过打线接合而电连接至图案化导电层。
在本发明的一实施例中,上述的发热元件通过覆晶接合而电连接至图案化导电层。
在本发明的一实施例中,上述的发热元件为一芯片封装体,而芯片封装体包括一芯片以及一承载板,且芯片配置于承载板上。
基于上述,由于本发明的高导热绝缘结构的热膨胀系数是介于基材的热膨胀系数与发热元件的热膨胀系数之间。因此,发热元件、高导热绝缘结构以及基材彼此之间的热膨胀系数差异可渐近式的逐渐减少。如此一来,可避免发热元件、高导热绝缘结构以及基材之间因热膨胀系数差异过大而导致相互之间的应力增加,可有效防止发热元件剥落、坏损的现象产生,进而可提高封装载板的使用可靠度。
为让本发明的上述特征和优点能更明显易懂,下文特举实施例,并配合所附附图作详细说明如下。
附图说明
图1为本发明的一实施例的一种封装载板承载一发热元件的剖面示意图;
图2为本发明的另一实施例的一种封装载板承载一发热元件的剖面示意图;
图3为本发明的再一实施例的一种封装载板承载一发热元件的剖面示意图;
图4为本发明的一实施例的一种封装载板的剖面示意图;
图5为本发明的另一实施例的一种封装载板的剖面示意图;
图6A至图6G为本发明的一实施例的一种封装载板的制作方法的剖面示意图。
主要元件符号说明
10:发热元件
20:芯片封装体
22:芯片
24:承载板
26、50:封装胶体
30、32:焊线
40:焊料层
60:凸块
100a、100b、100c:封装载板
110、110b:基材
112a、112a’:表面
112b、112b’:另一表面
114:凹穴
116、172b:贯孔
120a、120b、120c:高导热绝缘结构
122:第一金属层
124:第二金属层
126:高导热绝缘材料层
130、130b:图案化导电层
130a、174:导电层
160:辅助介质层
170:绝缘通孔结构
172:绝缘层
172a:绝缘材料层
具体实施方式
图1为本发明的一实施例的一种封装载板承载一发热元件的剖面示意图。请参考图1,在本实施例中,封装载板100a适于承载一发热元件10,而发热元件10例如是一电子芯片或一光电元件,但并不以此为限。其中,电子芯片可以是一集成电路芯片,其例如为一绘图芯片、一存储器芯片、一半导体芯片等单一芯片或是一芯片模块。光电元件例如是一发光二极管(LED)、一激光二极管或一气体放电光源等。当然,发热元件10也可以是任何发热的物件如运转中的马达或加热器等。在此,发热元件10是以一半导体芯片作为举例说明。
详细来说,封装载板100a包括一基材110、一高导热绝缘结构120a以及一图案化导电层130。基材110具有一表面112a、相对于表面112a的一另一表面112b以及一凹穴114,其中基材110的材质包括具有高导热性的金属,例如是铜或铝,合金,例如是铜合金或铝合金,或非金属,但不以此为限。其中,基材110可快速传导发热元件10所产生的热能,以降低发热元件10的工作温度。
高导热绝缘结构120a配置于基材110的凹穴114内且突出于基材110的表面112a,其中高导热绝缘结构120a例如是先通过印刷的方式涂布或填充于基材110的凹穴114内,而后再经由烧结所形成。高导热绝缘结构120a例如是一陶瓷材料层、一高导热胶层或一高导热绝缘材料层,其中高导热胶层大部分是由环氧树脂(epoxy)混合陶瓷粉末,例如是氧化铝(Al2O3)、氮化铝(AlN)或氮化硼(BN)所制成,而高导热絶缘材料层例如是石墨、碳、氧化铝(Al2O3)或氮化铝(AlN)等材料以镀膜、发泡、烧结或热压等方式所制成。此外,若高导热绝缘结构120a为高导热胶层时,其厚度例如是介于2毫米至8毫米之间。若高导热绝缘结构120a为高导热絶缘材料层时,其厚度例如是介于20毫米至30毫米之间。
图案化导电层130配置于基材110的部分表面112a以及相对表面112a的另一表面112b上,且部分图案化导电层130完全覆盖高导热绝缘结构120a。也就是说,本实施例的封装载板100a实质上为一双面线路承载板。此外,发热元件10适于通过一焊料层40而配置于位于高导热绝缘结构120a上的图案化导电层130上。特别是,高导热绝缘结构120a的热膨胀系数介于基材110的热膨胀系数与发热元件10的热膨胀系数之间。
另外,本实施例的封装载板100a可更包括一绝缘通孔结构170,而基材110更具有一贯孔116。绝缘通孔结构170配置于贯孔116内,且绝缘通孔结构170是由一绝缘层172以及一导电层174所构成。其中,绝缘层172覆盖贯孔116的内壁,而导电层174覆盖绝缘层172且延伸至绝缘层172的相对两表面,并与图案化导电层130电性绝缘。特别是,在本实施例中导电层174与图案化导电层130例如是由同一道制层所形成的膜层,而发热元件10(例如是半导体芯片)例如是通过多条焊线30以打线接合的方式而电连接至图案化导电层130以及导电层174上。此外,也可通过一封装胶体50来包覆发热元件10、这些焊线30以及部分封装载板100a,用以保护发热元件10与这些焊线30及封装载板100a之间的电连接关系。
由于本实施例的高导热绝缘结构120a的热膨胀系数是介于基材110的热膨胀系数与发热元件10的热膨胀系数之间。因此,发热元件10、高导热绝缘结构120a以及基材110彼此之间的热膨胀系数差异可渐近式的逐渐减少。如此一来,可避免发热元件10、高导热绝缘结构120a以及基材110之间因热膨胀系数差异过大而导致相互之间的应力增加,可有效防止发热元件10剥落、坏损的现象产生,进而可提高封装载板100a的使用可靠度。
值得一提的是,本发明并不限定发热元件10与封装载板100a的接合形态以及发热元件10的型态,虽然此处所提及的发热元件10具体化是通过打线接合而电连接至封装载板100a的图案化导电层130以及导电层174。但,在其他实施例中,请参考图2,发热元件10也可通过多个凸块60以覆晶接合的方式而电连接至位于高导热绝缘结构120a上的图案化导电层130上;或者是,请参考图3,发热元件10为一芯片封装体20,而芯片封装体20例如是由一芯片22、一承载板24以及一封装胶体26所组成,其中芯片22配置于承载板24上且通过多条焊线32而电连接至承载板24,而封装胶体26包覆芯片22、这些焊线32以及部分承载板24,以保护芯片10、这些焊线32以及承载板24之间的电连接关系。上述的发热元件10与封装载板100a的接合形态以及发热元件10的形态仅为举例说明之用,并非用以限定本发明。
再者,本发明也不限定封装载板100a的形态,虽然此处所提及的封装载板100a为一双面线路承载板,且基材110具有凹穴114。但,在其他实施例中,请参考图4,封装载板100b也可为一单面线路承载板,且基材110b不具有凹穴,其中高导热绝缘结构120b直接配置于基材110b的表面112a’,且图案化导电层130b仅配置于基材110b的部分表面112a’上且部分图案化导电层130b覆盖高导热绝缘结构120b。
此外,请参考图5,封装载板100c也可更包括一辅助介质层160,而高导热绝缘结构120c包括一第一金属层122、一第二金属层124以及一高导热绝缘材料层126,其中高导热绝缘结构120c通过辅助介质层160而固定于凹穴114内。高导热绝缘材料层126配置于第一金属层122与第二金属层124之间,第二金属层124位于高导热绝缘材料层126与图案化导电层130之间,而第一金属层122位于高导热绝缘材料层126与辅助介质层160之间。特别是,图1所提及的高导热绝缘结构120a具体化是先通过印刷而后烧结的方式所构成,但在图5的实施例中,封装载板100c的高导热绝缘结构120c的形成方式为先将第一金属层122以及第二金属层124堆叠于高导热绝缘材料层126上,再经由辅助介质层160以表面粘着的方式配置于凹穴114内。此外,辅助介质层160例如是一导热胶层、一焊料层或一共熔合金层(eutectic)。因此,图1所绘示的封装载板100a仅为举例说明,并非用以限定本发明。
此外,在其他未绘示的实施例中,发热元件10也可选择性地配置于如前述实施例所提及的不具凹穴114的基材110b且为单面线路结构的封装载板100b或具有表面粘着型的高导热绝缘结构120c的封装载板100c,本领域的技术人员当可参照前述实施例的说明,依据实际需求,而选用前述构件,以达到所需的技术效果。
以上仅介绍本发明的封装载板100a、100b、100c的结构,并未介绍本发明的封装基板100a、100b、100c的制作方法。对此,以下将以另一实施例配合图6A至图6G来详细说明上述实施例的封装载板100a的制作方法。在此必须说明的是,下述实施例沿用前述实施例的元件标号与部分内容,其中采用相同的标号来表示相同或近似的元件,并且省略了相同技术内容的说明。关于省略部分的说明可参考前述实施例,下述实施例不再重复赘述。
图6A至图6G为本发明的一实施例的一种封装载板的制作方法的剖面示意图。请先参考图6A,依照本实施例的封装载板100a的制作方法,首先,提供一基材110,其中基材110具有一表面112a以及一相对于表面112a的另一表面112b。
接着,请参考图6B,通过冲切、激光或蚀刻技术来形成一凹穴114于基材110的表面112a上。在此必须说明的是,在封装载板100b的制作中,此形成凹穴114的步骤省略。亦即,此步骤为选择性的制作工艺步骤,可依据使用者的需求而自行选择是否进行此步骤。
接着,请参考图6C,先通过印刷的方式涂布或填充高导热绝缘材料于基材110的凹穴114内,而后再经由烧结而形成高导热绝缘结构120a。之后,形成一贯穿基材110的表面112a与另一表面112b的贯孔116。在此必须说明的是,在封装载板100b的制作中,此形成贯孔116的步骤省略。亦即,此步骤为选择性的制作工艺步骤,可依据使用者的需求而自行选择是否进行此步骤。
接着,请参考图6D,填充一绝缘材料层172a于贯孔116内,其中绝缘材料层172a填满贯孔116。
接着,请参考图6E,形成一贯穿绝缘材料层172a的贯孔172b,以定义出一绝缘层172。
然后,请参考图6E,形成一导电层130a于基材110的表面112a与另一表面112b,其中导电层130a覆盖高导热绝缘结构120a以及于绝缘层172(意即覆盖绝缘材料层172a的贯孔172b的内壁)。
最后,请参考图6F,图案化导电层130a,以形成一图案化导电层130。其中,图案化导电层130的一部分配置于基材110的部分表面112a以及相对表面112a的另一表面112b上,且部分图案化导电层130覆盖高导热绝缘结构120a。图案化导电层130的另一部分(意即导电层174)覆盖绝缘层172且延伸至绝缘层172的相对两表面,并与图案化导电层130电性绝缘。至此,已大致完成封装载板100a的制作。
综上所述,由于本发明的高导热绝缘结构的热膨胀系数是介于基材的热膨胀系数与发热元件的热膨胀系数之间。因此,发热元件、高导热绝缘结构以及基材彼此之间的热膨胀系数差异可渐近式的逐渐减少。如此一来,可避免发热元件、高导热绝缘结构以及基材之间因热膨胀系数差异过大而导致相互之间的应力增加,可有效防止发热元件剥落、坏损的现象产生,进而可提高封装载板的使用可靠度。
虽然结合以上实施例揭露了本发明,然而其并非用以限定本发明,任何所属技术领域中熟悉此技术者,在不脱离本发明的精神和范围内,可作些许的更动与润饰,故本发明的保护范围应以附上的权利要求所界定的为准。
Claims (10)
1.一种封装载板,其适于承载一发热元件,该封装载板包括:
基材,具有一表面;
高导热绝缘结构,配置于该基材的部分该表面上;以及
图案化导电层,配置于该基材的部分该表面上,且部分该图案化导电层覆盖该高导热绝缘结构,其中该发热元件适于配置于位于该高导热绝缘结构上的该图案化导电层上,且该高导热绝缘结构的热膨胀系数介于该基材的热膨胀系数与该发热元件的热膨胀系数之间。
2.如权利要求1所述的封装载板,其中该基材的该表面具有凹穴,而该高导热绝缘结构位于该凹穴内,且突出于该基材的该表面。
3.如权利要求2所述的封装载板,还包括辅助介质层,该高导热绝缘结构包括第一金属层、第二金属层以及高导热绝缘材料层,该高导热绝缘结构通过该辅助介质层而固定于该凹穴内,其中该高导热绝缘材料层配置于该第一金属层与该第二金属层之间,该第二金属层位于该高导热绝缘材料层与该图案化导电层之间,而该第一金属层位于该高导热绝缘材料层与该辅助介质层之间。
4.如权利要求3所述的封装载板,其中该辅助介质层包括导热胶层、焊料层或共熔合金层(eutectic)。
5.如权利要求1所述的封装载板,其中该高导热绝缘结构包括陶瓷材料层或高导热胶层。
6.如权利要求1所述的封装载板,还包括绝缘通孔结构,该基材具有贯孔,该绝缘通孔结构配置于该贯孔内,其中该绝缘通孔结构包括一绝缘层以及一导电层,该绝缘层覆盖该贯孔的内壁,该导电层覆盖该绝缘层且延伸至该绝缘层的相对两表面,并与该图案化导电层电性绝缘,而该图案化导电层还配置于该基材相对于该表面的另一表面上。
7.如权利要求1所述的封装载板,其中该发热元件包括电子芯片或光电元件。
8.如权利要求1所述的封装载板,其中该发热元件通过打线接合而电连接至该图案化导电层。
9.如权利要求1所述的封装载板,其中该发热元件通过覆晶接合而电连接至该图案化导电层。
10.如权利要求1所述的封装载板,其中该发热元件为一芯片封装体,而该芯片封装体包括芯片以及承载板,且该芯片配置于该承载板上。
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CN113460948A (zh) * | 2021-06-30 | 2021-10-01 | 西人马联合测控(泉州)科技有限公司 | 一种芯片封装结构和芯片封装方法 |
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TW201232725A (en) | 2012-08-01 |
TWI449138B (zh) | 2014-08-11 |
US20120181066A1 (en) | 2012-07-19 |
CN102610586B (zh) | 2015-09-02 |
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