CN107305875B - 双向半导体封装件 - Google Patents

双向半导体封装件 Download PDF

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CN107305875B
CN107305875B CN201710186058.3A CN201710186058A CN107305875B CN 107305875 B CN107305875 B CN 107305875B CN 201710186058 A CN201710186058 A CN 201710186058A CN 107305875 B CN107305875 B CN 107305875B
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base plate
clad base
direct copper
substrate
semiconductor chip
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CN107305875A (zh
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高在铉
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Hyundai Mobis Co Ltd
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Abstract

提供了一种双向半导体封装件。该双向半导体封装件包括：下部直接覆铜(DBC)基板，包括第一基底以及结合至第一基底的上表面和下表面的第一图案层；引线框，安装在下部DBC基板的上表面上；半导体芯片，安装在引线框的上表面上；上部DBC基板，包括第二基底以及结合至第二基底的上表面和下表面的第二图案层；缓冲层，其一端焊接在上部DBC基板的下表面上且另一端焊接在引线框的上表面上的安装了半导体芯片的区域以外的剩余区域的上表面上；缓冲线，其一端焊接在位于半导体芯片的一个方向上的区域的上表面上并且另一端焊接在位于半导体芯片的另一方向上的区域的上表面上；以及导线，其将下部DBC基板的上表面电连接至半导体芯片。

Description

双向半导体封装件
相关申请的引证
本申请要求于2016年4月19日提交的韩国专利申请第10-2016-0047483号的优先权和权益，其全部内容通过引证结合于此。
技术领域
本发明涉及一种双向半导体封装件，并且更具体地，涉及其中用于制造双向半导体封装件的处理个数减少的双向半导体封装件。
背景技术
通常，在半导体工业中，存在产品变得更轻、更紧密、更多功能以及以低成本具有更高性能的趋势。
集成电路(IC)封装技术是满足该趋势所需的一项重要技术。
IC封装件保护诸如单个元件的半导体芯片以及其中各种电子电路和配线由于各种外部环境因素(诸如，灰尘、湿气、电负载、机械负载等)而堆叠的IC设备。
此外，IC封装件指的是其中信号输入和输出端子使用引线框、印刷电路板(PCB)等形成在主板上并且使用密封剂模制以优化且最大化半导体芯片的电性能的封装件。
同时，最近，由于安装了IC封装件的产品变得很轻、短且小并且需要许多功能，所以诸如系统级封装(SiP)(其中，在IC封装件上安装了多个半导体芯片)、堆叠式封装(PoP)等的方法已被应用为IC封装技术。
此外，还应该降低PCB(其上安装了高度集成且超薄的部件)的厚度的事实已变为一项挑战。
应增加基板的电路设计中的自由度以满足这些需求，并且已尝试通过应用各种新技术(诸如微通孔、积层等)来解决这种问题。
同时，在各种基板中，由于不同于一般PCB，陶瓷基板是使用陶瓷作为基底材料而形成的，所以陶瓷基板具有能够承受高温和高电流的特性。
由于该特性，陶瓷基板主要用于功率半导体、绝缘栅极双极晶体管(IGBT)、大功率发光二极管(LED)、太阳能电池模块等。
这种陶瓷基板，并且具体为直接覆铜(DBC)基板，用于相对高电压的产品。
最近，由于多功能和高性能的趋势，电子设备需要大量半导体，并且因此，产生高温并且需要半导体封装件的更高的散热效率。
因此，传统地，DBC基板沿向上和向下的方向层叠以进一步增加半导体封装件的散热效率，并且因此半导体封装件的散热效果通过在两个方向上的散热而增大。
如在图1中所示，传统双向半导体封装件包括下部DBC基板10、上部DBC基板20、半导体芯片30、间隔构件40以及线50。
在传统双向半导体封装件中，半导体芯片30安装在下部DBC基板10的上表面上，并且线50结合至所安装的半导体芯片30的上表面。
接下来，将焊料施加至半导体芯片30的上表面的线50结合至的区域以外的剩余区域，并且将间隔构件40安装在焊料的上表面上。
此外，上部DBC基板20安装在间隔构件40的上表面上，并且在以上处理之后使用密封剂进行模制。
因此，下部DBC基板10与上部DBC基板20可电连接至彼此，并且双向半导体封装件的散热效果可进一步增强。
然而，由于DBC基板10和20与间隔构件40之间的接触面积大，所以存在当制造双向半导体封装件时，由于焊接在半导体芯片30的底面上生成空气层并且半导体封装件的寿命减少的问题。
此外，在传统双向半导体封装件中，存在制造双向半导体封装件的处理中其总体焊接厚度不均匀并且半导体芯片30或DBC基板10和20被损坏或者模制构件与其分离的问题。
此外，传统地，间隔构件40包括将半导体芯片30连接至上部DBC基板20的第一间隔构件41以及支撑上部DBC基板20和下部DBC基板10的第二间隔构件42。由于将第一间隔构件41和第二间隔构件42分别焊接至下部DBC基板10和上部DBC基板20的处理占据总处理时间的高百分比，所以存在产量降低以及成本增加的问题。
发明内容
本发明针对于一种焊接在基板上并且与基板的接触面积较小的热量生成部分。
根据本发明的一个方面，提供了一种双向半导体封装件，包括：下部直接覆铜(DBC)基板，该下部直接覆铜基板包括：由陶瓷制成的第一基底以及结合至第一基底的上表面和下表面的第一图案层；引线框，安装在下部DBC基板的上表面上；半导体芯片，安装在引线框的上表面上；上部DBC基板，包括由陶瓷制成的第二基底以及结合至第二基底的上表面和下表面的第二图案层，其中，上部DBC基板在向上方向上与下部DBC基板间隔开；缓冲层，该缓冲层的一端焊接在上部DBC基板的下表面上并且另一端焊接在引线框的上表面上的安装了半导体芯片的区域以外的剩余区域的上表面上，其中，缓冲层支撑下部DBC基板与上部DBC基板之间的间隙；缓冲线，沿横向方向与缓冲层间隔开，并且该缓冲线的一端焊接在位于半导体芯片的一个方向上的区域的上表面上并且另一端焊接在位于半导体芯片的另一方向上的区域的上表面上；以及导线，被配置为将下部DBC基板的上表面电连接至半导体芯片。缓冲线的一端与另一端之间的一部分与上部DBC基板的下表面接触，并且由半导体芯片生成的热量传递至上部DBC基板。
沿上部DBC基板的方向弯曲的至少一个拐点以及沿下部DBC基板的方向弯曲的至少一个拐点连续形成在缓冲线的一端与另一端之间，并且从上部DBC基板向下部DBC基板弯曲的弯曲部的拐点可与上部DBC基板的下表面接触。
缓冲线可包括条带状金属线或胶带状金属线。
第一图案层和第二图案层可由铜制成。
半导体芯片可包括功率半导体芯片。
封装件可进一步包括模制部，该模制部被配置为围绕下部DBC基板和上部DBC基板并且被配置为保护下部DBC基板、上部DBC基板以及布置在下部DBC基板与上部DBC基板之间的各种电子部件。
模制部可利用环氧模制化合物(EMC)进行模制。
附图说明
对于本领域普通技术人员来说，通过参考附图详细描述本发明的示例性实施方式，本发明的以上和其他目的、特征和优势将变得更加显而易见，其中：
图1是示出了传统双向半导体封装件的截面图；以及
图2是示出了根据本发明的一个实施方式的双向半导体封装件的截面图。
具体实施方式
参考附图和以下具体实施方式，本发明的优势和特征以及实现其的方法应被清楚理解。然而，本发明不限于以下所公开的实施方式，并且可以各种不同形式实现。提供实施方式以便向本领域技术人员充分说明本发明并且充分说明本发明的范围。本发明的范围由所附权利要求限定。同时，提供本文使用的术语只是为了描述而并非为了限制本发明的实施方式。除非上下文另外明确表示，否则单数形式包括复数形式。应理解，当在本文中使用时，术语“包括(comprise)”和/或“包含(comprising)”指定所述部件、步骤、操作和/或元件，但不排除一种或多种其他部件、步骤、操作和/或元件的存在或添加。
在下文中，将参考附图详细描述本发明的实施方式。
图2是示出了根据本发明的一个实施方式的双向半导体封装件的截面图。
参考图2，根据本实施方式的双向半导体封装件包括下部直接覆铜(DBC)基板100、引线框200、半导体芯片300、上部DBC基板400、缓冲层500、缓冲线600、导线700以及模制部800。
与将由绝缘材料制成的引线框200放置在传统散热材料的表面上的情况相比，下部DBC基板100具有更高散热效率。
下部DBC基板100包括第一基底110和第一图案层120。
第一基底110是由陶瓷制成的板，并且更具体地，是由作为绝缘材料的氧化铝(Al2O3)、氮化铝(AlN)等形成的板。
第一图案层120结合至第一基底110的上表面和下表面，并且由铜或铜合金制成。
与一般基板相比，具有这种结构的下部DBC基板100具有更高的散热效率。
此外，由于由铜或铜合金制成的第一图案层120结合至下部DBC基板100的第一基底110的上表面和下表面，所以可在其上执行焊接或引线接合。
引线框200通过图案化金属框架上的引线端子而形成以使半导体芯片300的电性能最大化，并且引线框被安装在下部DBC基板100的上表面上的安装了半导体芯片300的区域上。
整个引线框200可被电镀，并且电镀材料可包括镍、铜或其他金属。
半导体芯片300通过在其上执行焊接或施加导电环氧树脂而被安装在引线框200的上表面上。
半导体芯片300包括功率半导体芯片300。
最近，电子设备的设计已随着子设备的多功能和高性能的趋势而多样化，并且因此半导体芯片300的数量可根据电子设备的设计而改变。
与将由绝缘材料制成的氧化铝引线框200放置在传统散热材料的表面上的情况相比，上部DBC基板400具有更高散热效率。
上部DBC基板400包括第二基底410和第二图案层420。
第二基底410是由陶瓷制成的板，并且更具体地，是由作为绝缘材料的氧化铝(Al2O3)、氮化铝(AlN)等形成的板。
第二图案层420结合至第二基底410的上表面和下表面并且由铜或铜合金制成。
具备这种结构的上部DBC基板400具有与上述的下部DBC基板100的结构和特性相同的结构和特性，并且沿向上方向与下部DBC基板100间隔开。
因此，由于根据本发明的一个实施方式的双向半导体封装件包括下部DBC基板100和上部DBC基板400，所以需要大量半导体的半导体封装件的高热量可被有效耗散。
缓冲层500的一端焊接在上部DBC基板400的下表面上，并且其另一端焊接在引线框200的上表面上的安装了半导体芯片300的区域以外的剩余区域的上表面上。
因此，缓冲层500可稳固支撑下部DBC基板100与上部DBC基板400之间的间隙。
此外，由于缓冲层500稳固支撑下部DBC基板100与上部DBC基板400之间的间隙，所以根据本发明的一个实施方式的双向半导体封装件的总体厚度可均匀保持。
此外，缓冲层500阻挡热量从外部传递至半导体芯片300的路径，使得半导体芯片300不被热量损坏。
优选地，缓冲层500由相变材料(PCM)制成。
已知PCM具有如下特性，周围能量在相位转换过程期间累积了预定时间，并且随后当能量的量大于PCM的存储容量时被再发射。
由于根据本发明的一个实施方式的双向半导体封装件包括具有这种特性的缓冲层500，所以连续执行制造半导体封装件的处理所生成的热量可被顺利排出至外部。
缓冲线600沿横向方向与缓冲层500间隔开。缓冲线600的一端焊接在位于半导体芯片300的一个方向上的区域的上表面上，并且其另一端焊接在位于半导体芯片300的另一方向上的区域的上表面上。
缓冲线600可包括条带状金属线或胶带状金属线。
因此，由于缓冲线600以线型形成，所以缓冲线600的与半导体芯片300的上表面接触的截面的面积可较小，可防止由于焊接而在半导体芯片300的薄表面上生成空气层，并且因此根据本发明的一个实施方式的双向半导体封装件的寿命可增长。
此外，由于缓冲线600以线型形成，所以焊接厚度可以是均匀的，并且因此，在制造双向半导体封装件的处理中，可防止半导体芯片300、上部DBC基板400或下部DBC基板100损坏，或者可防止模制构件与其分层。沿上部DBC基板400的方向弯曲的至少一个拐点610以及沿下部DBC基板100的方向弯曲的至少一个拐点610连续形成在缓冲线600的一端与另一端之间。
同时，从上部DBC基板400向下部DBC基板100弯曲的弯曲部的拐点610与上部DBC基板400的下表面接触。
因此，由于缓冲线600可轻易将由半导体芯片300生成的热量传递至上部DBC基板400，所以由半导体芯片300生成的热量可被有效耗散。
此外，由于缓冲线600的一端和另一端(即，两个位置)焊接在半导体芯片300的上表面上，所以可减少用于制造根据本发明的一个实施方式的双向半导体封装件的处理的个数，并且因此可降低由复杂处理造成的缺陷率。
导线700将下部DBC基板100的上表面电连接至半导体芯片300。
导线700可由金、铝、铜等形成。
模制部800用来密封和保护下部DBC基板100、上部DBC基板400以及通过围绕下部DBC基板100和上部DBC基板400而布置在下部DBC基板100与上部DBC基板400之间的各种电子部件。
模制部800可利用环氧模制化合物(EMC)进行模制。
如上所述，在根据本发明的双向半导体封装件中，由于缓冲层500稳固支撑下部DBC基板100与上部DBC基板400之间的间隙，所以双向半导体封装件的总体厚度可均匀保持。
此外，由于缓冲线600形成为具有线型截面，所以与半导体芯片300的上表面接触的该截面的面积可较小，可防止由于焊接而在半导体芯片300的薄表面上生成空气层，并且因此双向半导体封装件的寿命可增加。
此外，由于缓冲线600形成为具有线型截面，所以焊接厚度可以是均匀的，并且因此，在制造双向半导体封装件的处理中，可防止半导体芯片300、上部DBC基板400或下部DBC基板100损坏，或者可防止模制构件与其分层。
此外，由于从上部DBC基板400向下部DBC基板100弯曲的弯曲部的拐点610与上部DBC基板400的下表面接触，所以由半导体芯片300生成的热量可被轻易传递至上部DBC基板400，并且因此，由半导体芯片300生成的热量可被有效耗散。
此外，由于缓冲线600的一端和另一端(即，两个位置)焊接在半导体芯片300的上表面上，所以可减少用于制造双向半导体封装件的处理的个数，并且因此可降低由复杂处理造成的缺陷率。
在根据本发明的双向半导体封装件中，由于缓冲层稳固支撑下部DBC基板与上部DBC基板之间的间隙，所以可均匀保持双向半导体封装件的总体厚度。
此外，由于缓冲线形成为具有线型截面，所以与半导体芯片的上表面接触的该截面的面积可较小，可防止由于焊接而在半导体芯片的薄表面上生成空气层，并且因此双向半导体封装件的寿命可增长。
此外，由于缓冲线形成为具有线型截面，所以焊接厚度可以是均匀的，并且因此，在制造双向半导体封装件的处理中，可防止半导体芯片、上部DBC基板或下部DBC基板损坏，或者可防止模制构件与其分层。
此外，由于从上部DBC基板向下部DBC基板弯曲的弯曲部的拐点与上部DBC基板的下表面接触，所以由半导体芯片生成的热量可被轻易传递至上部DBC基板，并且因此通过半导体芯片生成的热量可被有效耗散。
此外，由于缓冲线的一端和另一端(即，两个位置)焊接在半导体芯片的上表面上，所以可减少用于制造双向半导体封装件的处理的个数，并且因此可降低由复杂处理造成的缺陷率。
本发明不限于上述实施方式，并且在本发明的范围内可体现为各种方式。

Claims (7)

1.一种双向半导体封装件，包括：
下部直接覆铜基板，包括由陶瓷制成的第一基底以及结合至所述第一基底的上表面和下表面的第一图案层；
引线框，安装在所述下部直接覆铜基板的上表面上；
半导体芯片，安装在所述引线框的上表面上；
上部直接覆铜基板，包括由陶瓷制成的第二基底以及结合至所述第二基底的上表面和下表面的第二图案层，其中，所述上部直接覆铜基板沿向上方向与所述下部直接覆铜基板间隔开；
缓冲层，所述缓冲层的一端焊接在所述上部直接覆铜基板的下表面上并且所述缓冲层的另一端焊接在所述引线框的上表面上的安装了所述半导体芯片的区域以外的剩余区域的上表面上，其中，所述缓冲层支撑所述下部直接覆铜基板与所述上部直接覆铜基板之间的间隙；
缓冲线，沿横向方向与所述缓冲层间隔开，并且所述缓冲线的一端焊接在位于所述半导体芯片的一个方向上的区域的上表面上并且所述缓冲线的另一端焊接在位于所述半导体芯片的另一方向上的区域的上表面上，其中，所述缓冲线具有线型截面；以及
导线，被配置为将所述下部直接覆铜基板的上表面电连接至所述半导体芯片，
其中，所述缓冲线的所述一端与所述另一端之间的部分与所述上部直接覆铜基板的下表面接触，并且由所述半导体芯片生成的热量传递至所述上部直接覆铜基板。
2.根据权利要求1所述的双向半导体封装件，其中：
沿所述上部直接覆铜基板的方向弯曲的至少一个拐点以及沿所述下部直接覆铜基板的方向弯曲的至少一个拐点连续形成在所述缓冲线的一端与另一端之间；并且
从所述上部直接覆铜基板向所述下部直接覆铜基板弯曲的弯曲部的拐点与所述上部直接覆铜基板的下表面接触。
3.根据权利要求1所述的双向半导体封装件，其中，所述缓冲线包括条带状金属线或胶带状金属线。
4.根据权利要求1所述的双向半导体封装件，其中，所述第一图案层和所述第二图案层由铜制成。
5.根据权利要求1所述的双向半导体封装件，其中，所述半导体芯片包括功率半导体芯片。
6.根据权利要求1所述的双向半导体封装件，进一步包括模制部，所述模制部被配置为围绕所述下部直接覆铜基板和所述上部直接覆铜基板并且被配置为保护所述下部直接覆铜基板、所述上部直接覆铜基板以及布置在所述下部直接覆铜基板与所述上部直接覆铜基板之间的各种电子部件。
7.根据权利要求6所述的双向半导体封装件，其中，所述模制部利用环氧模制化合物进行模制。
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