US20110024898A1 - Method of manufacturing substrates having asymmetric buildup layers - Google Patents

Method of manufacturing substrates having asymmetric buildup layers Download PDF

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Publication number
US20110024898A1
US20110024898A1 US12/533,569 US53356909A US2011024898A1 US 20110024898 A1 US20110024898 A1 US 20110024898A1 US 53356909 A US53356909 A US 53356909A US 2011024898 A1 US2011024898 A1 US 2011024898A1
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Prior art keywords
buildup layers
layers
buildup
core
layer
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US12/533,569
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Andrew Leung
Roden Topacio
Liane Martinez
Yip Seng Low
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ATI Technologies ULC
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ATI Technologies ULC
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Priority to US12/533,569 priority Critical patent/US20110024898A1/en
Priority to EP10803777.1A priority patent/EP2460393B1/en
Priority to JP2012521917A priority patent/JP5723363B2/ja
Priority to PCT/CA2010/001174 priority patent/WO2011011880A1/en
Priority to KR1020117031056A priority patent/KR101633839B1/ko
Priority to CN201080034121.8A priority patent/CN102656955B/zh
Publication of US20110024898A1 publication Critical patent/US20110024898A1/en
Priority to US13/152,918 priority patent/US8298945B2/en
Assigned to ATI TECHNOLOGIES ULC reassignment ATI TECHNOLOGIES ULC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LEUNG, ANDREW, LOW, YIP SENG, MARTINEZ, LIANE, TOPACIO, RODEN
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B37/00—Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding
    • B32B37/02—Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding characterised by a sequence of laminating steps, e.g. by adding new layers at consecutive laminating stations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2309/00—Parameters for the laminating or treatment process; Apparatus details
    • B32B2309/08—Dimensions, e.g. volume
    • B32B2309/10—Dimensions, e.g. volume linear, e.g. length, distance, width
    • B32B2309/105—Thickness
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2310/00—Treatment by energy or chemical effects
    • B32B2310/08—Treatment by energy or chemical effects by wave energy or particle radiation
    • B32B2310/0806—Treatment by energy or chemical effects by wave energy or particle radiation using electromagnetic radiation
    • B32B2310/0843—Treatment by energy or chemical effects by wave energy or particle radiation using electromagnetic radiation using laser
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2457/00—Electrical equipment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09136—Means for correcting warpage
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
    • H05K3/0035—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material of blind holes, i.e. having a metal layer at the bottom
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0055—After-treatment, e.g. cleaning or desmearing of holes
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
    • Y10T156/10—Methods of surface bonding and/or assembly therefor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing

Definitions

  • the present invention relates generally to electronic packaging, and more particularly to substrates for use in such packaging, having an unequal number of buildup layers on opposite sides, that may form part of integrated circuit packages, peripheral expansion cards and printed wiring boards or printed circuit boards.
  • Substrates are used in integrated circuit packages, peripheral expansion cards, motherboards and other printed wiring boards that are used to form electronic circuit packages. Conductive traces formed on the substrate electrically interconnect various electrical components that are attached to the substrate.
  • Integrated circuit packages usually include a carrier substrate used to attach a semiconductor die containing an integrated circuit.
  • the carrier substrate may also contain solder balls or pins which are used to attach the integrated circuit package to an external circuit such as a peripheral expansion card or a printed circuit board.
  • a substrate usually includes a core on which one or more routing layers for routing electrical signals are formed.
  • a passive circuit of conductive traces is initially formed on one or both surfaces of the core. These conductive traces are often etched using thin-film metals or copper foils. Thereafter, one or more additional routing layers are built upon the core (so called “buildup layers”).
  • a buildup layer typically includes a dielectric layer and a conductive layer. The dielectric layer is typically formed by laminating dielectric material over a formed routing layer or the core. The conductive layer is formed on the dielectric layer. The dielectric material in the buildup layer insulates the conductive layer, from conductive traces underneath the dielectric layer. Holes may be formed at suitable points in the dielectric layer to interconnect parts of the conductive layer on the dielectric of one buildup layer, to traces underneath the dielectric material. Multiple such buildup layers can be formed on one another.
  • PTH plated through-holes
  • Forming an equal number of buildup layers on each side of the core is often inefficient as it may lead to the formation of more buildup layers than may be required. For example, if an odd number of buildup layers (e.g., three layers) are sufficient, then having an equal number of buildup layers on top and at the bottom of the core (e.g., two on each side) introduces a fourth, largely redundant layer. This is undesirable as it adds to the material and manufacturing cost of the package.
  • Single-sided substrates that have buildup layers formed only on one side, are also known. However, such substrates are also susceptible to warping. Moreover, in a single-sided substrate, electric components, such as an integrated circuit die, are typically attached to the same side of the substrate (containing the buildup layers) which limits the area available to attach the die.
  • a method of manufacturing a substrate with asymmetric buildup layers is disclosed.
  • the substrate has a core, m buildup layers formed on one surface of the core and n buildup layers (m>n) formed on the opposite surface of the core.
  • Each of the buildup layers comprises a dielectric layer, and a conductive layer formed thereon.
  • the method includes: forming (m ⁇ n) of the m buildup layers on the first surface. Forming each of the (m ⁇ n) of the m buildup layers includes drilling and desmearing a respective dielectric layer; and forming n pairs of buildup layers, each of the n pairs having one of the n buildup layers formed on the second surface and one of the remaining n of the m buildup layers formed on the first surface. Forming each of the n pairs of buildup layers includes drilling each one of a respective pair of dielectric layers, and desmearing the respective pair of dielectric layers concurrently.
  • FIG. 1 is a flowchart of a conventional process used to manufacture a conventional substrate having an unequal number of buildup layers on either sides of the core;
  • FIGS. 2A-2K are vertical cross-sectional views of a conventional substrate at different stages of manufacturing corresponding to the steps depicted FIG. 1 ;
  • FIG. 3 is a flowchart of a process, exemplary of an embodiment of the present invention, used to make an exemplary substrate;
  • FIGS. 4A-4K are vertical cross-sectional views of an exemplary substrate at different stages of manufacturing corresponding to the exemplary steps depicted in FIG. 3 ;
  • FIG. 5 is a vertical cross-sectional view of an exemplary semiconductor device having an unequal number of buildup layers on each side of a substrate core
  • FIG. 6 is a vertical cross-sectional view of another embodiment of an exemplary semiconductor device having an unequal number of buildup layers on each side of its core and copper rings.
  • Substrates that include a core having k layers, m buildup layers on one side of the core, and n buildup layers on the other side of the core may generally be said to have an m/k/n buildup design, where m and n are positive integers. Such substrates may be said to have asymmetric buildup layers if m ⁇ n.
  • Asymmetric substrates that have m/k/n buildup design thus include a core and a total of m+n buildup layers.
  • Each buildup layer typically includes a dielectric layer such as Ajinomoto build-up film (ABF) for example, and conductive traces formed on the dielectric layer.
  • Ajinomoto build-up film ABSF
  • FIG. 1 depicts a conventional manufacturing process often used by substrate vendors to provide substrates having asymmetric or unequal numbers of buildup layers on opposite sides of a core.
  • FIGS. 2A-2K depicts cross-sectional views of such a substrate at different stages concordant with the steps in flowchart S 100 .
  • a substrate core 118 which may have its own sub-layers is initially machine drilled in step S 102 to form a plated through-hole (PTH).
  • PTH plated through-hole
  • conductive traces are used to form a circuit or conductive layer on either side of core 118 .
  • a plated through hole 116 may be used to interconnect circuit traces on opposite sides of substrate core 118 .
  • a first top buildup layer 126 and a first bottom buildup layer 128 are laminated using a dielectric material (e.g. ABF).
  • the first buildup dielectric layers 126 , 128 top and bottom) are laser drilled, and desmeared to expose traces of the core circuit formed in step S 104 .
  • conductive traces are used to form conductive layers on both first top buildup layer 126 and on first bottom buildup layer 128 .
  • Desmearing generally refers to the removal of residues, to ensure proper electrical interconnections.
  • Residues may include smeared epoxy-resin byproducts, ABF bits or dielectric bits may attach to trace surfaces that are exposed within a drilled hole (via, micro-via or PTH).
  • dielectric materials such as epoxy-resin or ABF, often melt and become smeared across surfaces of conductive traces.
  • Subsequent plating of drilled holes (vias or through-holes) using conductive material is intended to electrically connect traces from different buildup layers.
  • the residue would create a dielectric barrier between trace surfaces and the conductive plating of the inner walls of drilled holes, often leading to a defective circuit.
  • Desmearing typically involves the use of a cleaning solution such as sodium or potassium permanganate to chemically clean and remove such residue from conductive traces.
  • step S 112 the dielectric layer of a second buildup layer 124 is formed using an ABF layer or equivalent dielectric material. However, no additional (second) bottom buildup layer is formed, as it is not required.
  • step S 114 the top second buildup layer 124 is laser drilled and desmeared to expose the traces of the conductive layer of the first buildup layer formed in step S 110 .
  • holes are drilled, residues of the drilled material are formed.
  • a dielectric layer such as epoxy fiber glass or resin
  • pieces of the dielectric material may be formed.
  • friction of the drill bit against the material being drilled causes the temperature of the drill bit to rise above the melting temperature of the material.
  • Laser drilling similarly raises the temperature above the melting point of the material being drilled.
  • Pieces of the drilled material thus melted are often smeared onto surfaces such as the inner walls of the hole which expose parts of conductive traces.
  • Desmearing is thus required to remove the residue (left by drilling in step S 114 ), some of which may have been smeared on the conductive traces.
  • Desmearing typically involves several immersions or dipping of the substrate in a cleaning solution such as a permanganate solution, for a predetermined duration.
  • a cleaning solution such as a permanganate solution
  • Desmearing is known in the art and is described, for example, in U.S. Pat. No. 4,425,380 and U.S. Pat. No. 4,601,783 the contents of which are incorporated herein by reference.
  • desmearing may also involve a water rinse after immersing the substrate in a chemical solution.
  • step S 114 first bottom buildup layer 128 is also desmeared. Notably, this is the second desmearing step performed on layer 128 as it was already desmeared in step S 108 and may thus be unnecessary.
  • step S 116 additional conductive traces are used to form the conductive layer of second top buildup layer 124 and the conductive layer of bottom buildup layer 128 .
  • step S 118 solder masks 120 and 132 are applied to the conductive layer formed on buildup layers 124 , 128 respectively.
  • step S 120 surface finishing is performed to provide additional protection against oxidation of the conductive layer, and to prepare the surface for mounting solder balls and/or attaching a die.
  • the resulting substrate depicted in FIG. 2K has a 2/k/1 buildup design where k is the number of sub-layers in core 118 .
  • the substrate of FIG. 2K may include an overdesmeared bottom buildup layer 128 as a consequence of two desmearing steps (S 108 and S 114 ).
  • Over-desmearing results from subjecting a dielectric layer to multiple desmearing steps.
  • the dielectric layer of buildup layer 128 is desmeared twice in S 100 (once in step S 108 and then again in step S 114 ).
  • Over-desmearing leads to many undesirable changes in a buildup layer.
  • the adhesion properties a dielectric layer may be negatively affected.
  • drilled holes or vias in the dielectric layer may expand, if multiple desmearing steps are applied.
  • the surface of dielectric layers may become rougher as a result.
  • FIG. 3 depicts a flowchart S 300 depicting a manufacturing process exemplary of an embodiment of the present invention, which may be used to provide a substrate device having different (unequal) numbers of buildup layers on opposite sides of its core.
  • the first surface (e.g., top) of the core may have m buildup layers formed thereon while the second (e.g., bottom) surface may have n buildup layers formed (where m ⁇ n).
  • FIGS. 4A-4K depict sectional views of the substrate being manufactured, at different stages manufacturing concordant with the steps depicted in flowchart S 300 .
  • a substrate core (e.g., core 218 ) which may have its own sub-layers (sub-layers not shown), is initially machine drilled in step S 302 .
  • conductive traces are used to form a conductive layer or circuit on either side of core 218 .
  • Conductive layers may be formed by etching conductive traces on the core using thin-film metal or copper foils.
  • a plated through hole (PTH) 216 may be formed and used to interconnect the core circuit traces on opposite sides of substrate core 218 .
  • PTH is formed by plating the inner walls of the hole formed in step S 302 , with conductive material, such as copper.
  • step S 306 the dielectric layer of a first top buildup layer 226 is formed by laminating a dielectric material such as ABF. However, at this step, no bottom buildup layer is formed. Instead only the top buildup layer is formed. It should be noted that this contrasts with the conventional process depicted in flowcharts S 100 , in which both the first top and the first bottom buildup layers would have been formed at this stage.
  • step S 308 first buildup layer 226 is laser drilled, and desmeared to expose circuit traces formed in step S 304 on the upper side of core 218 .
  • the circuit on the lower side of core 218 is already exposed, as there is no lamination of the bottom.
  • step S 310 conductive traces are used to form a conductive layer or circuit on buildup layer 226 .
  • the circuit formed on the lower surface of core 218 is not limited.
  • steps S 306 , S 308 , S 310 may be sequentially performed to form a dielectric layer, drill and desmear the dielectric layer, and then form a conductive layer on the desmeared dielectric, in order to form (m ⁇ n) of the top m buildup layers.
  • a second top buildup layer 224 and a first bottom buildup layer 228 are formed using a layer of dielectric material such as ABF.
  • layer 228 may be substantially thicker than layer 224 to help mitigate warping.
  • the dielectric layers of second top buildup layer 224 and first bottom buildup layer 228 may be laser drilled and then desmeared.
  • the drilled vias expose parts of the circuit traces of the conductive layer atop top buildup layer 226 (formed in step S 310 ) and also expose parts of the circuit traces formed at the bottom of substrate core 218 (formed in step S 304 ).
  • step S 316 additional conductive traces are used to form conductive layers of both second top buildup layer 224 and first bottom buildup layer 228 .
  • the drilled vias may be filled with conductive material to interconnect traces of newly formed conductive layers with the existing conductive layers formed in step S 310 .
  • steps S 312 , S 314 and S 316 may be used to form n pairs of buildup layers, each pair having one of the n buildup layers to be formed on the second (bottom) surface of the core, and one of the remaining n of the m buildup layers formed on the first (top) surface.
  • Each buildup layer includes a dielectric layer and a conductive layer formed thereon.
  • Forming each of the n pairs of buildup layers involves drilling each one of a respective pair of dielectric layers, and desmearing that pair of dielectric layers concurrently (S 314 ).
  • Conductive layers are then formed on the desmeared dielectric layers (S 316 ).
  • (m ⁇ n) of the m layers have already been formed using steps S 306 , S 308 , S 310 .
  • solder mask is applied to circuits formed on buildup layers 224 , 228 .
  • Solder masks are of course applied on the outermost buildup layers 224 , 228 .
  • solder mask 232 applied on the side having fewer buildup layers may be substantially thicker than solder mask 220 on the opposite (upper) side of core 218 .
  • step S 320 surface finishing is performed to prepare the surface for mounting solder balls and/or attaching a die.
  • each layer of dielectric material e.g. ABF
  • the substrate in FIG. 4K would not have any overdesmeared buildup layers that typically result from undergoing two or more desmearing steps.
  • the method depicted in S 300 is representative of a generalized method of manufacturing a substrate that is exemplary of an embodiment of the present invention. Accordingly, a general method of manufacturing a substrate having a core (e.g. core 218 ), m buildup layers (e.g., two buildup layers 226 , 224 ) on a first (e.g. top) surface of the core and n buildup layers (e.g.
  • a core e.g. core 218
  • m buildup layers e.g., two buildup layers 226 , 224
  • n buildup layers e.g.
  • one buildup layer 228 ) on a second (e.g., bottom) surface of the core involves: forming (m ⁇ n) of the m buildup layers on the first surface, where forming each of the (m ⁇ n) of the m buildup layers includes drilling and desmearing a respective dielectric layer; and forming n pairs of buildup layers, each of the n pairs including one of the n buildup layers formed on the second surface and one of the remaining n of the m buildup layers formed on the first surface.
  • Forming each of the n pairs of buildup layers includes drilling each one of a respective pair of dielectric layers, and desmearing the respective pair of dielectric layers concurrently.
  • Each buildup layer may be formed by sequentially forming a dielectric layer, drilling and desmearing the dielectric, and forming a conductive layer of traces on the desmeared dielectric.
  • Conductive traces my be formed by etching or depositing conductive materials, such as thin-film metal or copper foil, after the dielectric layer is drilled and desmeared.
  • laser drilling and machine drilling may be interchangeably used for drilling core layers having a thickness or height less than about 100 ⁇ m.
  • Thicker cores e.g., 400 ⁇ m or 800 ⁇ m typically use mechanical drilling.
  • Other known methods for forming holes or cavities within dielectric materials or insulators may also be used.
  • Coreless substrates and single-sided substrates are also highly susceptible to warping. Stiffeners are often required to ensure that coreless or single-sided substrates can withstand mechanical and thermal stresses that cause warping and potentially render circuits inoperable.
  • Exemplary embodiments of the present invention may include thicker buildup dielectric layers and thicker solder-mask layers on the side of the core that contains fewer buildup layers, to mitigate warping.
  • bottom buildup layer 228 may use a thicker dielectric layer than the dielectric layer used in buildup layers 224 , 226 .
  • buildup layer 228 may be about 40 ⁇ m-60 ⁇ m, while buildup layers 224 , 226 are each about 25 ⁇ m-40 ⁇ m.
  • solder mask 232 may be made substantially thicker than its corresponding upper solder mask 220 .
  • various relative thickness values may be used.
  • solder mask 232 may be 30 ⁇ m-60 ⁇ m while solder mask 220 may only be 16 ⁇ m-30 ⁇ m in height.
  • Solder mask 232 may be replaced by a layer of dielectric material.
  • a plurality of rings made for example of copper, may be used to reinforce the semiconductor devices exemplary of the present invention.
  • FIG. 5 depicts a partial vertical cross-section of an exemplary integrated circuit package 200 including a substrate 204 having buildup layers on both sides.
  • Integrated circuit package 200 includes a die 202 attached to substrate 204 .
  • Die 202 is typically made of a semiconductor material such as a piece of silicon wafer and contains an integrated circuit and pads 208 formed on its active surface. Pads 208 provide I/O connection points to the integrated circuit on die 202 . UBM may be formed on each of pads 208 to facilitate attachment of solder bumps 210 using the controlled collapse chip connect (C4) or flip chip attachment technique. Solder bumps 210 formed on pads 208 may be used to attach die 202 to substrate 204 .
  • C4 controlled collapse chip connect
  • Substrate 204 includes a substrate core 218 , and a plurality of buildup layers 224 , 226 , 228 .
  • Solder masks 220 , 232 are formed on the outermost buildup layers 224 , 228 respectively.
  • Pre-solder 236 may be applied on each of substrate pads 234 .
  • Substrate core 218 may include a plurality of its own multiple layers or sub-layers (not shown).
  • a plated through hole (PTH) 216 formed in core 218 can be used to electrically interconnect traces 212 in layers 224 , 226 with traces 212 in layer 228 .
  • Vias or micro-vias 214 may be formed by laser drilling, and plated or filled with conductive material to interconnect traces on layer 224 with those on layer 226 .
  • micro-vias 214 may be used to interconnect traces 212 on layer 226 with traces on the upper surface of core 218 ; or traces on layer 228 with traces on the lower surface of core 218 .
  • Pre-solder 236 may be in the form of solder paste, and thus may increase solder volume and provide good interconnection between solder bumps 210 and substrate pads 234 during the die attach process. Pre-solder 236 also increases the effective height of bumps 210 which helps capillary underfill processes.
  • buildup layer 228 may contain a much thicker dielectric material than layers 224 , 226 .
  • layer 228 may be 40 ⁇ m-60 ⁇ m thick while layers 224 , 226 may each have a nominal thickness in the range of 25 ⁇ m-40 ⁇ m exclusive.
  • any layer (e.g., buildup layer 228 ) on the side of the core containing fewer buildup layers (e.g., bottom) may be thicker than each layer (e.g., layers 224 , 226 ) on the opposite (e.g., top) side.
  • solder mask 232 may be much thicker than solder mask 220 .
  • solder mask 220 may have a height of 16 ⁇ m-30 ⁇ m exclusive while solder mask 232 may have a thickness in the range of 30 ⁇ m-60 ⁇ m.
  • the specific heights of buildup layers and solder masks are provided only as examples, to highlight the relative thicknesses of buildup layers. Other embodiments may of course use thickness values outside the ranges specified.
  • thicker layers and solder masks help mitigate warping in package 200 .
  • FIG. 6 depicts a cross-sectional view of an integrated circuit package 200 ′ exemplary of another embodiment of the present invention.
  • Package 200 ′ may be substantially similar to package 200 , except for the presence of a plurality of rings 240 provided to help reduce warping.
  • Like parts in FIG. 5 and FIG. 6 are substantially similar in structure and function, and are labeled with like numerals.
  • a prime (′) symbol distinguishes parts in FIG. 6 from its counterparts in FIG. 5 , and will not be discussed further.
  • core 218 or core 218 ′ may be formed from a material having a low coefficient of thermal expansion (CTE), which helps mitigate warping.
  • CTE coefficient of thermal expansion
  • Materials may have linear coefficients of thermal expansion (denoted ⁇ 1 , ⁇ 2 ) in perpendicular in-plane directions.
  • Exemplary materials may include those with coefficients of thermal expansion less than about 15 ppm/° C. (e.g., ⁇ 1 , ⁇ 2 5-12 ppm/° C.), glass-cloth reinforced resins having high glass transition temperature (Tg) of about 200° C.-240° C., and the like.
  • Rings 240 may be formed by depositing metal (e.g., copper) of suitable thickness on one or more of buildup layers 224 ′, 226 ′, 228 ′ or core 218 ′, as part of (or after) forming a respective conductive layer.
  • metal e.g., copper
  • Various ways of embedding stiffener rings within semiconductor packages are well known to those of ordinary skill in the art, and may be used to form rings 240 .
  • rings 240 may be formed together with conductive traces 212 during circuit formation stage.
  • Rings 240 may take on the shape of the package 200 ′. That is, a plan view of rings 240 may be substantially the same as an outline of the circumference of package 200 ′ as viewed from above.
  • Rings 240 may be made of similar material as the traces themselves, (e.g., copper). Conveniently, this allows rings 240 to be formed at the same manufacturing step used to form conductive traces on a buildup layer. In alternate embodiments, other materials of suitable strength may also be used to construct rings 240 .
  • embodiments of the present invention may include exemplary substrates having many different combinations of buildup layers on either side of the core.
  • the substrates with asymmetric buildup layers discussed above are only exemplary and not limiting.
  • Other embodiments of the present invention may generally have buildup designs of the form m/k/n where m and n, are positive integers and m ⁇ n (e.g., m>n>0).
  • Semiconductor device manufacturing using exemplary methods discussed above may be performed for each die, or at the wafer level.
  • wafer level packaging instead of applying the methods discussed to a substrate for an individual die, the packaging methods are applied to a substrate for an entire fabricated wafer at once. As a last step, the substrate and wafer are cut into individually packaged semiconductor packages ready for assembly onto an external wiring board.
  • top and ‘bottom’ used to refer to opposite surfaces or sides of the core correspond with the illustrations of exemplary embodiments, and may thus be interchanged, depending on the orientation of the figures.
  • Embodiments of the present invention may be used in a variety of applications including the manufacture of DRAM, SRAM, EEPROM, flash memory, graphics processors, general purpose processors, DSPs, and various standard analog, digital and mixed signal circuit packages.
  • Exemplary methods and substrates may be applied to constructing printed circuit boards (PCB) or printed wiring boards (PWB) as well as carrier substrates for integrated circuit packages.
  • PCB printed circuit boards
  • PWB printed wiring boards
  • Embodiments of the invention may thus be used in motherboards, daughter cards, memory modules, peripheral expansion cards (e.g., graphics cards, network interface cards, sound cards), and the like.
US12/533,569 2009-07-31 2009-07-31 Method of manufacturing substrates having asymmetric buildup layers Abandoned US20110024898A1 (en)

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EP10803777.1A EP2460393B1 (en) 2009-07-31 2010-07-28 A method of manufacturing substrates having asymmetric buildup layers and substrates having asymmetric buildup layers
JP2012521917A JP5723363B2 (ja) 2009-07-31 2010-07-28 非対称なビルドアップ層を有する基板を製造する方法
PCT/CA2010/001174 WO2011011880A1 (en) 2009-07-31 2010-07-28 A method of manufacturing substrates having asymmetric buildup layers
KR1020117031056A KR101633839B1 (ko) 2009-07-31 2010-07-28 비대칭 빌드업 층들을 가지는 기판의 제조 방법
CN201080034121.8A CN102656955B (zh) 2009-07-31 2010-07-28 制造具有不对称积层的基板的方法
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