WO2000079849A1

WO2000079849A1 - High performance ball grid array substrates

Info

Publication number: WO2000079849A1
Application number: PCT/US2000/015885
Authority: WO
Inventors: Gordon Smith; Nancy M. W. Androff; Marc Hein; Michael A. Petti; Jeffrey T. Gotro
Original assignee: Isola Laminate Systems Corp.
Priority date: 1999-06-18
Filing date: 2000-06-09
Publication date: 2000-12-28
Also published as: WO2000079849A9

Abstract

Electronic substrates and printed circuit boards prepared from the electronic substrate, and more particularly, to methods and apparatuses for providing high density printed circuit substrates.

Description

TITLE: High Performance Ball Grid Array Substrates

BACKGROUND OF THE INVENTION

(1) Field of the Invention

The present invention concerns electronic substrates and printed circuit boards prepared from the electronic substrate, and more particularly, to methods and apparatuses for providing high density printed circuit substrates.

(2) Description of the Art

Traditionally substrates used in printed wiring board manufacturing and in creating chip packaging interposers, consist of glass reinforced resin composite laminates capped with copper foil sheeting. Laminates are manufactured by pressing copper foil sheets to a glass cloth reinforced resin. The copper foil serves as a seed layer for forming circuits on the laminate surface. Foils typically used within high density circuit formation are electroplated films formed with a rough surface to embed "teeth" into the laminate enhancing the electroplated foil adhesion. However, this rough surface has a disadvantage; the foil roughness and embedded copper impose difficulties in etching circuits. Etching copper between fine circuit traces is difficult do to the roughness approaching the dimensions of the circuit. In addition, to completely remove the teeth, longer and more severe etch conditions are required, impacting line quality.

These manufacturing problems are even more troublesome as circuit size reduction becomes more important. Ball grid array substrates have become a major packaging method in the last few years. Specifically, the plastic ball grid array (PBGA) has become widely accepted as a packaging substrate for high I/O wire bonded or flip chip assemblies. Typical PBGA substrates are made using a two-sided high performance laminate, such as bismaleamide triazine (BT). The PBGA market consists of two-sided substrates, or layer pairs, with the IC device mounted on one side, and an array of solder balls on the opposite side.

Typically PBGA's have two circuit layers on each side of the substrate. However, with the number of I/Os for integrated circuits on the increase, a need has arisen for multi- l layer PBGA. This need is due to the large amount of circuit traces that need to be routed away from the bond fingers, or in the case of the flip chip, escape from under the chip. Thus, there is a need for multi-layer PBGA's that are reliable, that have a low profile, and that are manufactured in a cost effective and reproducible method.

SUMMARY OF THE INVENTION In one aspect, this invention includes a method for using layer pairs and thin conductive metal films to reliably manufacture electronic substrates having multiple circuit layers. In another aspect, this invention includes a method for manufacturing thin and reliable multi-layer PBGA's.

In another aspect, this invention includes layer pairs including ultra-thin circuit layers. In one embodiment, this invention includes layer pairs useful in the manufacture of electronic substrates. The layer pairs comprise a core including a resin impregnated reinforcing material having a first surface and a second surface, a first conductive metal layer adjacent to the core first surface, and a second conductive metal layer adjacent to the core of second surface wherein the core first surface and core second surface each have a roughness of no more than 6.0 microns.

In another embodiment, this invention includes methods for manufacturing an electronic substrate. The method includes the steps of forming a core having a first surface, a second surface, a first circuit associated with the first surface and a second circuit associated with the second surface. A first layer of resin coated conductive foil further comprises a b-stage resin layer, a conductive metal layer, and a c-stage resin layer located between the b-stage resin layer and the conductive metal layer is applied to the core first surface such that the b-stage resin layer is associated with the first circuit. A second layer of resin coated conductive foil further comprising a b-stage resin layer, a conductive metal layer, and a c-stage resin layer located between the b-stage resin layer and the conductive metal layer is applied to the core second surface such that the b-stage resin layer is associated with the second circuit to form an uncured laminate. The uncured laminate is then laminated under heat and pressure. A third circuit is formed on the conductive foil layers associated with the first resin coated conductive foil layer of the cured laminate and a fourth circuit is formed on the conductive foil layer associated with the second resin coated conductive foil layer of the cured laminate to form a multi-layer laminate.

In still another embodiment, this invention includes a method for manufacturing an electronic substrate. The method includes the steps of forming a core having a first surface, a second surface, a first circuit associated with the first surface and a second surface associated with the second surface. A first layer of resin coated conductive foil further comprising a b- stage resin layer, a conductive metal layer, and a c-stage resin layer located between the b- stage resin layer and the conductive metal layer is applied to the core first surface such that the b-stage resin layer is associated with the first circuit. A second layer of resin coated conductive foil further comprising a b-stage resin layer, a conductive metal layer, and a c- stage resin layer located between the b-stage resin layer and the conductive metal layer is applied to the core second surface such that the b-stage resin layer is associated with the second circuit to form an uncured laminate. A blind via is formed in the first resin coated conductive foil layer, the second resin coated conductive foil layer, or in both the first resin coated conductive foil layer and the second resin coated conductive foil layers. Third and fourth circuits are formed on the first and second resin coated conductive foil layers by the further steps of; (i) applying a photoresist layer to the first and second conductive foil layers; (ii) exposing and developing the photoresist layers to expose a first portion of the first and second conductive foil layers and to cover a second portion of the first and second conductive foil layers; (iii) electroplating the exposed first portion of the first and second conductive foil layers and at least one blind via with a conductive metal; (iv) removing the resist layer from the first and second conductive foil layers to expose the second portion of the first and second conductive soil layers; and (v) flash etching the laminate to remove the exposed second portion of the first and second conductive foil layers from the laminate.

DESCRIPTION OF THE FIGURES

Figures 1A and IB, show a conventional process for preparing a base laminate. In Figure 1A, a conductive layer 2 such as copper is first electroplated onto a drum 4. The surface 6 of the conductive material 2 that is adjacent to the drum 4 is typically smooth, while the surface 8 of the conductive layer 2 that is on the opposite side of the drum 4 is typically matted. In addition, the matted surface 8 of the conductive layer 2 is typically treated by adding nodules or pinning teeth to the surface 8 so as to enhance the bond strength of the conductive layer 2 to a dielectric (see Figure IB) during the lamination process. The surface roughness μ of surface 8 is typically greater than 6.0 microns (peak-to-valley, R_ZDIN) as measured with a contact profilometer. A silane coupling promoter 10 is subsequently attached to the matted surface 8 to further enhance the bond strength of the conductive layer 2. As shown in Figure IB, the treated conductive layer 2 is then laminated onto one or both sides of a dielectric layer 12 under heat and pressure (only one layer 2 is shown as being attached to the dielectric layer 12 in Figure IB) to form a base laminate 14. An etch resist mask 16 may be patterned onto the base laminate 14 as shown in Figure IC. The resist mask 16 is then patterned, as shown in Figure ID, and the conductive layer 2 is subsequently etched to provide a substrate 18 as shown in Figure IE. The conductive layer 2 is typically 5-18 μm thick. The etch resist is subsequently removed to provide the circuitized substrate as shown in Figure IF. Figures 2 illustrates one embodiment of an integrated circuit package 20 provided in accordance with the principles of the present invention.

Figures 3 A-H illustrate one embodiment of a process for forming high density circuit substrates 26.

Figure 4A illustrates a side view of one embodiment of a polymer coated base laminate 100 provided in accordance with the principles of the present invention. Figure 4B illustrates a side view of a second embodiment of a polymer-coated base laminate 100a provided in accordance with the principles of the present invention. Figure 4C illustrates a side view of a second embodiment of a resin-coated laminate 100c provided in accordance with the principles of the present invention. Figures 5-10 are cross-sectional illustration of a metal-clad intermediate products useful in the method of this invention. Figures 11A-11B are steps of methods of this invention for manufacturing an electronic substrate and preferably an interposer that includes multiple circuitry layers;

Figure 12 is an electronic substrate manufactured by the methods of this invention; and Figures 13 A and 13B depict interposer configurations prepared by the methods of this invention.

DESCRIPTION OF THE CURRENT EMBODIMENT The present invention relates to electronic substrates manufactured from layer pairs which include highly stable dielectric cores. The present invention also relates to electronic substrates, and in particular, multilayer interposers that are manufactured from a layer pair and two or more layers of resin coated conductive metal and preferably RCC™ resin coated foil. The present invention also relates to electronic substrates manufactured from a layer pair and two or more dielectric layers including ultra-thin conductive layers.

Ultra-stable core materials are disclosed in co-pending U.S. Patent Application Serial No. 09/123,952, filed in July 1998, the specification of which is hereby incorporated herein by reference in its entirety. The cores or base laminates useful in the present invention have first and second surfaces having a RJDIN surface roughness of no greater than 6.0 microns. A conductive layer such as copper is attached to the core. In an alternate embodiment, an adhesion layer is first attached to the core. Subsequently, a conductive layer is deposited over the adhesion layer.

The choice of glass cloth is an important feature of the base laminate. A balanced weave construction provides isotropic properties in the plane (uniform CTE in both the X and Y direction). The preferred embodiment involves the use of CS 6060 glass cloth manufactured by Hexcel-Schwebel. This fabric has 60 X 60 ends per inch with a nominal fabric thickness of 0.0019 inches. The yarn bundles are very uniform in both the warp and fill (X and Y) directions. During impregnation of the 6060 glass fabric, the resin easily wets the glass bundles and exhibits excellent penetration into the glass fiber bundles. Good penetration during impregnation results in a prepreg with very low levels of cigar voids (cylindrical voids in the intends of the fiber bundles). Low levels of prepreg cigar voids produce a subsequent laminate with very low void content. Consistent impregnation (low levels of cigar voids) also has an added benefit of providing a laminate with very consistent resin content. The dielectric constant depends on the ratio of the resin-to-glass, and a laminate with a very consistent resin content will exhibit a stable dielectric constant in the plane of the laminate. Thus stability is important for signal speed integrity across the circuit. To yield a very uniform 0.002" laminate, 56-58% resin is required. During the impregnation process, care is taken to control resin content very closely.

During mechanical drilling (using a 4-6 mil diameter drill bit), the geometry of the glass bundles is an important parameter of hole wall quality. If the yarn knuckles are too thick (or occupy a large area), the drill has a higher propensity to deflect off the knuckles causing a non-uniform hole. Fabrics with uniform, small cross-sectional areas (such as 6060 style fabrics) in the warp and fill direction exhibit more consistent drilling. Additionally, during laser drilling, the smaller fiber bundle cross-sectional area leads to higher drilling rates and to more uniform hole walls.

In another embodiment, of this invention, the reinforcing material used in the core will be a 3070 style glass cloth (from Hexcel-Schwebel). This woven glass cloth is also a balanced weave with a yam count of 70 x 70 ends per inch having a nominal thickness of 0.0031 inches.

The use of glass cloth coated with a coupling agent is preferred in order to minimize measling and blistering. The optimal coupling agent was determined after conditioning the laminate sample for 96 hours at 121°C, 2 atmospheres and optically inspecting for measling. CS309 (from Hexcel-Schwebel) was found to give the optimum results after pressure cooker testing. Selection of the correct coupling agent is required to minimize the potential for Conductive Anodic Filament (CAF) formation. In the absence of a tenacious bond between the resin and the glass fiber and under the application of humidity and bias, copper filament growth can occur along the fiber bundles. The choice of the coupling agent is key to providing a high level of CAF resistance. Low propensity for CAF formation is a key functional parameter for substrates used in packaging applications.

Figure 2 illustrates one embodiment of an integrated circuit package 20 made using the layer pair cores of this invention. Package 20 may include an integrated circuit 22 that is mounted to a first surface 24 of a substrate 26. The integrated circuit 22 may be mounted to the substrate 26 with a plurality of solder bumps 28. The attachment of the integrated circuit

22 to the substrate 26 may be performed with a process commonly referred to as the flip chip solder connection. Although a flip chip solder package is described herein, it is understood that the integrated circuit 22 may be attached to the substrate 26 with bond wires or tape automated bonding (TAB) or by other techniques as known in the technology.

A plurality of contacts 30 may be attached to a second surface 32 of the substrate 26. The contacts 30 may be solder balls that are reflowed onto the substrate 26. The contacts 30 may be subsequently attached to a printed circuit board (not shown). Substrate 26 may have surface pads, routing traces, power/ground planes and vias that interconnect the solder bumps 28 to the contacts 30. Substrate 26 may also have multiple layers of routing traces, power/ground planes and vias to interconnect the integrated circuit 22 to the contacts 30. Figures 3A-H illustrate an exemplary process for forming a high density printed circuit substrate 26. The high density printed circuit substrate 26 comprises a base laminate 50, as shown in Figure 3A. The base laminate 50 is a dielectric layer. A via opening 52a and/or 52b may be formed in the base laminate 50, as shown in Figure 3B. Via opening 52a and/or 52b may be mechanically drilled (e.g., via opening 52a) or laser drilled (e.g., via opening 52b) in the base laminate 50. A typical diameter of a laser drilled hole is in the range of 10-100 μm, while a typical diameter of the mechanically drilled hole is approximately 0.004 inches/100 μm or larger. As shown in Figure 3C, a first conductive layer 54 may be attached to the base laminate 50. In one embodiment, first conductive layer 54 is an adhesion layer. Examples of such an adhesion layer includes chromium, titanium, tungsten, zinc and nickel. It is understood that other types of adhesives known in the art may also be used. The first conductive layer 54 may be deposited in any manner generally known in the art, including various additive, semi-additive or subtractive techniques. Deposition of the first conductive layer 54 may be performed via processes such as vacuum metallization, sputtering, ion plating, chemical vapor deposition, electroplating, electroless plating, etc.. In one embodiment, the first conductive layer 54 has a thickness in the range of 50-200 Angstroms. In another embodiment, the first conductive layer 54 may be simultaneously attached onto both surfaces of the base laminate 50. In an alternate embodiment, the first conductive layer 54 is simultaneously attached onto both surfaces of the base laminate 50 and into the via opening 52a and/or 52b. Subsequently, a second conductive layer 56 is attached to the first conductive layer 54, as shown in Figure 3C. As in the case of the first conductive layer 54, the second conductive layer 56 may be deposited in any manner generally know in the art, including various additives, semi-additive or subtractive techniques. Deposition of the first conductive layer 56 (and other conductive layers described herein) may be performed via processes such as vacuum metallization, sputtering, ion plating, chemical vapor deposition, electroplating, electroless plating, etc.. The conductive layers 54 and 56 may be formed of single metal layers or composite layers formed by different processes, conductive polymers and the like. Examples of the second conductive layer 56 includes copper, gold, and aluminum. In one embodiment, the first conductive layer 56 is an adhesive layer and the second conductive layer is a seed layer. In another embodiment, the second conductive layer 56 is greater than 500 Angstroms.

In a further embodiment, the thickness of second conductive layer 56 is in the range of 50-10,000 Angstroms. The second conductive layer 56 may be deposited on one or both sides of the base laminate 50. Alternatively, the second conductive layer 56 may be simultaneously attached (e.g., vacuum metallized or sputtered) onto both surfaces of the base laminate 50 and into the via opening 52a and/or 52b. In another embodiment a conductive layer having a thickness of from 50-10,000 Angstroms may be applied to the base laminate 50 using an ultra-thin conductive metal layer that is formed by vapor deposition or sputtering of the conductive metal on a polymeric or metal carrier film which has been coated with an organic polymeric release agent. The conductive metal layer is then applied to a surface of base laminate 50. Then the carrier film is then separated from the polymeric release agent, leaving the conductive metal layer bonded to the substrate. Such ultra-thin conductive metal articles are described in U.S. patent application S.N. 09/075732, filed on May 11, 1998, the specification of which is incorporated herein by reference. Using this approach, base laminate circuits or circuit seed layers in the range of 0.005 μm to 1.0 μm (50 to 10,000 Angstroms) become practical. In still another embodiment, a direct metallization process using an immersion Palladium catalyst, may be implemented to attach a single conductive layer such as copper (instead of two conductive layers, e.g., the first and second conductive layers 54 and 56), onto one or both surfaces of the base laminate 50.

In this alternate metallization process, a first conductive layer 54 such as the adhesion layer (e.g., chromium, tungsten, titanium, nickel or zinc) is not required to facilitate bonding of the second conductive layer 56 (e.g., the seed layer) to the base laminate 50.

As shown in Figures 3D and 3E, a resist 58 such as a photoimageable dry film resist may be patterned onto the second conductive layer 56 (or to the single conductive layer that was attached to the base laminate 50 using the direct metallization process). The plating resist 58 can be patterned with conventional photolithographic techniques by applying a layer of resist and subsequently removing portions of the resist material, as shown in Figure 3E.

In one embodiment, the portions of the resist 58 may be masked and the excess portions of the resist 58 may be removed using appropriate developing solutions such as aqueous or solvent based developing solution. An additional layer of conductive material 60, for example, copper, may be deposited (e.g., electroplated) onto the areas of the second conductive layer 56 not covered by the resist 58, as shown in Figures 3F-1 and 3F-2, to facilitate fine line geometry circuits. In one embodiment, as shown in Figure 3F-1, the via opening 52a and/or 52b can either be plated to a specified copper wall thickness (typically 0.001 inch), or completely plated closed, yielding a solid post for future joining processes, as shown in Figure 3F-2. Typically, the smaller laser drilled holes are better candidates for plating the via openings completely closed.

As shown in Figure 3G, the resist 58 is then removed. Next, a flash etching process is implemented. The purpose of this is to remove the second conductive layer 56 (which for example, is the copper seed layer) or for removing the single conductive layer (which for example, is the copper seed layer). Subsequently, the substrate 26 is subject to an etch solution to remove the first conductive layer 54 (which, for example, is a chromium etch solution for removing the 50-200 Angstroms of chromium exposed after the copper is removed). Removal of the chromium ensures electrical insulation between the plated circuit traces. The circuitization process described above may be applied to one or both surfaces (for example, surface 24 and/or 32 of the substrate 26.

Through the use of the build up processes as described above and as shown in Figures 3A-3H is provided a circuit substrate having reduced copper thickness. Accordingly, conventional techniques for providing circuit substrates, which includes lamination of electrodeposited copper foils to thermosetting resin-cloth prepregs under heat and pressure, may be avoided. Such conventional techniques typically provide copper layers that are 5-18 μm thick. However, using the technique described with respect to Figures 3A-3H, copper layers of less than 5 μm thick may be achieved. In alternate embodiments, copper layers of 1-3 μm may be achieved. Figure 4A illustrates a side view of a useful base laminate 100. In one embodiment, polymer-coated base laminate 100 comprises a base laminate 102 that includes at least one ply of a base laminate layer (for example, any one of 102-102J. Examples of the base laminate layer (e.g., any of 102,-102_n) include a prepreg material (b-staged material). In an alternate embodiment, the polymer-coated base laminate 100 comprises a base laminate 102 that includes a plurality of base laminate layers 102,-102_n which are selected and interleaved to form the base laminate 102. In one embodiment, the base laminate 102 is sandwiched between two removable layers or removable release films 104a and 104b. In one embodiment, the removable layer 104a or 104b is a removable polymer film. Examples of the polymer release film (e.g., 104a and/or 104b) include any one of: a polypropylene film, a polyimide film, a film constructed from fluorinated resins, polyetherimides, or a polyphenylene sulfide film. However, it is understood that other polymer release films known to one of ordinary skill in the art may be used.

In an alternate embodiment, the removable layer 104a and/or 104b may be a conductive layer or a conductive release sheet. The conductive layer may be a conductive metallic layer or a conductive non-metallic layer. Examples of the conductive metallic layer includes electrodeposited copper or aluminum, which has its shiny surface (or the surface adjacent to the drum during fabrication) pressed to the base laminate 102. The conductive layer (e.g., 104a and/or 104b) may also be fabricated from rolled copper or rolled aluminum, with the smooth surface of either material pressed against the base laminate 102. Examples of the non- metallic conductive layers include layers comprised of semiconductor material. The base laminate's 102 thickness and physical properties are controlled by the number and type of material used to fabricate the base laminate layers 102,-102_n. For example, a 0.004-inch base laminate 102 may comprise 2 plies of prepreg material (for example, 102, and 102₂), where each ply of prepreg layer (e.g., 102, and 102₂) comprises, for example, resin impregnated into a single ply of balanced cloth that is sandwiched between two removable layers or release films.

The release film 104a and/or 104b serves two functions: 1) it provides the base laminate 102 with a very smooth surface after lamination, and 2) it provides a protective cover for the base laminate 102 until just prior to use in the circuit board fabrication line. In one embodiment, the surface roughness of the base laminate 102 of the present invention is no greater than 6.0 microns (peak-to-valley, R_ZDIN), as measured with a contact profilometer. In a further embodiment, the surface roughness μ of the base laminate 102 is 0 microns < μ < 3 microns (peak-to-valley, R_ZDIN), as measured with a contact profilometer. It should be noted that the use of other types of surface roughness measurement techniques (e.g., a laser profilometer) will yield surface roughness ranges that vary compared to the contact profilometer data. Such variations are due to the different surface roughness measurement techniques employed, but can be correlated to measurements provided by a contact profilometer. For example, as discussed in an earlier section, the surface roughness g of surface 8 (Figures 1A and IB) of a conventional substrate is typically greater than 6.0 microns (peak-to-valley, R_ZDIN), as measured with a contact profilometer. The surface roughness μ of the base laminate 102 of the present invention is no greater than 6.0 microns (peak-to valley, R_ZDIN), as measured with a contact profilometer. It is understood that other types of surface roughness measurement techniques, while providing surface roughness measurements that vary compared to that measured by a contact profilometer, will still yield surface roughness measurements correlated to that provided by the contact profilometer.

It has been determined that the use of polyimide or polypropylene as the removable layer 104a and/or 104b provides two optimal features in the base laminate 102: very smooth high gloss surfaces with no or minimal adhesion of the release film 104a and/or 104b to the base laminate layer 102,102.. It has also been determined that samples produced with polar polymers such as nylon, polyethylene naphthalate (PEN), and polyetheylene terephthalate (PET) have adhered to the finished laminate and could not be removed from the substrate.

The release film 104a and or 104b may be removed from the outer surfaces of the base laminate 102 prior to drilling. In one embodiment, when using a polymer release film such as thermoplastic release sheets that melt at the press temperature, sacrificial sheets 106a and/or 106b such as copper foils or non-polar polymer films may be placed between the polymer release film (e.g., 104a and/or 104b) and the press plates 110a and 110b, as shown in Figure 4B. The use of the sacrificial sheets 106a and/or 106b such as electrodeposited copper, rolled copper or aluminum, or a polymer film that does not melt at press temperature, prevents the polymer release film (e.g., 104a and/or 104b) from adhering to the press plates 110a and 110b during lamination. The sacrificial sheets 106a and/or 106b and the polymer release film (e.g., 104a and/or 104b) may be subsequently peeled off the base laminate 102 to provide a base laminate 102 with a smooth topography.

In another embodiment, as shown in Figure 4C, a single layer of adhesive 108a and/or 108b attached between the base laminate 102 and the copper layer 114a and/or 114b. One example of such an adhesive is a single-pass resin layer such as that provided by Mitsui under the tradename Multifoil™. During lamination, the adhesive layer 108a and/or 108b softens, flows and cures forming a fully cured laminate 100c with a smooth surface. After lamination, the copper layer 114a and/or 114b can either be etched to the desired thickness (typically 5-9 microns), or completely removed. The resulting surface will have the surface roughness of the copper layer 114a and/or 114b. To obtain a smooth surface, a copper layer 114a and/or 114b with a very low profile tooth structure may be used.

Thus, to provide each base laminate layer 102„...,102_n, a balanced cloth (i.e., a cloth having a uniform weave) is impregnated with a resin having a glass transition temperature (Tg) of greater than 180°C, a dielectric constant in the range of 2.9-3.1, and which is cured to provide base laminate layer 102„...,102_π. The resulting base laminate layer 102,,..., or 102_n is stress relieved; has a reduced dissipation factor in the range of 0.008-0-015; a low moisture content in the range of 0.4-0.6% by weight; and a low dielectric constant in the range of 3.2- 3.7. The resulting base laminate layer 102,,..., or 102_n also has a controlled CTE that is closely matched to the CTE of the second conductive layer 56 or 82 (e.g., a copper seeding layer) that is subsequently attached to the base laminate 102.

In addition, the cloth that is selected also has a controlled coefficient of thermal expansion (CTE) that is closely matched to that of the second conductive layer (e.g., the copper layer) 56 (of Figure 3C). The CTE for copper is 17 parts per million (ppm). In one embodiment, the CTE of the cloth is in the range of 15-20 ppm. By providing a base laminate that is made from a cloth having a controlled CTE that is closely matched to that of the second conductive layer (e.g., the copper layer) 56 (of Figure 3C), and by using the removable release film 104a and/or 104b during the manufacture of the base laminate 50 or 102 (thus avoiding the need to use the conventional techniques for providing circuit substrates, which includes lamination of electrodeposited copper foils to thermosetting resin-cloth prepregs under heat and pressure), the resulting circuit substrate 26 or 26a is stress-relieved. In addition, post baking of the laminate 100 or 100a may also be implemented to provide additional stress relief.

In one embodiment, the cloth may be constructed from a material that is easily ablatable by laser, so as to facilitate subsequent laser drilling of via openings in the laminate 50 or 102. Such a cloth may be obtained from: (1) by using an ultra-violet (UN)-absorbable fiber, (2) by coating the cloth with a UV absorbable substance, (3) by coating the cloth with an enhanced thermal conductivity substance; (4) by using a non-woven glass in which the diameter of the fiber is smaller than the hole to be lased; or (5) by using a filler material has a small diameter.

Upon selection of the appropriate cloth, a coupling agent is applied to the cloth to minimize measling and blistering of the laminate 50 or 102 after exposure to high temperature and humidity. Selection of the appropriate coupling agent is required to minimize the potential for Conductive Anodic Filament (CAF) formation.

Upon selection and conditioning, the cloth is impregnated with a resin solution. The term "impregnation" as used herein includes solution casting, extrusion or spinning of the resin solution into the cloth. One method for attaching the resin solution to the cloth is to pass the cloth through a resin bath containing a selected resin solution. In one embodiment, the resin solution comprises a resin, a solvent which lowers the viscosity of the resin for better penetration of the cloth, a catalyst and additives, all of which may be premixed in a container and subsequently pumped into the resin bath. In one embodiment, a resin solution includes a polymer having a high glass transition temperature (Tg) upon cure. In one embodiment, Tg of the cure is greater than 180°C. An example of the resin used in the resin solution includes an epoxy resin. It is understood that other resins with the properties described herein (i.e., a high

Tg, a low dielectric constant, and appropriately cured to provide a base laminate with a low moisture content) may be used. In one further embodiment, the resin solution is cured with an agent that does not contain dicyandiamide (DICY). The use of a non-DICY curing agent leads to a cured resin that exhibits significantly lower moisture absorption compared with standard epoxy resins. Such low moisture absorption is a key feature of the substrate 26 or 26a for providing a base laminate 102 with enhanced performance during accelerated moisture testing. Such a non- DICY curing agent provides a laminate structure with a low moisture content, a reduced dielectric constant and a reduced dissipation factor, as compared with a standard FR4 epoxy- based laminate. In one embodiment, the cured resin has a dielectric constant in the range of 2.9-3.1.

During impregnation of the cloth, the appropriate resin solution easily wets the bundles of the cloth, and exhibits excellent penetration into the fiber bundles. Such good resin penetration during impregnation results in a base laminate layer with very low levels of cigar voids, which subsequently results in a base laminate 102 with very low void content. In addition, consistent impregnation of the cloth by the resin solution results in the added benefit of providing a laminate 102 with a very consistent resin content. The dielectric constant of the resulting laminate 102 depends on the ratio of the resin-to-fiber, and a laminate with a very consistent resin content will exhibit a stable dielectric constant in the plane of the laminate. This stability is important for signal speed integrity across the circuit. For example, to yield a very uniform 0.002 inch laminate 102, the base laminate 102 consists of a single ply of glass cloth having 58-59% of resin by weight. In one embodiment, for enhanced surface smoothness (at a slight increase in thickness), the resin content of the base laminate layer may be increased to the range of 60-64% of resin by weight. During the impregnation process, care is taken to control resin content very closely. This is accomplished by pulling the cloth through two counter rotating metering rolls. The resin-impregnated cloth is then dried in a drying tower for a duration of 2 to 3 minutes at approximately 350°F. The heat in the drying tower removes the solvent in the resin solution. The cloth is then subjected to a further period of heating at approximately 350°F and for a duration of 1 to 3 minutes, to partially cure the resin impregnated within the cloth. The resulting base laminate layer (or prepreg material) 102' may then be cut to the required size to provide each ply or each base laminate layer 102, ... 102_n of base laminate 102.

Subsequently, multiple plies of prepreg are laminated using heat and pressure to produce a laminate. The resulting laminate is stable, stress-relieved, has a controlled coefficient of thermal expansion (CTE) that is closely matched to the conductive layer (e.g., copper), has a reduced dissipation factor in the range of 0.008 - 0.015, a low moisture content -in the range of 0.4-0.6% by weight; and a low dielectric constant in the range of 3.2 -3.7.

As shown in Figure 11 A, the base laminate or core 300 will have a first side 302 and a second side 304. A first high density circuit 306 is then manufactured on the core first side 302 and a second circuit 308 is manufactured on the core second side 304 to give a layer pair that is useful in the manufacture of an electronic substrate including multiple circuit layers.

The additional metal layers are applied to the layer pair using resin coated conductive metal layers. The resin coated conductive metal layer may be any resin coated conductive material that is useful in the manufacture of electronic substrates. A preferred resin coated conductive material RCC™ resin coated foil manufactured by AlliedSignal. U.S. Patent No. 5,362,534, the specification of which is incorporated herein by reference, discloses resin coated conductive metals including copper that are useful in this invention.

RCC™ consists preferably of a copper foil 310 with two coatings of a thermosetting resin. One coating is c-staged 312 (completely cured) and the second coating is b-staged 314 (partially cured to allow additional flow, fill and curing during lamination. The RCC™ schematic is shown in Figure 11 A.

The layer pair and/or the resin coated conductive metal layer may include a very thin conductive metal layer. Using very thin conductive metal layers to form circuit traces produces a very thin electronic substrate with reliable circuitry. A description of useful thin metal layer containing resin coated materials are disclosed in co-pending U.S. Patent Application Serial No. 09/075732, filed on May 11, 1998, the specification of which is incorporated herein by reference.

The present invention is directed toward electronic substrates manufactured from very thin metal conductive layers which are formed by vapor deposition or sputtering of the conductive metal on a polymeric film, or onto a metal carrier film which has been coated with an organic polymeric release agent. The metal conductive layer can then be bonded to a printed wiring board substrate, such as an epoxy based laminate. Then the carrier film can be separated from the polymeric release agent, leaving the metal conductive layer bonded to the substrate. Using this approach, conductive metal layers in the range of 0.005 μm to 1.0 μm (50 to 10,000 Angstroms) are practical. In accordance with the present invention, a metal-clad laminate product for use in the manufacture of an electronic substrate including multiple circuit layers can be made including a polymer or metal foil carrier layer, a polymeric release agent layer formed on the carrier film, a very ultra thin metal layer formed on the release agent layer. Shown in Figure 5 is a metal-clad intermediate 210 made in accordance with the present invention. The intermediate 210 is made up of a carrier film 211 to which is applied a polymeric release agent layer 212, onto which is applied a very ultra thin conductive metal layer 213.

Figure 6 is an alternative embodiment of such a metal clad laminate product here designated 220. In the embodiment of Fig. 6, a carrier film 221 has applied to it a polymeric release agent layer 222. Onto the release agent layer 222 is deposited a primary very ultra thin conductive metal layer 223. On top of the primary metal layer 223 is a secondary metal layer

224, also preferably formed by sputtering or vapor deposition.

Shown in Fig. 7 is an alternative embodiment metal clad intermediate 230 is illustrated which includes a carrier film 231, a release agent 232, and a primary very ultra thin conductive metal layer 233. Also deposited on the metal layer 233 is an adhesion layer 235.

Shown in Fig. 8 is another embodiment which includes a metal clad intermediate 240, a carrier film 241, a release agent layer 242, a very ultra thin primary metal layer 243, a secondary metal layer 244 and an adhesive layer 245.

Shown in Fig. 9 an alternative metal clad intermediate 250 is shown which includes a carrier film 251, a release agent layer 252, a very ultra thin primary metal layer 253, and a secondary metal layer 254. This embodiment also includes two layers of resin consisting of a c-stage resin layer 255 and a b-stage resin layer 256.

Shown in Fig. 10 is another alternative metal clad intermediate 260 including a carrier film 261, a release agent layer 262, a primary metal layer 263, a secondary metal layer 264, an adhesion layer 265, and two layers of resin 266 and 267.

These alternative embodiments are illustrated and discussed to exemplify the wide variation in selection and number of layers that can be used to assemble such intermediates.

Preferably, the carrier film comprises a flexible, dimensionally stable material with good tear and chemical resistances. The carrier film should be able to tolerate above-ambient temperatures. Preferably, the carrier film is made of a material having low absorbed moisture and residual solvent, because water and solvents can interfere with the metallization step. Suitable materials include polymeric film or metal foils. A metal foil is preferred because metal foils tend to have high tensile strength at elevated temperatures, low absorbed moisture, and low residual solvent.

The carrier film employed was an electroplated copper foil, a polyimide film or a polyester film. Other metal foils that would make suitable carrier films include rolled or electrodeposited metal and metal alloys including steel, aluminum (Alcoa, AllFoils), and copper (Gould Inc., Oak Mitsui 30 Inc.). It is expected that certain polymeric films would be suitable for the practice of the present invention. Examples of suitable polymeric films include polyesters such as polyethylene terephthalate (Mylar®, DuPont), polybutylene terephthalate and polyethylene naphthalate (Kaladex® ICI America), poly-propylene, polyvinyl fluoride (Tedlar® DuPont), polyimide (Kapton®, DuPont; Upilex UBE® Industries), and nylon (Capran®, AlliedSignal).

The release agent layer (212 in Fig. 5, 222 in Fig. 6, 232 in Fig. 7, etc.) is used to facilitate removal of the carrier film from the very ultra thin metal layer. In order to avoid the problem of picking, which results in incomplete transfer of the very ultra thin metal foil to the substrate under lamination, the release agent layer is designed to peel at the interface between the release agent layer and the layer carrier film. The release agent layer is subsequently removed with the aid of a plasma, an oxidizing environment, intense light, or an appropriate solvent. Preferably, the release agent layer is removed by washing with a solvent, most preferably an aqueous solution. In methods that lack a release agent layer, and in methods that employ a release agent layer that peels at the interface between the release agent layer and the very ultra thin metal layer, incomplete transfer of the metal of the very ultra thin metal foil to the substrate commonly occurs.

The release agent layer (212 in Fig. 5, 222 in Fig. 6, etc.) is made of a polymeric material. Preferably, the release agent layer is an aqueous-soluble material to facilitate its convenience removal from the very ultra thin metal layer. Because photo resists are developed in an alkaline environment, it would be most preferable to use a release agent layer that is soluble in an alkaline aqueous solution. A useful polymer is one that is of a good film- forming material. The polymer can be coated from water with the aid of a volatile base such as ammonium hydroxide to aid solubility. Optionally, the release agent layer comprises a water-soluble surfactant to improve solution wetting properties, and to control drying defects.

A useful release agent layer is applied as a formulation comprising a polyvinylpyrrolidone (PNP) polymer, a surfactant, and water. The wet weight composition of a preferred release agent layer is 10% PNP and 0.5% surfactant. It is expected that formulations containing PNP in the range of from about 1% PNP to about 50% PNP, and surfactant in the range of from about 0% surfactant to about 5% surfactant would also be suitable for the practice of the present invention. Preferred PNPs for use in the present invention have a molecular weight in the range of about 10,000 to about 5,000,000. It is reasonable to expect that a release agent layer comprising a polymer such as acid modified acrylic polymers, acrylic copolymers, urethanes, and polyesters, carboxylic acid functional styrene acrylic resins (S.C.Johnson Wax, Joncryl®), polyvinyl alcohols (Air Products & Chemicals, Airvol®), and cellulose based polymers could be successfully employed in the practice of the present invention. Other suitable water soluble surfactants that could be used to in the release agent layer of the present invention include alkylarylpolyether alcohols, glycerin, ethoxylated castor oil (CasChem Inc., Surfactols® 365), and fluoroaliphatic polymeric esters (3M Corporation, Fluorad® 430). The release agent layer formulation is applied in an amount sufficient to achieve a dry weight of from about lOmg/ft² to about lOOmg/ft², about 0.1 μm to 10 μm in thickness. Preferably, the release agent layer formulation is applied in an amount sufficient to achieve a dry weight of from about 1000mg/ft² to about 400mg/ft², about 1 μm to 4 μm in thickness.

A thin primary conductive metal layer (213 in Fig. 5, 223 in Fig. 6, etc.) can be deposited onto the release agent layer by sputtering using a Desk III (Denton Vacuum), and In-Line 3060 (Denton Vacuum), or a 903M (MRC). It is expected that any sputtering or vapor deposition method known in the art may be successfully used in this invention. The primary metal layer is used as a plating seed layer for subsequent circuit formation. Typical metal layers are made from gold, chrome, or copper. Other suitable metals include, but are not limited to, tin, nickel, aluminum, titanium, zinc, chromium-zinc alloy, brass, bronze, and alloys of the same. The metal layer may be made from a mixture of suitable metals. The primary layer is from about 0.005 μm (50 Angstroms) to about 1.0 μm (10,000 Angstroms) in thickness. Most preferably the primary layer has thickness of from about 0.1 μm to about 0.8 μm (1000 to about 8000 Angstroms).

Optionally, a secondary metal layer (such as layer 224 in Fig. 6, 244 in Fig. 8 or 264 in Fig. 10) may be employed to protect the primary layer from oxidation, to increase adhesion during lamination, or to act as a barrier to metal migration. The secondary layer may be from about 0.001 μm (10 Angstroms) to about 0.1 μm (1000 Angstroms) in thickness. Most preferably the secondary layer has thickness of from about 0.01 μm (100 Angstroms) to about 0.03 μm (300 Angstroms). To form the secondary metal layer, a layer of zinc, indium, tin, cobalt, aluminum, chrome, nickel, nickel-chrome, brass, or bronze is deposited on the first metal layer. Other suitable metals include magnesium, titanium, manganese, bismuth, molybdenum, silver, gold, tungsten, zirconium, antimony, and chromium-zinc alloys. The secondary metal layer prevents the metal in the first metal layer from oxidizing after removal from the metallizing chamber, and increases adhesion to thermosetting resin systems.

Optionally, an adhesion layer (e.g. 235 in Fig. 7, 245 in Fig. 8 etc.) can be applied to the metal layer. The adhesion layer may be employed in order to increase the bond between the metal layers and the substrate layers following lamination. The adhesion layer may be organic, organometallic, or inorganic compounds, and applied to a thickness of 0.0005 μm (5 Angstroms) to 10 μm (100,000 Angstroms). Multiple layers may be used such as an organometallic layer followed by an organic layer. Typically when an organometallic layer is used, such as a silane, the coating will be from 0.0005 μm (5 Angstroms) to 0.005 μm (500 Angstroms) in thickness. When using organic adhesion layers, such as thermoplastics, thermosetting polymers, or mixtures, the coating would be 0.1 μm (1000 Angstroms) to 10 μm (100,000 Angstroms) in thickness.

Useful organometallic compounds include materials based on zirconium, titanium, and silicon. Silicon based organometallics, known as silanes or coupling agents, are widely used and available. The coupling agent may be applied neat or applied after dissolving it in an appropriate solvent. Suitable coupling agents typically have a silane-hydrolyzable end group with alkoxy, acyloxy, or amine functionality, and an organofunctional end group. The hydrolyzable end group reacts with the metal surface while the organofunctional group bonds to the substrate layer to which the metal is laminated. Coupling agents can be subjected to a hydrolysis reaction prior to coating if dissolved in an acidic medium. Useful coupling agents include compounds such as N-(2-aminoethyl)-3aminopropyltrimethoxy silane (Dow Corning, Huls America Inc.) and 3-Glycidoxypropyltrimethoxy silane (Dow Corning, Huls America Inc.). Organic adhesion layers consisting of thermoplastics, thermosetting polymers, or mixtures are appropriate adhesion layers. These adhesives can be based on polyimide resins, epoxy resins, polyester resins, acrylic resins, butadiene rubbers, and the like. One useful adhesive consisting of a polyester epoxy system is available (Cortaulds, Z-Flex™). Resin layers can be applied to the metal layer or to the adhesive layer (if present) in uses where a controlled dielectric thickness is required. Such uses include built up technologies. Typically the resins are thermosetting systems that are coated from an appropriate solvent. After drying, the resins can be cured to a semi-cured state if additional cure is required before lamination to a circuit board. A single semi-cured resin layer can be used. Preferably, two resin layers are used where the first resin layer down (primary layer) is cured to a greater extent than the second resin layer. The first resin layer serves as a controlled dielectric spacing layer and has a thickness of from about 5 to about 500 μms, preferably from about 20 to about 50 μms. Appropriate resin systems include (but not limited to): epoxy resins cured by phenolic or dicyandiamide hardeners, cyanate esters, bismaleimides, and polyimide systems. The second layer can have a different composition than the primary layer; however, to attain good interlayer adhesion, it is preferable that the composition of the second layer is similar to that of the first resin layer. The second resin layer serves as an adhesion layer and as a void filling layer during lamination and has a thickness between 5 and 500 μm, preferably between 20 and 50 μm. By "laminating under suitable lamination conditions" it is meant laminating under appropriate conditions of temperature and pressure for a suitable period of time to adhere the layers together for practical use in making an electronic substrate. The laminates of this invention are typically incorporated into technical components by various plating process including the panel plating and pattern plating processes with or without the introduction of vias into the substrate under manufacture. In fact, the laminates are preferably used in panel and pattern plating process to produce multilayer electrical substrates. The use of laminates of this invention in pattern plating process allows the number of steps in the prior processes to be reduced. Therefore, an aspect of this invention are novel panel plating and pattern plating process using laminates of this invention.

Methods for manufacturing an electronic substrate including multiple circuit layers from a novel combination of electronic substrate components is set forth in Figures 11A-11D. The methods for manufacturing the layer pair begin with the lay-up process. Lay-up involves placing the texturizing layer on the outer surfaces (top and bottom) and interleaving a variable number of plies of prepreg between the texturizing layer. The purpose of the texturizing layer is to impart a surface that enhances bonding of subsequent layers of resin. Texturizing layers may include: (1) MLS copper foil (Oak Mitsui) laminated with the drum side (treated smooth side) laminated against the prepreg; (2) Shiny side of Vτ oz. electrodeposited copper foil laminated against the prepreg to form a smooth surface; (3) Shiny side of 1 oz. electrodeposited copper foil laminated against the prepreg to form a smooth surface; (4)

Polypropylene film; (5) Polyimide film such as UBE Upilex S; and (6) ultrathin copper layer.

The order is from a relatively rough textured surface (#1) to a very smooth, essentially flat surface (6).

The number of plies is dictated by the base laminate thickness. For example, a 0.004" laminate would use 2 plies of 6060 prepreg between the two polymer films. Thicker laminates would use more plies of prepreg in the lay-up stack. During lamination, the polymer release agent softens (and in the case of the polypropylene film, melts) and the prepreg softens, liquifies to a low viscosity fluid, additionally wets the glass cloth bundles, and cures to a high Tg rigid substrate. The polypropylene film has two functions: (1) it provides an ultra smooth surface after lamination; and (2) it provides a protective cover for the substrate until just prior to use in the UltraStable fabrication line. The polypropylene film is manually removed from the outer surface of the laminate prior to laser drilling. When using thermoplastic release sheets that melt at the press temperature, sacrificial sheets of copper foils are placed between the polymer release film and the press plates. The use of the copper foil prevents the polymeric film from adhering to the press plates during lamination.

The press cycle for the lay-up material is dependent on the release film. For polymeric films that do not melt (only soften), the book can be loaded hot at 180°F into a press and the pressure is increased to 400psi. The sample is then ramped at 10°F per minute to 375 °F and allowed to dwell at this temperature for 75 minutes. The sample is then cooled to room temperature for 20 minutes. A post bake can be used after lamination to additionally reduce the laminate stress. For film that melt, a modified press cycle is required to minimize slipping during lamination. For these materials, two different press cycles can be used. For both cycles the samples are loaded at 180°F, the pressure is increased to 400 psi, the temperature is ramped at 10 °F/min to 330°F, and the samples are held at 330°F for 75 min. From this point, two different options were used: 1) post bake 4 hours at 375 °F, or 2) drop pressure to 50 psi, heat at 10°F/minute to 375 °F and hold for 75 min., crash cool to 70°F and hold for 20 minute. A post bake can be added to the second cycle to additionally relieve laminate stress.

According to Figure 11A, base laminate or core 300 may be drilled or undrilled and contains a very dense circuit layer 306 on its first surface 302 and a very dense circuit layer

308 on its second face 304 to form a layer pair 320. Important base laminate properties include surface smoothness, low moisture absorption, flatness during high temperature operations. The desired properties allows for very densely routed circuits.

Separate RCC layers including a conductive metal layer 310 and c-stage layer 312 and a b-stage layer 314 are laminated onto the first high density circuit 306 of layer pair 320 and second high density layer pair 308 of layer pair 320 using a lamination press to form an electronic laminated. During lamination, b-stage layer 314 liquifies slightly and fills spaces 316 between circuits of first and second dense circuit layers 306 and 308 to form a multi-layer intermediate laminate.

Multi-layer intermediate laminate 330 is shown in Figure 11B. It is preferred that the copper associated with the RCC is ultra-thin copper as described above. The external copper layer 310 is either patterned using a suitable photoresist to open copper where a via (interconnection hole between layers of metal) is required (for CO₂ drilling or plasma etching of c-stage layer 314), and directly laser drilled using a YAG laser were drilling through the c-stage layer 314 occurs during the same step as the copper or metal foil drilling. The YAG laser is capable of drilling through the copper foil on the outer layer. The use of very thin copper on the outer layer will enhances the via drilling/lasing speed. Some to all of the vias 332 lased or drilled into the RCC layer penetrate only to the first and second very dense circuit layers 306 and 308. Such vias are known as blind vias 332. After the vias are formed (laser with YAG, CO₂ or plasma) the full panel is subjected to a cleaning process (to clean out debris from the vias) to prepare the panel for electroless copper plating.

Referring to Figures 11C and 11D, a thin copper layer 316 that acts as a seed layer is deposited onto the vias 332 and onto the very ultra thin copper layer 310. The electroless plating process provides a continuous copper metal layer on both sides of the electronic substrate. The seed layer is deposited onto the substrates in thickness ranging from about 1 to about 5 microns. At this point, the methods set forth in Figures 11C and 11D diverge. Referring to Figure 11C, which depicts a pattern plate process, a photoresist layer 334 is applied to both electroless copper plated surfaces 316. A photoresist is applied to electroless copper plated layers 316. The photo resist 334 is exposed and developed to produce an exposed first portion 335 of this ultra thin conductive metal layer corresponding to a circuit patterns 306 and 308 and a covered second portion 336 and 336' of ultra thin conductive metal layer 310 and 310' . The substrate is electroplated to build circuits and surfaces associated with vias 332 and circuits 337. Next, the resist layer 334 is stripped to expose the electroless copper plated thin conductive metal layers 336 and 336' after which the substrate is flashed etched to remove the electroless copper layer 316 and ultra thin copper layer 310 associated that were not built up during the electroplating procedure to give the electronic substrate depicted in Figure 12. Figure 11D is an alternative panel plating process. According to Figure 11D, the entire electroless copper plated seed layer 316 is electroplated with a conductive metal such as copper to give an electroplated layer 329 having a thickness of from about 10 to about 30 microns. A photo resist layer 333 is applied to the electroplated copper layer, exposed and developed to leave photoresist covering vias and other circuit trace locations on the substrate surface. The substrate, as shown in Figure 11D, is the etched to remove the electroplate layer 329, electroless copper plated layer 316 and ultra thin copper layer 310 in the surface locations not protected by the resist layer 333. Finally, the resist layer 333 is removed to give an electronic substrate as shown in Figure 12.

The electronic substrates of this invention are most useful for manufacturing interposers including flip chip interposers and wire bond interposers. Figure 13 A depicts a wire bond interposer and Figure 13B depicts a flip chip interposer. Both interposers include a multi electronic substrate 400 of this invention including multiple circuit layers. The wire bond substrate of Figure 13A includes an integrated circuit 402 associated with electronic substrate 400 on substrate first surface 401. A plurality of bond fingers 410 are located on the surface of electronic substrate 400. A wire bond 412 links each bond finger 410 with integrated circuit 402. Second side 402 of electronic substrate 400 includes one or more ball pads 400. Balls pads 404 may include a solder balls 406. Solder balls 406 are complementary to pads on multi-layer wiring boards. The flip chip interposer depicted in Figure 13B also includes an integrated circuit 402 associated with top surface 401 of electronic substrate 400. Furthermore, the flip chip interposer includes a plurality of ball pads 404 including solder balls 406. However, instead of being associated with circuit traces by wires, the flip chip includes a plurality of bond pads 408 which correspond to a ball grid array 414 associated with integrated circuit 402.

Figure 12 depicts a 6 layer product of this invention. The electronic substrate in Figure 12 includes a first circuit layer 340 and second circuit layer 342 associated with core 300. In addition, the electronic substrate includes a third circuit layer 344 and fourth circuit layer 346 that are the result of building up the resin coated copper layers that were applied to the core first and second surfaces. Additional resin coated copper layers 301 may be associated with third and fourth circuit layers 344 and 346 respectively to produce a product having many circuit layers. To achieve highly dense circuitry in very thin layers, an RCC material including a b- stage/c-stage/conductive foil construction are preferably used to add third, and fourth, and subsequent circuit layers to the structure. The b-stage layer is required to provide for fill between the circuit traces and to provide for uniform flow and leveling across the surface of the base layer pair. The c-stage layer provides a rigid layer that minimizes dimpling and provides for a smooth surface. A smooth surface is required for precise die attach (in the case of wire bonded IC) and a very planar, smooth surface will be an absolute requirement for a flip chip IC bonding approach. For packaging applications the thickness of the coating layers on the RCC are; c-stage layer > 10 microns, but typically in the range of 10-35 microns; b-stage layer > 10 microns, but typically in the range of 10-35 microns. The additional unique aspect is the use of the Ultra Thin release copper as the outer layer, enabling rapid laser drilling with either CO₂ or Nd-YAG lasers.

Using very thin RCC coating layers allows for the manufacture of very thin electronic substrates. The electronic substrates of this invention will typically have a thickness of from about 500 microns to about 300 microns in thickness for a 6 layer substrate. For a 4 layer substrate shown in Figure 12, the substrate thickness will typically range from about 75 to about 400 microns. The very thin substrates of this invention are particularly useful in the manufacture of integrated chip interposers and allow for the manufacture of the low profile integrated circuit containing printed wiring boards.

To make the laminate suitable for optical inspection techniques, the laminate is preferably opaque through the use of a suitable solvent dye. For purposes of this invention, the term "dye" and "ink" are used synonymously to refer to compositions, that when added to the polymer composition, alter the color and light transmission properties of products manufactured from the polymer composition. Dyes that are useful in the compositions and products of this invention are those that do not effect polymer processability, reactivity or end product properties that are colorfast, that do not migrate when the polymer is used to manufacture solid products, that are stable in the resin or varnish composition long enough to provide a shelf life of several weeks, and that do not fade over time. One class of preferred dyes that are useful in the compositions of this invention are solvent based dyes. Solvent dyes are defined as dyes that are soluble in organic solvents. These dyes are based on a wide variety of chemistries ranging from anthraquinones, phthallocyanines, diphenyl methane (for blue), and azine based dyes for blacks. Black dyes may also be obtained through blending of other colors, for example yellow, red, violet (pyraziene, azo, and anthraquinones). Other classes of preferred dyes include nitrogen containing dyes, highly aromatic dyes, and highly aromatic nitrogen containing dyes. The dyes should be present in the compositions and products of this invention in an amount sufficient to enhance the ability of automated optical inspection machines that process the laminate products to recognize flaws and defects in the materials as well as to recognize non-polymer components of products such as circuit traces in a printed circuit board. Thus, the dyes or inks of this invention are present in the polymer compositions of this invention in an amount ranging from about 0.01 to about 10.0 wt % and more preferably in a range of from about 0.01 to about 5.0 wt %.

Claims

What we claim is:

1. A layer pair useful in the manufacture of electronic substrates comprising;

(a) a core including a resin impregnated reinforcing material having a first surface and a second surface; (b) a first conductive metal layer adjacent to the core first surface; and

(c) a second conductive metal layer adjacent to the core second surface wherein the core first surface and core second surface each have a roughness of no more than 6.0 microns.

2. The layer pair of claim 1 wherein the reinforcing material is woven glass cloth having a balanced weave construction.

3. The layer pair of claim 1 wherein the first conductive metal layer and second conductive metal layer each have a thickness no greater than 10,000 Angstroms.

4. The layer pair of claim 1 wherein the first conductive metal layer, the second conductive metal layer or the first and the second conductive metal layers are ultra-thin conductive metal layers.

5. An electronic substrate comprising:

(a) a layer pair useful in the manufacture of electronic substrates the layer pair further comprising;

(i) a core including a resin impregnated woven glass cloth having a balacned weave wherein the core includes a first surface and a second surface;

(ii) a first circuit formed from a first conductive metal layer adjacent to the core first surface wherein the first conductive metal layer has a thickness no greater than 10,000 Angstroms; and

(iii) a second circuit formed from a second conductive metal layer adjacent to the core second surface wherein the second conductive layer has a thickness no greater than about 10,000 Angstroms and wherein the core first surface and core second surface each have a roughness of no more than 6.0 microns;

(b) a third circuit layer divided from the first circuit layer by a first resin layer; and

(c) a fourth circuit layer divided from the second circuit layer by a second resin layer.

6. A method for manufacturing an electronic substrate comprising the step of:

(a) forming core having a first surface, a second surface, a first circuit associated with the first surface and a second surface associated with the second surface;

(b) applying a first layer of resin coated conductive foil further comprising a b- stage resin layer, a conductive metal layer, and a c-stage resin layer located between the b- stage resin layer and the conductive metal layer to the core first surface such that the b-stage resin layer is associated with the first circuit;

(c) applying a second layer of resin coated conductive foil further comprising a b- stage resin layer, a conductive metal layer, and a c-stage resin layer located between the b- stage resin layer and the conductive metal layer to the core second surface such that the b- stage resin layer is associated with the second circuit;

(d) laminating the uncured laminate under heat and pressure to form a cured intermediate laminate; and

(e) forming a third circuit on the conductive foil layers associated with the first resin coated conductive foil layer and a fourth circuit on the conductive foil layer associtaed with the second resin coated conductive foil layer to form a multi-layer laminate.

7. The method of claim 6 wherein a blind via is formed in the first resin coated conductive foil layer, the second resin coated conductive foil layer, or in both the first resin coated conductive foil layer and the second resin coated conductive foil layer.

8. The method of claim 7 wherein the third and fourth circuits are formed on the first and second resin coated conductive foil layers by the further steps of;

(i) applying a photoresist layer to the first and second conductive foil layers; (ii) exposing and developing the photoresist layers to expose a first portion of the first and second conductive foil layers and to cover a second portion of the first and second conductive foil layers;

(iii) electroplating the exposed first portion of the first and second conductive foil layers and at least one blind via with a conductive metal;

(iv) removing the resist layer from the first and second conductive foil layers to expose the second portion of the first and second conductive soil layers; and (v) flash etching the laminate to remove the exposed second portion of the first and second conductive foil layers from the laminate.

9. The method of claim 6 wherein the third and fourth conductive foil layers are ultra-thin conductive metal layers.

10. The method of claim 6 wherein a third layer of resin coated conductive foil further comprising a b-stage resin layer, a conductive metal layer, and a c-stage resin layer located between the b-stage resin layer and the conductive metal layer to the core second surface such that the b-stage resin layer is associated with the third circuit, a fourth layer of a third layer of resin coated conductive foil further comprising a b-stage resin layer, a conductive metal layer, and a c-stage resin layer located between the b-stage resin layer and the conductive metal layer to the core second surface such that the b-stage resin layer is associated with the fourth circuit and a fifth circuit is formed on the conductive foil layers associated with the third resin coated conductive foil layer and a sixth circuit is formed on the conductive foil layer associated with the fourth resin coated conductive foil layer prior to curing step (d).

11. The method of claim 10 wherein a blind via is formed in the third resin coated conductive foil layer, the fourth resin coated conductive foil layer, or in both the third resin coated conductive foil layer and the fourth resin coated conductive foil layer.

12. The method of claim 11 wherein the fifth and sixth circuits are formed on the third and fourth resin coated conductive foil layers by the further steps of; (i) applying a photoresist layer to the third and fourth conductive foil layers;

(ii) exposing and developing the photoresist layers to expose a first portion of the third and fourth conductive foil layers and to cover a second portion of the third and fourth conductive foil layers;

(iii) electroplating the exposed first portion of the third and fourth conductive foil layers and at least one blind via with a conductive metal;

(iv) removing the resist layer from the third and fourth conductive foil layers to expose the second portion of the third and fourth conductive foil layers; and

(v) flash etching the laminate to remove the exposed second portion of the third and fourth conductive foil layers from the laminate.

13. The method of claim 6 wherein the core first surface and core second surface each have a roughness of no more than 6.0 microns.

14. The method of claim 6 wherein the reinforcing material is woven glass cloth having a balanced weave.

15. The method of claim 6 wherein the first and second conductive foil layers are each ultra-thin conductive metal layers.

16. A method for manufacturing an electronic substrate comprising the step of: (a) forming core having a first surface, a second surface, a first circuit associated with the first surface and a second circuit associated with the second surface; (b) applying a first layer of resin coated conductive foil further comprising a b- stage resin layer, a conductive metal layer, and a c-stage resin layer located between the b- stage resin layer and the conductive metal layer to the core first surface such that the b-stage resin layer is associated with the first circuit;

(c) applying a second layer of resin coated conductive foil further comprising a b- stage resin layer, a conductive metal layer, and a c-stage resin layer located between the b- stage resin layer and the conductive metal layer to the core second surface such that the b- stage resin layer is associated with the second circuit to form an uncured laminate;

(d) laminating the uncured laminate to give a cured intermediate laminate;

(e) forming a blind via in the first resin coated conductive foil layer, the second resin coated conductive foil layer, or in both the first resin coated conductive foil layer and the second resin coated conductive foil layer; and

(f) forming third and fourth circuits on the first and second resin coated conductive foil layers by the further steps of;

(i) applying a photoresist layer to the first and second conductive foil layers;

(ii) exposing and developing the photoresist layers to expose a first portion of the first and second conductive foil layers and to cover a second portion of the first and second conductive foil layers; (iii) electroplating the exposed first portion of the first and second conductive foil layers and at least one blind via with a conductive metal;

(iv) removing the resist layer from the first and second conductive foil layers to expose the second portion of the first and second conductive foil layers; and

(v) flash etching the laminate to remove the exposed second portion of the first and second conductive foil layers from the laminate.

17. The method of claim 16 wherein a third layer of resin coated conductive foil layer including a b-stage resin layer, a conductive metal layer, and a c-stage resin layer located between the b-stage resin layer and the conductive metal layer to the core second surface such that the b-stage resin layer is associated with the third circuit; a fourth layer of a third layer of resin coated conductive foil including a b-stage resin layer, a conductive metal layer, and a c-stage resin layer located between the b-stage resin layer and the conductive metal layer to the core second surface such that the b-stage resin layer is associated with the fourth circuit; forming a via in the third resin coated conductive foil layer, the fourth resin coated conductive foil layer, or in both the third resin coated conductive foil layer and the fourth resin coated conductive foil layer; and fifth and six circuit layers are formed on the third and fourth resin coated conductive foil layers according to step (f).

18. An interposer including the electronic substrate of claim 16 having a plurality of ball pads associated with the fourth circuit layer and at least one solder ball associated with a ball pad.

19. The interposer of claim 18 wherein at least one wire bond finger is associated with electronic substrate third circuit.

20. The interposer of claim 18 wherein a plurality of bond pads are associated with electronic substrate third circuit.